Ritesh, there is a document which explains silicon bugs present in the first revision of the chip: http://espressif.com/sites/default/file ... p32_en.pdf
Adding to what ESP_Sprite said about using external SRAM in the current revision:
It is possible to use external SRAM with the first revision and map it into data address space, but care should be taken to access data stored therein in a very
control fashion. Reads and writes should not be interleaved. Memory bars should be placed between reads and writes. Care should be taken not to disrupt read or write patterns due to control flow or interrupts. In general, this can be achieved for some applications such as audio or imaging, where access patterns to data are very predictable (you can know exactly when you are going to read or write something). Placing general purpose heap memory into the external SRAM should not be done in the first silicon revision.
Edit: new silicon revision should become available in February. Allow some time for the new revision to make its way into the supply chain.