hydrabus wrote:I have done some Sigrok (PulseView) capture of the signals (tested with Windows7)
Thanks hydrabus. That's interesting, your IO0 delay is closer to 2ms than the 4ms I was seeing. But same pattern.
Nice work rudi for figuring this one out. However, it's quite strange that this works - when both RTS & DTR are asserted on the Core board it should actually set EN & IO0 high not low. The reason for this is so that normal serial programs (which assert RTS & DTR by default) don't hold the board in reset - it should only pull EN or IO0 low if DTR or RTS is asserted, not when both are.