//  ESP32 - Initialize FPGA SPI
void FPGA_SPI_On(void)
{

   DPORT_SET_PERI_REG_MASK (DPORT_PERIP_CLK_EN_REG, 0x00010000);  //2021  Enable VSPI Clock thru' DPORT
   DPORT_CLEAR_PERI_REG_MASK (DPORT_PERIP_RST_EN_REG, 0x00010000);  //2021 Disable VSPI Reset

	CLEAR_PERI_REG_MASK (GPIO_ENABLE_REG, 0x00840020);	// Disable GPIO O/P's GPIO5, GPIO18, GPIO23 (FPGA_SPI O/P's)
	SET_PERI_REG_MASK (GPIO_ENABLE_REG, 0x08000000);				// Enable GPIO O/P's GPIO27 (FPGA_PWR)
	SET_PERI_REG_MASK (GPIO_OUT_REG, 0x08000000);				// Set GPIO27 to O/P HI (PFGA_PWR ON)

	CLEAR_PERI_REG_MASK (IO_MUX_GPIO18_REG, 0x000067FF);			// IO_MUX O/P - FPGA VSPICLK
	SET_PERI_REG_MASK (IO_MUX_GPIO18_REG, 0x00001800);
	CLEAR_PERI_REG_MASK (IO_MUX_GPIO23_REG, 0x000067FF); 			// IO_MUX O/P - FPGA VSPIMOSI
	SET_PERI_REG_MASK (IO_MUX_GPIO23_REG, 0x00001800);
	CLEAR_PERI_REG_MASK (IO_MUX_GPIO5_REG, 0x000067FF);			    // IO_MUX O/P - FPGA CS
	SET_PERI_REG_MASK (IO_MUX_GPIO5_REG, 0x00001800);
	CLEAR_PERI_REG_MASK (IO_MUX_GPIO19_REG, 0x000065FF);	 		// IO_MUX I/P - FPGA VSPIMISO
	SET_PERI_REG_MASK (IO_MUX_GPIO19_REG, 0x00001A00);
	CLEAR_PERI_REG_MASK (VSPI_CTRL_REG, 0x07B06000);				// Set bit order; std SPI mode
	CLEAR_PERI_REG_MASK (VSPI_CTRL1_REG, 0xF0000000);				// CS_HOLD_DELAY not used. Manual CS
	CLEAR_PERI_REG_MASK (VSPI_CTRL2_REG, 0xFFFFF0FF);				// Timing delay - bits 16 & 17 0x00 for (FPGA), 0x01 for others
	WRITE_PERI_REG (VSPI_CLOCK_REG, 0x00001001);			// SPI Clock f_SPI = 160MHz/(n+1), 0x00001001 = 40MHz (SYSCLK 40MHZ clock)
//	WRITE_PERI_REG (VSPI_CLOCK_REG, 0x80000000);			// SPI Clock f_SPI = 160MHz/(n+1), 0x00001001 = 40MHz (SYSCLK 80MHZ clock)
	CLEAR_PERI_REG_MASK (VSPI_PIN_REG, 0x400039E1);			// Set pin functions, disable CS1, CS2
	SET_PERI_REG_MASK (VSPI_PIN_REG, 0x20000006);
	CLEAR_PERI_REG_MASK (VSPI_SLAVE_REG, 0xC0000000);			// Clear bit 31 (set & clear for SPI reset)
	CLEAR_PERI_REG_MASK (VSPI_USER_REG, 0x7601FC31);			// Configure SPI (set bit 27 for WRITE, set bit 28 for READ
	SET_PERI_REG_MASK (VSPI_USER_REG, 0x890000C0);				// Initialize for WRITE
//	CLEAR_PERI_REG_MASK (VSPI_USER_REG, 0x6E01FC31);				// Configure SPI (set bit 27 for WRITE, set bit 28 for READ
//	SET_PERI_REG_MASK (VSPI_USER_REG, 0x910000C0);					// Initialize for READ
	CLEAR_PERI_REG_MASK (VSPI_MOSI_DLEN_REG, 0x00FFFFE8);			// 24 bit data out
	SET_PERI_REG_MASK (VSPI_MOSI_DLEN_REG, 0x00000017);
	CLEAR_PERI_REG_MASK (VSPI_MISO_DLEN_REG, 0x00FFFFE8);			// 24 bit data in
	SET_PERI_REG_MASK (VSPI_MISO_DLEN_REG, 0x00000017);

	CLEAR_PERI_REG_MASK (GPIO_FUNC5_OUT_SEL_CFG_REG, 0x00000EFF);	// GPIO5 Simple GPIO O/P
	SET_PERI_REG_MASK (GPIO_FUNC5_OUT_SEL_CFG_REG, 0x00000100);		// Output high if not direct IO_MUX for FPGA_SPI_CS
	SET_PERI_REG_MASK (GPIO_ENABLE_REG, 0x00000020);				// (i.e. IO_MUX_GPIO5_REG set to function 1 instead of 2)
	SET_PERI_REG_MASK (GPIO_OUT_REG, 0x00000020);				// Enable Output & set GPIO5 high

	FPGA = TRUE;
}



// ESP32 - READ 8 bit CMD + 24 bit data optimized (config for 40MHz SPI - 1.71us)
UINT16 Read_FPGA(UINT8 address)	// ESP32 SPI FPGA Write  9/13/17
{								// (SPI starts FPGA SPI config - only need to select Read)
  unsigned int rcv = 0; 	// Command byte first (LS Byte)
  unsigned int data = 0;

  if (FPGA)
  {
	while (READ_PERI_REG(VSPI_CMD_REG) & 0x00040000);  	// Check that last SPI finished (adds 88ns)
 	 	 	 	 	 	 	 	 	 	 	 	 	 // Set FPGA SPI for Read
	*((int*)VSPI_USER_REG) = (*((int*)VSPI_USER_REG) & 0x91FE03CE) | 0x910000C0;
												// Load address into Command register
	*((int*)VSPI_USER2_REG) = (*((int*)VSPI_USER2_REG) & 0x0FFF0000) | ((UINT32) address) | 0x70000000;

	*((int*)VSPI_CMD_REG) |= 0x00040000;				// Initiate SPI transmit

	while (READ_PERI_REG(VSPI_CMD_REG) & 0x00040000);  	// Check that last SPI finished

	rcv = REG_READ (VSPI_W8_REG);					    // Get 24 bits of data
//	rcv =  0x00D0BC0A;								// Test data only
	data = ((rcv & 0x0000000F) << 12);					// Extract D15-D12
	data |= ((rcv & 0x0000FF00) >> 4);					// 	 ...then D11-D4
	data |= ((rcv & 0x00F00000) >> 20);					//     ...then D3-D0
  }
  return ((UINT16) data);
}