/home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/bin/openocd [OpenOCD] Open On-Chip Debugger v0.12.0-esp32-20230921 (2023-09-21-13:41) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html User : 3 1 options.c:52 configuration_output_handler(): debug_level: 3User : 4 1 options.c:52 configuration_output_handler(): Debug: 5 1 options.c:233 add_default_dirs(): bindir=/builds/idf/openocd-esp32/_build/../openocd-esp32/bin Debug: 6 1 options.c:234 add_default_dirs(): pkgdatadir=/builds/idf/openocd-esp32/_build/../openocd-esp32/share/openocd Debug: 7 1 options.c:235 add_default_dirs(): exepath=/home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/bin Debug: 8 1 options.c:236 add_default_dirs(): bin2data=../share/openocd Debug: 9 1 configuration.c:33 add_script_search_dir(): adding /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts Debug: 10 1 configuration.c:33 add_script_search_dir(): adding /home/slawek/.config/openocd Debug: 11 1 configuration.c:33 add_script_search_dir(): adding /home/slawek/.openocd Debug: 12 1 configuration.c:33 add_script_search_dir(): adding /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/bin/../share/openocd/site Debug: 13 1 configuration.c:33 add_script_search_dir(): adding /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/bin/../share/openocd/scripts Debug: 14 1 command.c:151 script_debug(): command - ocd_find board/esp32c6-builtin.cfg Debug: 15 1 configuration.c:88 find_file(): found /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts/board/esp32c6-builtin.cfg Debug: 16 1 command.c:151 script_debug(): command - ocd_find interface/esp_usb_jtag.cfg Debug: 17 1 configuration.c:88 find_file(): found /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts/interface/esp_usb_jtag.cfg Debug: 18 1 command.c:151 script_debug(): command - adapter driver esp_usb_jtag Info : 19 1 transport.c:106 allow_transports(): only one transport option; autoselecting 'jtag' Debug: 20 1 command.c:151 script_debug(): command - espusbjtag vid_pid 0x303a 0x1001 Info : 21 1 esp_usb_jtag.c:901 esp_usb_jtag_vid_pid(): esp_usb_jtag: VID set to 0x303a and PID to 0x1001 Debug: 22 1 command.c:151 script_debug(): command - espusbjtag caps_descriptor 0x2000 Info : 23 1 esp_usb_jtag.c:912 esp_usb_jtag_caps_descriptor(): esp_usb_jtag: capabilities descriptor set to 0x2000 Debug: 24 1 command.c:151 script_debug(): command - adapter speed 40000 Debug: 25 1 adapter.c:249 adapter_config_khz(): handle adapter khz Debug: 26 1 adapter.c:213 adapter_khz_to_speed(): convert khz to adapter specific speed value Debug: 27 1 adapter.c:213 adapter_khz_to_speed(): convert khz to adapter specific speed value Debug: 28 1 command.c:151 script_debug(): command - ocd_find target/esp32c6.cfg Debug: 29 1 configuration.c:88 find_file(): found /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts/target/esp32c6.cfg Debug: 30 1 command.c:151 script_debug(): command - ocd_find target/esp_common.cfg Debug: 31 1 configuration.c:88 find_file(): found /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts/target/esp_common.cfg Debug: 32 1 command.c:151 script_debug(): command - ocd_find bitsbytes.tcl Debug: 33 1 configuration.c:88 find_file(): found /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts/bitsbytes.tcl Debug: 34 1 command.c:151 script_debug(): command - ocd_find memory.tcl Debug: 35 1 configuration.c:88 find_file(): found /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts/memory.tcl Debug: 36 1 command.c:151 script_debug(): command - ocd_find mmr_helpers.tcl Debug: 37 1 configuration.c:88 find_file(): found /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts/mmr_helpers.tcl Debug: 38 1 command.c:151 script_debug(): command - ocd_find target/esp_version.cfg Debug: 39 1 configuration.c:88 find_file(): found /home/slawek/.espressif_v52-beta1/tools/openocd-esp32/v0.12.0-esp32-20230921/openocd-esp32/share/openocd/scripts/target/esp_version.cfg Debug: 40 1 command.c:151 script_debug(): command - version Debug: 41 1 command.c:151 script_debug(): command - add_help_text program_esp write an image to flash, address is only required for binary images. verify, reset, exit, compress, restore_clock and encrypt are optional Debug: 42 1 command.c:151 script_debug(): command - add_usage_text program_esp [address] [verify] [reset] [exit] [compress] [no_clock_boost] [restore_clock] [encrypt] Debug: 43 1 command.c:151 script_debug(): command - add_help_text program_esp_bins write all the images at address specified in flasher_args.json generated while building idf project Debug: 44 1 command.c:151 script_debug(): command - add_usage_text program_esp_bins flasher_args.json [verify] [reset] [exit] [compress] [no_clock_boost] [restore_clock] Debug: 45 1 command.c:151 script_debug(): command - add_help_text esp_get_mac Print MAC address of the chip. Use a `format` argument to return formatted MAC value Debug: 46 1 command.c:151 script_debug(): command - add_usage_text esp_get_mac [format] Debug: 47 2 command.c:151 script_debug(): command - jtag newtap esp32c6 cpu -irlen 5 -expected-id 0x0000dc25 Debug: 48 2 tcl.c:419 handle_jtag_newtap_args(): Creating New Tap, Chip: esp32c6, Tap: cpu, Dotted: esp32c6.cpu, 4 params Debug: 49 2 core.c:1476 jtag_tap_init(): Created Tap: esp32c6.cpu @ abs position 0, irlen 5, capture: 0x1 mask: 0x3 Debug: 50 2 command.c:151 script_debug(): command - target create esp32c6 esp32c6 -chain-position esp32c6.cpu -coreid 0 -rtos FreeRTOS Debug: 51 2 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 52 2 FreeRTOS.c:1414 freertos_create(): freertos_create Debug: 53 2 command.c:285 register_command(): command 'esp' is already registered Debug: 54 2 command.c:285 register_command(): command 'esp32c6 esp' is already registered Debug: 55 2 command.c:151 script_debug(): command - esp32c6 configure -work-area-phys 0x40800000 -work-area-virt 0x40800000 -work-area-size 0x24000 -work-area-backup 1 Debug: 56 2 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 57 2 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 58 2 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 59 2 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 60 2 command.c:151 script_debug(): command - flash bank esp32c6.flash esp32c6 0x0 0 0 0 esp32c6 Debug: 61 2 command.c:285 register_command(): command 'esp' is already registered Debug: 62 2 tcl.c:1307 handle_flash_bank_command(): 'esp32c6' driver usage field missing Debug: 63 2 command.c:151 script_debug(): command - flash bank esp32c6.irom esp32c6 0x0 0 0 0 esp32c6 Debug: 64 2 command.c:285 register_command(): command 'esp' is already registered Debug: 65 2 command.c:285 register_command(): command 'esp appimage_offset' is already registered Debug: 66 2 command.c:285 register_command(): command 'esp compression' is already registered Debug: 67 2 command.c:285 register_command(): command 'esp verify_bank_hash' is already registered Debug: 68 2 command.c:285 register_command(): command 'esp flash_stub_clock_boost' is already registered Debug: 69 2 command.c:285 register_command(): command 'esp encrypt_binary' is already registered Debug: 70 2 command.c:285 register_command(): command 'esp stub_log' is already registered Debug: 71 2 tcl.c:1307 handle_flash_bank_command(): 'esp32c6' driver usage field missing Debug: 72 2 command.c:151 script_debug(): command - flash bank esp32c6.drom esp32c6 0x0 0 0 0 esp32c6 Debug: 73 2 command.c:285 register_command(): command 'esp' is already registered Debug: 74 2 command.c:285 register_command(): command 'esp appimage_offset' is already registered Debug: 75 2 command.c:285 register_command(): command 'esp compression' is already registered Debug: 76 2 command.c:285 register_command(): command 'esp verify_bank_hash' is already registered Debug: 77 2 command.c:285 register_command(): command 'esp flash_stub_clock_boost' is already registered Debug: 78 2 command.c:285 register_command(): command 'esp encrypt_binary' is already registered Debug: 79 2 command.c:285 register_command(): command 'esp stub_log' is already registered Debug: 80 2 tcl.c:1307 handle_flash_bank_command(): 'esp32c6' driver usage field missing Debug: 81 2 command.c:151 script_debug(): command - esp32c6 configure -event halted global _ESP_WDT_DISABLE $_ESP_WDT_DISABLE esp halted_event_handler Debug: 82 2 command.c:151 script_debug(): command - esp32c6 configure -event examine-end # Need to enable to set 'semihosting_basedir' arm semihosting enable arm semihosting_resexit enable if { [info exists _SEMIHOST_BASEDIR] } { if { $_SEMIHOST_BASEDIR != "" } { arm semihosting_basedir $_SEMIHOST_BASEDIR } } Debug: 83 2 command.c:151 script_debug(): command - esp32c6 configure -event reset-assert-post global _ESP_SOC_RESET $_ESP_SOC_RESET Debug: 84 2 command.c:151 script_debug(): command - esp32c6 configure -event gdb-attach if { $_ESP_SMP_BREAK != 0 } { $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut } # necessary to auto-probe flash bank when GDB is connected and generate proper memory map halt 1000 if { [$_ESP_MEMPROT_IS_ENABLED] } { # 'reset halt' to disable memory protection and allow flasher to work correctly echo "Memory protection is enabled. Reset target to disable it..." reset halt } if { $_ESP_ARCH == "riscv" } { # by default mask interrupts while stepping riscv set_maskisr steponly } Debug: 85 2 command.c:151 script_debug(): command - esp32c6 configure -event gdb-detach $_TARGETNAME_0 esp gdb_detach_handler Debug: 86 2 command.c:151 script_debug(): command - riscv set_reset_timeout_sec 2 Debug: 87 2 command.c:151 script_debug(): command - riscv set_command_timeout_sec 5 Debug: 88 2 command.c:151 script_debug(): command - riscv set_mem_access sysbus progbuf abstract Debug: 89 2 command.c:151 script_debug(): command - riscv set_ebreakm on Debug: 90 2 command.c:151 script_debug(): command - riscv set_ebreaks on Debug: 91 2 command.c:151 script_debug(): command - riscv set_ebreaku on Debug: 92 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 2016=mpcer Debug: 93 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 2017=mpcmr Debug: 94 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 2018=mpccr Debug: 95 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 2051=cpu_gpio_oen Debug: 96 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 2052=cpu_gpio_in Debug: 97 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 2053=cpu_gpio_out Debug: 98 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3008=pma_cfg0 Debug: 99 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3009=pma_cfg1 Debug: 100 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3010=pma_cfg2 Debug: 101 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3011=pma_cfg3 Debug: 102 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3012=pma_cfg4 Debug: 103 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3013=pma_cfg5 Debug: 104 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3014=pma_cfg6 Debug: 105 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3015=pma_cfg7 Debug: 106 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3016=pma_cfg8 Debug: 107 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3017=pma_cfg9 Debug: 108 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3018=pma_cfg10 Debug: 109 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3019=pma_cfg11 Debug: 110 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3020=pma_cfg12 Debug: 111 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3021=pma_cfg13 Debug: 112 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3022=pma_cfg14 Debug: 113 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3023=pma_cfg15 Debug: 114 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3024=pma_addr0 Debug: 115 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3025=pma_addr1 Debug: 116 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3026=pma_addr2 Debug: 117 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3027=pma_addr3 Debug: 118 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3028=pma_addr4 Debug: 119 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3029=pma_addr5 Debug: 120 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3030=pma_addr6 Debug: 121 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3031=pma_addr7 Debug: 122 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3032=pma_addr8 Debug: 123 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3033=pma_addr9 Debug: 124 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3034=pma_addr10 Debug: 125 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3035=pma_addr11 Debug: 126 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3036=pma_addr12 Debug: 127 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3037=pma_addr13 Debug: 128 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3038=pma_addr14 Debug: 129 2 command.c:151 script_debug(): command - esp32c6 riscv expose_csrs 3039=pma_addr15 Info : 130 2 server.c:298 add_service(): Listening on port 6666 for tcl connections Info : 131 2 server.c:298 add_service(): Listening on port 4444 for telnet connections Debug: 132 2 command.c:151 script_debug(): command - init Debug: 133 2 command.c:151 script_debug(): command - target init Debug: 134 2 command.c:151 script_debug(): command - target names Debug: 135 2 command.c:151 script_debug(): command - esp32c6 cget -event gdb-flash-erase-start Debug: 136 2 command.c:151 script_debug(): command - esp32c6 configure -event gdb-flash-erase-start reset init Debug: 137 2 command.c:151 script_debug(): command - esp32c6 cget -event gdb-flash-write-end Debug: 138 2 command.c:151 script_debug(): command - esp32c6 configure -event gdb-flash-write-end reset halt Debug: 139 2 command.c:151 script_debug(): command - esp32c6 cget -event gdb-attach Debug: 140 2 target.c:1624 handle_target_init_command(): Initializing targets... Debug: 141 2 riscv.c:413 riscv_init_target(): [esp32c6] riscv_init_target() Debug: 142 2 semihosting_common.c:105 semihosting_common_init(): Info : 143 6 esp_usb_jtag.c:661 esp_usb_jtag_init(): esp_usb_jtag: serial (54:32:04:03:60:1C) Debug: 144 6 libusb_helper.c:331 jtag_libusb_choose_interface(): usb ep out 02 Debug: 145 6 libusb_helper.c:331 jtag_libusb_choose_interface(): usb ep in 83 Debug: 146 6 libusb_helper.c:339 jtag_libusb_choose_interface(): Claiming interface 2 Info : 147 7 esp_usb_jtag.c:738 esp_usb_jtag_init(): esp_usb_jtag: Device found. Base speed 24000KHz, div range 1 to 255 Debug: 148 7 adapter.c:213 adapter_khz_to_speed(): convert khz to adapter specific speed value Debug: 149 7 adapter.c:217 adapter_khz_to_speed(): have adapter set up Debug: 150 7 esp_usb_jtag.c:798 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 24000 khz is 0 Debug: 151 7 esp_usb_jtag.c:814 esp_usb_jtag_speed(): esp_usb_jtag: setting divisor 1 Debug: 152 8 adapter.c:213 adapter_khz_to_speed(): convert khz to adapter specific speed value Debug: 153 8 adapter.c:217 adapter_khz_to_speed(): have adapter set up Debug: 154 8 esp_usb_jtag.c:798 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 24000 khz is 0 Info : 155 8 adapter.c:177 adapter_init(): clock speed 24000 kHz Debug: 156 8 openocd.c:133 handle_init_command(): Debug Adapter init complete Debug: 157 8 command.c:151 script_debug(): command - transport init Debug: 158 8 transport.c:218 handle_transport_init(): handle_transport_init Debug: 159 9 core.c:716 legacy_jtag_add_reset(): SRST line released Debug: 160 9 core.c:740 legacy_jtag_add_reset(): TRST line released Debug: 161 9 core.c:326 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 162 10 command.c:151 script_debug(): command - jtag arp_init Debug: 163 10 core.c:1507 jtag_init_inner(): Init JTAG chain Debug: 164 10 core.c:326 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 165 10 core.c:1232 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS Debug: 166 10 core.c:326 jtag_call_event_callbacks(): jtag event: TAP reset Info : 167 13 core.c:1131 jtag_examine_chain_display(): JTAG tap: esp32c6.cpu tap/device found: 0x0000dc25 (mfg: 0x612 (Espressif Systems), part: 0x000d, ver: 0x0) Debug: 168 13 core.c:1362 jtag_validate_ircapture(): IR capture validation scan Debug: 169 14 core.c:1420 jtag_validate_ircapture(): esp32c6.cpu: IR capture 0x05 Debug: 170 15 command.c:151 script_debug(): command - dap init Debug: 171 15 arm_dap.c:94 dap_init_all(): Initializing all DAPs ... Debug: 172 15 openocd.c:150 handle_init_command(): Examining targets... Debug: 173 15 target.c:1812 target_call_event_callbacks(): target event 19 (examine-start) for core esp32c6 Debug: 174 15 riscv.c:1507 riscv_examine(): [esp32c6] Starting examination Debug: 175 16 riscv.c:373 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071 Debug: 176 16 riscv.c:1517 riscv_examine(): [esp32c6] dtmcontrol=0x1071 Debug: 177 16 riscv.c:1519 riscv_examine(): [esp32c6] version=0x1 Debug: 178 16 riscv-013.c:2591 init_target(): [esp32c6] Init. Debug: 179 18 riscv-013.c:452 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071 Debug: 180 18 riscv-013.c:1714 examine(): [esp32c6] dtmcontrol=0x1071 Debug: 181 18 riscv-013.c:1715 examine(): [esp32c6] dmireset=0 Debug: 182 18 riscv-013.c:1716 examine(): [esp32c6] idle=1 Debug: 183 18 riscv-013.c:1717 examine(): [esp32c6] dmistat=0 Debug: 184 18 riscv-013.c:1718 examine(): [esp32c6] abits=7 Debug: 185 18 riscv-013.c:1719 examine(): [esp32c6] version=1 Debug: 186 18 riscv-013.c:251 get_dm(): [esp32c6] Coreid [0] Allocating new DM Debug: 187 18 riscv-013.c:492 dmi_scan(): [esp32c6] reset_delays_wait done /home/slawek/.espressif/tools/openocd-esp32/v0.12.0-esp32-20230419/openocd-esp32/bin/openocd [OpenOCD] Debug: 188 36 riscv-013.c:4847 riscv013_invalidate_cached_debug_buffer(): [esp32c6] Invalidating progbuf cache Debug: 189 60 riscv-013.c:463 increase_dmi_busy_delay(): [esp32c6] dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0 Debug: 190 64 riscv-013.c:452 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71 Debug: 191 74 riscv-013.c:463 increase_dmi_busy_delay(): [esp32c6] dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0 Debug: 192 75 riscv-013.c:452 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071 Debug: 193 76 riscv-013.c:1772 examine(): [esp32c6] dmstatus: 0x000303a2 Debug: 194 76 riscv-013.c:1788 examine(): [esp32c6] hartsellen=20 Debug: 195 78 riscv-013.c:463 increase_dmi_busy_delay(): [esp32c6] dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0 Debug: 196 80 riscv-013.c:452 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071 Info : 197 86 riscv-013.c:1816 examine(): [esp32c6] datacount=2 progbufsize=16 Debug: 198 104 riscv-013.c:1853 examine(): [esp32c6] Detected 2 harts. Debug: 199 109 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 200 111 riscv-013.c:822 execute_abstract_command(): [esp32c6] command 0x321008 failed; abstractcs=0x10000202 Debug: 201 113 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 202 118 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 203 123 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading misa Debug: 204 123 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 [OpenOCD] Debug: 205 128 riscv-013.c:1561 register_read_direct(): [esp32c6] misa = 0x40903105 Debug: 206 128 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3106 Debug: 207 128 riscv-013.c:1121 prep_for_register_access(): [esp32c6] Preparing mstatus to access csr3106 Debug: 208 128 riscv.c:4806 riscv_get_register(): [esp32c6] No cache, reading mstatus from target Debug: 209 128 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mstatus Debug: 210 128 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mstatus Debug: 211 128 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 212 134 riscv-013.c:1561 register_read_direct(): [esp32c6] mstatus = 0x201800 Debug: 213 134 riscv.c:4722 riscv_set_or_write_register(): [esp32c6] No cache, writing to target: mstatus <- 0x201a00 Debug: 214 134 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x201a00 to register mstatus Debug: 215 134 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x201a00 to mstatus Debug: 216 138 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 217 146 riscv-013.c:1532 register_write_direct(): [esp32c6] mstatus <- 0x201a00 Debug: 218 146 riscv-013.c:1141 prep_for_register_access(): [esp32c6] Prepared to access csr3106 (mstatus=0x201a00) Debug: 219 146 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220c22; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc22 Debug: 220 158 riscv-013.c:822 execute_abstract_command(): [esp32c6] command 0x220c22 failed; abstractcs=0x10000302 Debug: 221 162 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[00] = DASM(0xc2202473) Debug: 222 167 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[01] = DASM(0x00100073) Debug: 223 171 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 224 176 riscv-013.c:822 execute_abstract_command(): [esp32c6] command 0x241000 failed; abstractcs=0x10000302 Debug: 225 179 program.c:71 riscv_program_exec(): [esp32c6] Unable to execute program 0x7fff64d63290 Debug: 226 179 riscv-013.c:1152 cleanup_after_register_access(): [esp32c6] Restoring mstatus to 0x201800 Debug: 227 179 riscv.c:4722 riscv_set_or_write_register(): [esp32c6] No cache, writing to target: mstatus <- 0x201800 Debug: 228 179 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x201800 to register mstatus Debug: 229 179 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x201800 to mstatus Debug: 230 181 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 231 187 riscv-013.c:1532 register_write_direct(): [esp32c6] mstatus <- 0x201800 Debug: 232 187 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr4016 Debug: 233 187 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220fb0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xfb0 Debug: 234 190 riscv-013.c:822 execute_abstract_command(): [esp32c6] command 0x220fb0 failed; abstractcs=0x10000302 Debug: 235 193 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[00] = DASM(0xfb002473) Debug: 236 196 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[01] = DASM(0x00100073) Debug: 237 196 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x100073 @1 Debug: 238 196 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 239 200 riscv-013.c:822 execute_abstract_command(): [esp32c6] command 0x241000 failed; abstractcs=0x10000302 Debug: 240 203 program.c:71 riscv_program_exec(): [esp32c6] Unable to execute program 0x7fff64d63290 Debug: 241 203 riscv-013.c:1949 examine(): [esp32c6] XLEN=32, misa=0x40903105 Debug: 242 203 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s0 Debug: 243 208 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 244 212 riscv-013.c:1532 register_write_direct(): [esp32c6] s0 <- 0x0 Debug: 245 212 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s1 Debug: 246 215 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 [OpenOCD] Debug: 247 218 riscv-013.c:1532 register_write_direct(): [esp32c6] s1 <- 0x0 Debug: 248 218 riscv.c:5350 riscv_init_registers(): [esp32c6] create register cache for 4194 registers Debug: 249 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 2016 (name=csr_mpcer). Debug: 250 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 2017 (name=csr_mpcmr). Debug: 251 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 2018 (name=csr_mpccr). Debug: 252 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 2051 (name=csr_cpu_gpio_oen). Debug: 253 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 2052 (name=csr_cpu_gpio_in). Debug: 254 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 2053 (name=csr_cpu_gpio_out). Debug: 255 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3008 (name=csr_pma_cfg0). Debug: 256 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3009 (name=csr_pma_cfg1). Debug: 257 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3010 (name=csr_pma_cfg2). Debug: 258 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3011 (name=csr_pma_cfg3). Debug: 259 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3012 (name=csr_pma_cfg4). Debug: 260 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3013 (name=csr_pma_cfg5). Debug: 261 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3014 (name=csr_pma_cfg6). Debug: 262 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3015 (name=csr_pma_cfg7). Debug: 263 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3016 (name=csr_pma_cfg8). Debug: 264 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3017 (name=csr_pma_cfg9). Debug: 265 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3018 (name=csr_pma_cfg10). Debug: 266 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3019 (name=csr_pma_cfg11). Debug: 267 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3020 (name=csr_pma_cfg12). Debug: 268 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3021 (name=csr_pma_cfg13). Debug: 269 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3022 (name=csr_pma_cfg14). Debug: 270 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3023 (name=csr_pma_cfg15). Debug: 271 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3024 (name=csr_pma_addr0). Debug: 272 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3025 (name=csr_pma_addr1). Debug: 273 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3026 (name=csr_pma_addr2). Debug: 274 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3027 (name=csr_pma_addr3). Debug: 275 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3028 (name=csr_pma_addr4). Debug: 276 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3029 (name=csr_pma_addr5). Debug: 277 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3030 (name=csr_pma_addr6). Debug: 278 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3031 (name=csr_pma_addr7). Debug: 279 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3032 (name=csr_pma_addr8). Debug: 280 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3033 (name=csr_pma_addr9). Debug: 281 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3034 (name=csr_pma_addr10). Debug: 282 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3035 (name=csr_pma_addr11). Debug: 283 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3036 (name=csr_pma_addr12). Debug: 284 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3037 (name=csr_pma_addr13). Debug: 285 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3038 (name=csr_pma_addr14). Debug: 286 219 riscv.c:5972 riscv_init_registers(): [esp32c6] Exposing additional CSR 3039 (name=csr_pma_addr15). Debug: 287 219 riscv-013.c:1591 set_dcsr_ebreak(): [esp32c6] Set dcsr.ebreak* Debug: 288 219 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dcsr from target Debug: 289 219 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dcsr Debug: 290 219 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 291 219 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 292 226 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 293 226 riscv.c:4831 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 Info : 294 226 riscv-013.c:1992 examine(): [esp32c6] Examined RISC-V core; found 2 harts Info : 295 226 riscv-013.c:1993 examine(): [esp32c6] XLEN=32, misa=0x40903105 Debug: 296 226 target.c:1812 target_call_event_callbacks(): target event 21 (examine-end) for core esp32c6 Debug: 297 226 target.c:5047 target_handle_event(): target(0): esp32c6 (esp32c6) event: 21 (examine-end) action: # Need to enable to set 'semihosting_basedir' arm semihosting enable arm semihosting_resexit enable if { [info exists _SEMIHOST_BASEDIR] } { if { $_SEMIHOST_BASEDIR != "" } { arm semihosting_basedir $_SEMIHOST_BASEDIR } } Debug: 298 226 command.c:151 script_debug(): command - arm semihosting enable Debug: 299 226 riscv_semihosting.c:169 riscv_semihosting_setup(): [esp32c6] enable=1 Debug: 300 226 command.c:151 script_debug(): command - arm semihosting_resexit enable Debug: 301 226 command.c:151 script_debug(): command - arm semihosting_basedir . Debug: 302 226 command.c:151 script_debug(): command - flash init Debug: 303 226 tcl.c:1364 handle_flash_init_command(): Initializing flash devices... Debug: 304 226 command.c:151 script_debug(): command - nand init Debug: 305 226 tcl.c:484 handle_nand_init_command(): Initializing NAND devices... Debug: 306 226 command.c:151 script_debug(): command - pld init Debug: 307 226 pld.c:250 handle_pld_init_command(): Initializing PLDs... Debug: 308 226 command.c:151 script_debug(): command - tpiu init Info : 309 226 gdb_server.c:3784 gdb_target_start(): starting gdb server for esp32c6 on 3333 Info : 310 226 server.c:298 add_service(): Listening on port 3333 for gdb connections [OpenOCD] Debug: 311 342 riscv.c:2779 riscv_poll_hart(): [esp32c6] triggered a halt; previous_target_state=0 Debug: 312 342 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 313 342 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 314 360 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 315 360 riscv-013.c:4791 riscv013_halt_reason(): [esp32c6] dcsr.cause: 0x3 Debug: 316 360 riscv.c:1621 set_debug_reason(): [esp32c6] debug_reason=0 Debug: 317 360 target.c:1812 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c6 Debug: 318 360 target.c:1812 target_call_event_callbacks(): target event 1 (halted) for core esp32c6 Debug: 319 360 target.c:5047 target_handle_event(): target(0): esp32c6 (esp32c6) event: 1 (halted) action: global _ESP_WDT_DISABLE $_ESP_WDT_DISABLE esp halted_event_handler Debug: 320 360 command.c:151 script_debug(): command - command mode Debug: 321 360 command.c:151 script_debug(): command - mww 0x60008064 0x50D83AA1 Debug: 322 380 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x60008064 Debug: 323 386 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 324 386 command.c:151 script_debug(): command - mww 0x60008048 0 Debug: 325 391 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x60008048 Debug: 326 395 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 327 395 command.c:151 script_debug(): command - mww 0x60009064 0x50D83AA1 Debug: 328 403 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x60009064 Debug: 329 409 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 330 409 command.c:151 script_debug(): command - mww 0x60009048 0 [OpenOCD] Debug: 331 416 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x60009048 Debug: 332 427 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 333 427 command.c:151 script_debug(): command - mww 0x600b1c18 0x50D83AA1 Debug: 334 438 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600b1c18 Debug: 335 444 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 336 444 command.c:151 script_debug(): command - mww 0x600B1C00 0 Debug: 337 454 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600b1c00 Debug: 338 460 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 339 460 command.c:151 script_debug(): command - mww 0x600b1c20 0x50D83AA1 Debug: 340 465 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600b1c20 Debug: 341 471 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 342 471 command.c:151 script_debug(): command - mww 0x600b1c1c 0x40000000 [OpenOCD] Debug: 343 477 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600b1c1c Debug: 344 482 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 345 482 command.c:151 script_debug(): command - esp halted_event_handler Debug: 346 482 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mcause from target Debug: 347 482 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mcause Debug: 348 482 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mcause Debug: 349 482 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 Debug: 350 493 riscv-013.c:1561 register_read_direct(): [esp32c6] mcause = 0x0 Debug: 351 493 riscv.c:4831 riscv_get_register(): [esp32c6] Read mcause: 0x0 Debug: 352 493 esp_riscv.c:142 esp_riscv_print_exception_reason(): [esp32c6] mcause=0 [Debug Adapter] 2024-02-01 10:20:44,534 - Debug Adapter (main) - DEBUG - START_TIME_2024_02_01_10-20-44 2024-02-01 10:20:44,534 - Debug Adapter (main) - DEBUG - Init errors:None 2024-02-01 10:20:44,534 - Debug Adapter (main) - INFO - Working directory: /mnt/c/MojeProgramy/VSCode-win32-x64 2024-02-01 10:20:44,535 - Debug Adapter (main) - INFO - Arguments: { 'app_flash_off': 131072, 'board_type': None, 'cmdfile': '/home/user/projects/workspace/test_proj/esp-idf-vscode-generated.gdb', 'core_file': (), 'debug': 5, 'developer_mode': 'none', 'device_name': 'esp32c6', 'elfpath': ( '/home/user/projects/workspace/test_proj/build/test_proj.elf',), 'log_file': '/home/user/projects/workspace/test_proj/debug.log', 'log_mult_files': None, 'log_no_debug_console': None, 'oocd': 'openocd', 'oocd_args': None, 'oocd_ip': 'localhost', 'oocd_mode': 'connect_to_instance', 'oocd_scripts': None, 'port': 43474, 'postmortem': False, 'tmo_scale_factor': 3, 'toolchain_prefix': 'riscv32-esp-elf-'} DEBUG_ADAPTER_STARTED 2024-02-01 10:20:44,535 - Debug Adapter (main) - CRITICAL - Debug adapter -> Extension: DEBUG_ADAPTER_STARTED 2024-02-01 10:20:44,535 - Debug Adapter (main) - INFO - Starting. Cmd: /home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter_main.py -d 5 -e /home/user/projects/workspace/test_proj/build/test_proj.elf -l /home/user/projects/workspace/test_proj/debug.log -p 43474 -dn esp32c6 -a 0x20000 -t riscv32-esp-elf- -x /home/user/projects/workspace/test_proj/esp-idf-vscode-generated.gdb -tsf 3 2024-02-01 10:20:44,535 - Debug Adapter (main) - INFO - Listening on port 43474 DEBUG_ADAPTER_READY2CONNECT 2024-02-01 10:20:44,535 - Debug Adapter (main) - CRITICAL - Debug adapter -> Extension: DEBUG_ADAPTER_READY2CONNECT [Debug Adapter] 2024-02-01 10:20:44,637 - Debug Adapter (main) - DEBUG - Got connection 2024-02-01 10:20:44,638 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Debug adapter -> Extension: DEBUG_ADAPTER_STARTED\n", "source": {}}, "seq": 0} 2024-02-01 10:20:44,639 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Starting. Cmd: /home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter_main.py -d 5 -e /home/user/projects/workspace/test_proj/build/test_proj.elf -l /home/user/projects/workspace/test_proj/debug.log -p 43474 -dn esp32c6 -a 0x20000 -t riscv32-esp-elf- -x /home/user/projects/workspace/test_proj/esp-idf-vscode-generated.gdb -tsf 3\n\n", "source": {}}, "seq": 1} 2024-02-01 10:20:44,639 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Listening on port 43474\n", "source": {}}, "seq": 2} 2024-02-01 10:20:44,639 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Debug adapter -> Extension: DEBUG_ADAPTER_READY2CONNECT\n", "source": {}}, "seq": 3} 2024-02-01 10:20:44,639 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Got connection\n", "source": {}}, "seq": 4} [Debug Adapter] 2024-02-01 10:20:44,685 - Debug Adapter (ReaderThread) - DEBUG - read line: >>b'Content-Length: 514\\r\\n'<< [Debug Adapter] 2024-02-01 10:20:44,685 - Debug Adapter (ReaderThread) - DEBUG - read line: >>b'\\r\\n'<< 2024-02-01 10:20:44,685 - Debug Adapter(Command Processor) - DEBUG - Got json: { "arguments": { "adapterID": "espidf", "clientID": "vscode", "clientName": "Visual Studio Code", "columnsStartAt1": true, "linesStartAt1": true, "locale": "en", "pathFormat": "path", "supportsArgsCanBeInterpretedByShell": true, "supportsInvalidatedEvent": true, "supportsMemoryEvent": true, "supportsMemoryReferences": true, "supportsProgressReporting": true, "supportsRunInTerminalRequest": true, "supportsStartDebuggingRequest": true, "supportsVariablePaging": true, "supportsVariableType": true }, "command": "initialize", "seq": 1, "type": "request" } 2024-02-01 10:20:44,686 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Got json: {\n \"arguments\": {\n \"adapterID\": \"espidf\",\n \"clientID\": \"vscode\",\n \"clientName\": \"Visual Studio Code\",\n \"columnsStartAt1\": true,\n \"linesStartAt1\": true,\n \"locale\": \"en\",\n \"pathFormat\": \"path\",\n \"supportsArgsCanBeInterpretedByShell\": true,\n \"supportsInvalidatedEvent\": true,\n \"supportsMemoryEvent\": true,\n \"supportsMemoryReferences\": true,\n \"supportsProgressReporting\": true,\n \"supportsRunInTerminalRequest\": true,\n \"supportsStartDebuggingRequest\": true,\n \"supportsVariablePaging\": true,\n \"supportsVariableType\": true\n },\n \"command\": \"initialize\",\n \"seq\": 1,\n \"type\": \"request\"\n}\n", "source": {}}, "seq": 5} [Debug Adapter] 2024-02-01 10:20:44,688 - Gdb - DEBUG - MI->: -gdb-set mi-async on [Debug Adapter] 2024-02-01 10:20:44,839 - Gdb - DEBUG - MI<-: [{'message': 'thread-group-added', 'payload': {'id': 'i1'}, 'stream': 'stdout', 'token': None, 'type': 'notify'}, {'message': 'done', 'payload': None, 'stream': 'stdout', 'token': None, 'type': 'result'}] [Debug Adapter] 2024-02-01 10:20:44,839 - Gdb - INFO - NOTIFY: thread-group-added {'id': 'i1'} 2024-02-01 10:20:44,839 - Gdb - DEBUG - RESULT: done None 2024-02-01 10:20:44,839 - Gdb - DEBUG - MI->: -gdb-set logging file /tmp/gdb_proc.log 2024-02-01 10:20:44,839 - Gdb - DEBUG - MI<-: [{'message': 'done', 'payload': None, 'stream': 'stdout', 'token': None, 'type': 'result'}] 2024-02-01 10:20:44,839 - Gdb - DEBUG - RESULT: done None 2024-02-01 10:20:44,839 - Gdb - DEBUG - MI->: -gdb-set logging on 2024-02-01 10:20:44,840 - Gdb - DEBUG - MI<-: [{'message': None, 'payload': "Warning: 'set logging on', an alias for the command 'set logging " "enabled', is deprecated.\\n", 'stream': 'stdout', 'type': 'console'}, {'message': None, 'payload': "Use 'set logging enabled on'.\\n\\n", 'stream': 'stdout', 'type': 'console'}, {'message': 'done', 'payload': None, 'stream': 'stdout', 'token': None, 'type': 'result'}] [Debug Adapter] 2024-02-01 10:20:44,840 - Gdb - INFO - CONS: ("Warning: 'set logging on', an alias for the command 'set logging enabled', " 'is deprecated.\\n') 2024-02-01 10:20:44,840 - Gdb - INFO - CONS: "Use 'set logging enabled on'.\\n\\n" 2024-02-01 10:20:44,840 - Gdb - DEBUG - RESULT: done None 2024-02-01 10:20:44,840 - Debug Adapter (main) - DEBUG - Created gdb object of type: GdbEspRiscv 2024-02-01 10:20:44,840 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Created gdb object of type: GdbEspRiscv\n", "source": {}}, "seq": 6} 2024-02-01 10:20:44,840 - Gdb - DEBUG - MI->: -file-exec-and-symbols /home/user/projects/workspace/test_proj/build/test_proj.elf [Debug Adapter] 2024-02-01 10:20:44,882 - Gdb - DEBUG - MI<-: [{'message': 'done', 'payload': None, 'stream': 'stdout', 'token': None, 'type': 'result'}] [Debug Adapter] 2024-02-01 10:20:44,882 - Gdb - DEBUG - RESULT: done None 2024-02-01 10:20:44,882 - Gdb - DEBUG - Connecting to 127.0.0.1:3333 2024-02-01 10:20:44,882 - Gdb - DEBUG - MI->: -target-select remote 127.0.0.1:3333 [OpenOCD] Info : 353 858 server.c:90 add_connection(): accepting 'gdb' connection on tcp/3333 Debug: 354 858 breakpoints.c:363 breakpoint_clear_target_internal(): Delete all breakpoints for target: esp32c6 Debug: 355 858 breakpoints.c:551 watchpoint_clear_target(): Delete all watchpoints for target: esp32c6 Debug: 356 858 target.c:1812 target_call_event_callbacks(): target event 22 (gdb-attach) for core esp32c6 Debug: 357 858 target.c:5047 target_handle_event(): target(0): esp32c6 (esp32c6) event: 22 (gdb-attach) action: if { $_ESP_SMP_BREAK != 0 } { $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut } # necessary to auto-probe flash bank when GDB is connected and generate proper memory map halt 1000 if { [$_ESP_MEMPROT_IS_ENABLED] } { # 'reset halt' to disable memory protection and allow flasher to work correctly echo "Memory protection is enabled. Reset target to disable it..." reset halt } if { $_ESP_ARCH == "riscv" } { # by default mask interrupts while stepping riscv set_maskisr steponly } Debug: 358 858 command.c:151 script_debug(): command - halt 1000 Debug: 359 858 target.c:3273 handle_halt_command(): - Debug: 360 858 riscv.c:1694 riscv_halt(): [esp32c6] halting all harts Debug: 361 858 riscv.c:1630 halt_prep(): [esp32c6] prep hart, debug_reason=0 Debug: 362 858 riscv.c:1633 halt_prep(): [esp32c6] Hart is already halted. [OpenOCD] Debug: 363 860 riscv.c:1653 riscv_halt_go_all_harts(): [esp32c6] Hart is already halted. Debug: 364 860 target.c:1812 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c6 Debug: 365 860 target.c:1812 target_call_event_callbacks(): target event 1 (halted) for core esp32c6 Debug: 366 860 target.c:5047 target_handle_event(): target(0): esp32c6 (esp32c6) event: 1 (halted) action: global _ESP_WDT_DISABLE $_ESP_WDT_DISABLE esp halted_event_handler Debug: 367 860 command.c:151 script_debug(): command - command mode Debug: 368 860 command.c:151 script_debug(): command - mww 0x60008064 0x50D83AA1 Debug: 369 871 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x60008064 Debug: 370 876 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 371 876 command.c:151 script_debug(): command - mww 0x60008048 0 Debug: 372 882 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x60008048 Debug: 373 889 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 374 889 command.c:151 script_debug(): command - mww 0x60009064 0x50D83AA1 Debug: 375 896 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x60009064 Debug: 376 901 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 377 901 command.c:151 script_debug(): command - mww 0x60009048 0 Debug: 378 908 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x60009048 Debug: 379 911 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 380 911 command.c:151 script_debug(): command - mww 0x600b1c18 0x50D83AA1 [OpenOCD] Debug: 381 963 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600b1c18 Debug: 382 989 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 383 989 command.c:151 script_debug(): command - mww 0x600B1C00 0 Debug: 384 996 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600b1c00 Debug: 385 1008 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 386 1008 command.c:151 script_debug(): command - mww 0x600b1c20 0x50D83AA1 Debug: 387 1021 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600b1c20 Debug: 388 1025 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 389 1025 command.c:151 script_debug(): command - mww 0x600b1c1c 0x40000000 Debug: 390 1035 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600b1c1c [OpenOCD] Debug: 391 1040 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 392 1040 command.c:151 script_debug(): command - esp halted_event_handler Debug: 393 1040 riscv.c:4819 riscv_get_register(): [esp32c6] Read mcause: 0x0 (cached) Debug: 394 1040 esp_riscv.c:142 esp_riscv_print_exception_reason(): [esp32c6] mcause=0 Debug: 395 1044 command.c:151 script_debug(): command - riscv dmi_write 0x17 0x2203a1 Debug: 396 1048 command.c:151 script_debug(): command - riscv dmi_read 0x04 Debug: 397 1054 command.c:151 script_debug(): command - riscv dmi_write 0x17 0x2203b5 Debug: 398 1058 command.c:151 script_debug(): command - riscv dmi_read 0x04 Debug: 399 1061 command.c:151 script_debug(): command - riscv dmi_write 0x17 0x2203b6 Debug: 400 1064 command.c:151 script_debug(): command - riscv dmi_read 0x04 Debug: 401 1070 command.c:151 script_debug(): command - riscv dmi_write 0x17 0x2203b7 Debug: 402 1074 command.c:151 script_debug(): command - riscv dmi_read 0x04 Debug: 403 1077 command.c:151 script_debug(): command - riscv set_maskisr steponly Debug: 404 1077 FreeRTOS.c:1387 freertos_clean(): freertos_clean Debug: 405 1077 FreeRTOS.c:882 freertos_update_threads(): freertos_update_threads Warn : 406 1077 FreeRTOS.c:890 freertos_update_threads(): No symbols for FreeRTOS! Debug: 407 1077 esp_flash.c:961 esp_algo_flash_probe(): Flash size = 0 KB @ 0x00000000 'esp32c6' - 'halted' Debug: 408 1077 esp_flash.c:245 esp_algo_flasher_algorithm_init(): base=00000000 set=0 Debug: 409 1077 esp_algorithm.c:290 algorithm_load_func_image(): stub: base 0x0, start 0x4080110c, 2 sections Debug: 410 1077 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 5202, flags 1 Debug: 411 1077 target.c:2017 target_alloc_working_area_try(): MMU disabled, using physical address for working memory 0x40800000 Debug: 412 1077 target.c:2070 target_alloc_working_area_try(): allocated new working area of 5204 bytes at address 0x40800000 [OpenOCD] Debug: 413 2563 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 414 2563 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 415 2563 target.c:1938 print_wa_layout(): 0x40801454-0x40823fff (142252 bytes) Debug: 416 2563 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800000 [OpenOCD] Debug: 417 2570 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800000 Debug: 418 2580 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800200 Debug: 419 2596 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 420 2596 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800400 Debug: 421 2604 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800400 Debug: 422 2612 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800600 Debug: 423 2621 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 424 2621 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800800 [OpenOCD] Debug: 425 2626 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800800 Debug: 426 2633 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800a00 Debug: 427 2641 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 428 2641 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800c00 Debug: 429 2645 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800c00 Debug: 430 2657 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800e00 Debug: 431 2667 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 432 2667 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40801000 Debug: 433 2675 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801000 [OpenOCD] Debug: 434 2683 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801200 Debug: 435 2691 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 436 2691 target.c:2379 target_write_buffer(): writing buffer of 82 byte at 0x40801400 Debug: 437 2701 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801400 Debug: 438 2712 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 439 2712 esp_riscv.c:826 esp_riscv_write_memory(): Use 32-bit access: size: 2 count:1 start address: 0x40801450 Debug: 440 2734 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 441 2739 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801450 Debug: 442 2744 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 443 2744 target.c:2070 target_alloc_working_area_try(): allocated new working area of 4 bytes at address 0x40801454 [OpenOCD] Debug: 444 2757 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 445 2757 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 446 2757 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 447 2757 target.c:1938 print_wa_layout(): 0x40801458-0x40823fff (142248 bytes) Debug: 448 2757 esp_algorithm.c:377 algorithm_load_func_image(): Write tramp to addr 0x40801454, sz 4 Debug: 449 2757 target.c:2379 target_write_buffer(): writing buffer of 4 byte at 0x40801454 Debug: 450 2763 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801454 Debug: 451 2769 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 452 2769 esp_algorithm.c:388 algorithm_load_func_image(): Tramp mapped to addr 0x40801454 Debug: 453 2769 target.c:2070 target_alloc_working_area_try(): allocated new working area of 11176 bytes at address 0x40801458 Debug: 454 2769 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 455 2769 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 456 2769 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 457 2769 target.c:1938 print_wa_layout(): 0x40804000-0x40823fff (131072 bytes) Debug: 458 2769 esp_algorithm.c:413 algorithm_load_func_image(): addr 0x00000000, sz 321, flags 0 Debug: 459 2769 esp_algorithm.c:417 algorithm_load_func_image(): DATA sec size 321 -> 324 Debug: 460 2769 esp_algorithm.c:419 algorithm_load_func_image(): BSS sec size 316 -> 316 Debug: 461 2769 target.c:2070 target_alloc_working_area_try(): allocated new working area of 640 bytes at address 0x40804000 [OpenOCD] Debug: 462 3072 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 463 3072 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 464 3072 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 465 3072 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 466 3072 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 467 3072 target.c:1938 print_wa_layout(): 0x40804280-0x40823fff (130432 bytes) Debug: 468 3072 target.c:2379 target_write_buffer(): writing buffer of 321 byte at 0x40804000 [OpenOCD] Debug: 469 3095 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804000 Debug: 470 3106 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 471 3106 esp_riscv.c:826 esp_riscv_write_memory(): Use 32-bit access: size: 1 count:1 start address: 0x40804140 Debug: 472 3123 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. [OpenOCD] Debug: 473 3128 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804140 Debug: 474 3132 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 475 3132 target.c:2070 target_alloc_working_area_try(): allocated new working area of 1300 bytes at address 0x40804280 [OpenOCD] Debug: 476 3619 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 477 3619 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 478 3619 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 479 3619 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 480 3619 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 481 3619 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 482 3619 target.c:1938 print_wa_layout(): 0x40804794-0x40823fff (129132 bytes) Debug: 483 3619 esp_algorithm.c:460 algorithm_load_func_image(): Stub loaded in 2541.6 ms Debug: 484 3619 esp_riscv_algorithm.c:43 esp_riscv_algo_regs_init_start(): Check stack addr 0x40804794 Debug: 485 3619 esp_riscv_algorithm.c:46 esp_riscv_algo_regs_init_start(): Adjust stack addr to 0x40804790 Debug: 486 3619 esp_riscv_algorithm.c:84 esp_riscv_algo_init(): Set arg[0] = 5 (a0) Debug: 487 3619 esp_riscv_algorithm.c:95 esp_riscv_algo_init(): Set arg[1] = -1 (a1) Debug: 488 3619 esp_riscv_algorithm.c:95 esp_riscv_algo_init(): Set arg[2] = 0 (a2) Debug: 489 3619 esp.c:240 esp_common_assist_debug_monitor_disable(): [esp32c6] addr 0x600c2000 [OpenOCD] Debug: 490 3629 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 491 3629 target.c:2598 target_read_u32(): address: 0x600c2000, value: 0x00000000 Debug: 492 3629 esp.c:248 esp_common_assist_debug_monitor_disable(): Saved register value 0x00000000 Debug: 493 3629 target.c:2686 target_write_u32(): address: 0x600c2000, value: 0x00000000 Debug: 494 3637 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600c2000 Debug: 495 3641 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 496 3641 target.c:2070 target_alloc_working_area_try(): allocated new working area of 28 bytes at address 0x40804794 [OpenOCD] Debug: 497 3666 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 498 3666 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 499 3666 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 500 3666 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 501 3666 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 502 3666 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 503 3666 target.c:1938 print_wa_layout(): b* 0x40804794-0x408047af (28 bytes) Debug: 504 3666 target.c:1938 print_wa_layout(): 0x408047b0-0x40823fff (129104 bytes) Debug: 505 3666 esp_algorithm.c:90 algorithm_run_image(): Algorithm start @ 0x40801454, stack 1300 bytes @ 0x40804794 Debug: 506 3666 esp_riscv.c:593 esp_riscv_start_algorithm(): save ra Debug: 507 3666 riscv.c:4823 riscv_get_register(): [esp32c6] Reading ra from target Debug: 508 3666 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register ra Debug: 509 3666 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading ra Debug: 510 3666 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001 Debug: 511 3672 riscv-013.c:1561 register_read_direct(): [esp32c6] ra = 0x40801456 Debug: 512 3672 riscv.c:4831 riscv_get_register(): [esp32c6] Read ra: 0x40801456 Debug: 513 3672 riscv.c:5259 register_get(): [esp32c6] Read 0x40801456 from ra (valid=1). Debug: 514 3672 esp_riscv.c:593 esp_riscv_start_algorithm(): save sp Debug: 515 3672 riscv.c:4823 riscv_get_register(): [esp32c6] Reading sp from target Debug: 516 3672 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register sp Debug: 517 3672 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading sp Debug: 518 3672 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002 Debug: 519 3677 riscv-013.c:1561 register_read_direct(): [esp32c6] sp = 0x40804780 Debug: 520 3677 riscv.c:4831 riscv_get_register(): [esp32c6] Read sp: 0x40804780 Debug: 521 3677 riscv.c:5259 register_get(): [esp32c6] Read 0x40804780 from sp (valid=1). Debug: 522 3677 esp_riscv.c:593 esp_riscv_start_algorithm(): save gp Debug: 523 3677 riscv.c:4823 riscv_get_register(): [esp32c6] Reading gp from target Debug: 524 3677 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register gp Debug: 525 3677 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading gp Debug: 526 3677 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003 Debug: 527 3685 riscv-013.c:1561 register_read_direct(): [esp32c6] gp = 0x0 Debug: 528 3685 riscv.c:4831 riscv_get_register(): [esp32c6] Read gp: 0x0 Debug: 529 3685 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from gp (valid=1). Debug: 530 3685 esp_riscv.c:593 esp_riscv_start_algorithm(): save tp Debug: 531 3685 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tp from target Debug: 532 3685 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tp Debug: 533 3685 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tp Debug: 534 3685 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004 Debug: 535 3694 riscv-013.c:1561 register_read_direct(): [esp32c6] tp = 0x0 Debug: 536 3694 riscv.c:4831 riscv_get_register(): [esp32c6] Read tp: 0x0 Debug: 537 3694 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tp (valid=1). Debug: 538 3694 esp_riscv.c:593 esp_riscv_start_algorithm(): save t0 Debug: 539 3694 riscv.c:4823 riscv_get_register(): [esp32c6] Reading t0 from target Debug: 540 3694 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register t0 Debug: 541 3694 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading t0 Debug: 542 3694 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005 Debug: 543 3703 riscv-013.c:1561 register_read_direct(): [esp32c6] t0 = 0x40027bd4 Debug: 544 3703 riscv.c:4831 riscv_get_register(): [esp32c6] Read t0: 0x40027bd4 Debug: 545 3703 riscv.c:5259 register_get(): [esp32c6] Read 0x40027bd4 from t0 (valid=1). Debug: 546 3703 esp_riscv.c:593 esp_riscv_start_algorithm(): save t1 Debug: 547 3703 riscv.c:4823 riscv_get_register(): [esp32c6] Reading t1 from target Debug: 548 3703 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register t1 Debug: 549 3703 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading t1 Debug: 550 3703 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006 Debug: 551 3711 riscv-013.c:1561 register_read_direct(): [esp32c6] t1 = 0xffffffe0 Debug: 552 3711 riscv.c:4831 riscv_get_register(): [esp32c6] Read t1: 0xffffffe0 Debug: 553 3711 riscv.c:5259 register_get(): [esp32c6] Read 0xffffffe0 from t1 (valid=1). Debug: 554 3711 esp_riscv.c:593 esp_riscv_start_algorithm(): save t2 Debug: 555 3711 riscv.c:4823 riscv_get_register(): [esp32c6] Reading t2 from target Debug: 556 3711 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register t2 Debug: 557 3711 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading t2 Debug: 558 3711 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007 Debug: 559 3717 riscv-013.c:1561 register_read_direct(): [esp32c6] t2 = 0x0 Debug: 560 3717 riscv.c:4831 riscv_get_register(): [esp32c6] Read t2: 0x0 Debug: 561 3717 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t2 (valid=1). Debug: 562 3717 esp_riscv.c:593 esp_riscv_start_algorithm(): save fp Debug: 563 3717 riscv.c:4823 riscv_get_register(): [esp32c6] Reading fp from target Debug: 564 3717 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s0 Debug: 565 3717 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s0 Debug: 566 3717 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 [OpenOCD] Debug: 567 3727 riscv-013.c:1561 register_read_direct(): [esp32c6] s0 = 0x0 Debug: 568 3727 riscv.c:4831 riscv_get_register(): [esp32c6] Read fp: 0x0 Debug: 569 3727 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from fp (valid=1). Debug: 570 3727 esp_riscv.c:593 esp_riscv_start_algorithm(): save s1 Debug: 571 3727 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s1 from target Debug: 572 3727 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s1 Debug: 573 3727 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s1 Debug: 574 3727 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 575 3736 riscv-013.c:1561 register_read_direct(): [esp32c6] s1 = 0x0 Debug: 576 3736 riscv.c:4831 riscv_get_register(): [esp32c6] Read s1: 0x0 Debug: 577 3736 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s1 (valid=1). Debug: 578 3736 esp_riscv.c:593 esp_riscv_start_algorithm(): save a0 Debug: 579 3736 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a0 from target Debug: 580 3736 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a0 Debug: 581 3736 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a0 Debug: 582 3736 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 583 3759 riscv-013.c:1561 register_read_direct(): [esp32c6] a0 = 0x20000000 Debug: 584 3759 riscv.c:4831 riscv_get_register(): [esp32c6] Read a0: 0x20000000 Debug: 585 3759 riscv.c:5259 register_get(): [esp32c6] Read 0x20000000 from a0 (valid=1). Debug: 586 3759 esp_riscv.c:593 esp_riscv_start_algorithm(): save a1 Debug: 587 3759 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a1 from target Debug: 588 3759 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a1 Debug: 589 3759 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a1 Debug: 590 3759 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b Debug: 591 3772 riscv-013.c:1561 register_read_direct(): [esp32c6] a1 = 0x60002000 Debug: 592 3772 riscv.c:4831 riscv_get_register(): [esp32c6] Read a1: 0x60002000 Debug: 593 3772 riscv.c:5259 register_get(): [esp32c6] Read 0x60002000 from a1 (valid=1). Debug: 594 3772 esp_riscv.c:593 esp_riscv_start_algorithm(): save a2 Debug: 595 3772 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a2 from target Debug: 596 3772 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a2 Debug: 597 3772 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a2 Debug: 598 3772 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c Debug: 599 3782 riscv-013.c:1561 register_read_direct(): [esp32c6] a2 = 0x10 Debug: 600 3782 riscv.c:4831 riscv_get_register(): [esp32c6] Read a2: 0x10 Debug: 601 3782 riscv.c:5259 register_get(): [esp32c6] Read 0x00000010 from a2 (valid=1). Debug: 602 3782 esp_riscv.c:593 esp_riscv_start_algorithm(): save a3 Debug: 603 3782 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a3 from target Debug: 604 3782 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a3 Debug: 605 3782 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a3 Debug: 606 3782 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d Debug: 607 3789 riscv-013.c:1561 register_read_direct(): [esp32c6] a3 = 0x10000 Debug: 608 3789 riscv.c:4831 riscv_get_register(): [esp32c6] Read a3: 0x10000 Debug: 609 3789 riscv.c:5259 register_get(): [esp32c6] Read 0x00010000 from a3 (valid=1). Debug: 610 3789 esp_riscv.c:593 esp_riscv_start_algorithm(): save a4 Debug: 611 3789 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a4 from target Debug: 612 3789 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a4 Debug: 613 3789 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a4 Debug: 614 3789 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e [OpenOCD] Debug: 615 3799 riscv-013.c:1561 register_read_direct(): [esp32c6] a4 = 0x408021e0 Debug: 616 3799 riscv.c:4831 riscv_get_register(): [esp32c6] Read a4: 0x408021e0 Debug: 617 3799 riscv.c:5259 register_get(): [esp32c6] Read 0x408021e0 from a4 (valid=1). Debug: 618 3799 esp_riscv.c:593 esp_riscv_start_algorithm(): save a5 Debug: 619 3799 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a5 from target Debug: 620 3799 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a5 Debug: 621 3799 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a5 Debug: 622 3799 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f Debug: 623 3811 riscv-013.c:1561 register_read_direct(): [esp32c6] a5 = 0x4 Debug: 624 3811 riscv.c:4831 riscv_get_register(): [esp32c6] Read a5: 0x4 Debug: 625 3811 riscv.c:5259 register_get(): [esp32c6] Read 0x00000004 from a5 (valid=1). Debug: 626 3811 esp_riscv.c:593 esp_riscv_start_algorithm(): save a6 Debug: 627 3811 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a6 from target Debug: 628 3811 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a6 Debug: 629 3811 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a6 Debug: 630 3811 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010 Debug: 631 3821 riscv-013.c:1561 register_read_direct(): [esp32c6] a6 = 0x8 Debug: 632 3821 riscv.c:4831 riscv_get_register(): [esp32c6] Read a6: 0x8 Debug: 633 3821 riscv.c:5259 register_get(): [esp32c6] Read 0x00000008 from a6 (valid=1). Debug: 634 3821 esp_riscv.c:593 esp_riscv_start_algorithm(): save a7 Debug: 635 3821 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a7 from target Debug: 636 3821 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a7 Debug: 637 3821 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a7 Debug: 638 3821 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011 Debug: 639 3830 riscv-013.c:1561 register_read_direct(): [esp32c6] a7 = 0x80000000 Debug: 640 3831 riscv.c:4831 riscv_get_register(): [esp32c6] Read a7: 0x80000000 Debug: 641 3831 riscv.c:5259 register_get(): [esp32c6] Read 0x80000000 from a7 (valid=1). Debug: 642 3831 esp_riscv.c:593 esp_riscv_start_algorithm(): save s2 Debug: 643 3831 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s2 from target Debug: 644 3831 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s2 Debug: 645 3831 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s2 Debug: 646 3831 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012 Debug: 647 3841 riscv-013.c:1561 register_read_direct(): [esp32c6] s2 = 0x0 Debug: 648 3841 riscv.c:4831 riscv_get_register(): [esp32c6] Read s2: 0x0 Debug: 649 3841 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s2 (valid=1). Debug: 650 3841 esp_riscv.c:593 esp_riscv_start_algorithm(): save s3 Debug: 651 3841 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s3 from target Debug: 652 3841 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s3 Debug: 653 3841 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s3 Debug: 654 3841 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013 Debug: 655 3846 riscv-013.c:1561 register_read_direct(): [esp32c6] s3 = 0x0 Debug: 656 3846 riscv.c:4831 riscv_get_register(): [esp32c6] Read s3: 0x0 Debug: 657 3846 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s3 (valid=1). Debug: 658 3846 esp_riscv.c:593 esp_riscv_start_algorithm(): save s4 Debug: 659 3846 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s4 from target Debug: 660 3846 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s4 Debug: 661 3846 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s4 Debug: 662 3846 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014 [OpenOCD] Debug: 663 3853 riscv-013.c:1561 register_read_direct(): [esp32c6] s4 = 0x0 Debug: 664 3853 riscv.c:4831 riscv_get_register(): [esp32c6] Read s4: 0x0 Debug: 665 3853 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s4 (valid=1). Debug: 666 3853 esp_riscv.c:593 esp_riscv_start_algorithm(): save s5 Debug: 667 3853 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s5 from target Debug: 668 3853 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s5 Debug: 669 3853 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s5 Debug: 670 3853 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015 Debug: 671 3861 riscv-013.c:1561 register_read_direct(): [esp32c6] s5 = 0x0 Debug: 672 3861 riscv.c:4831 riscv_get_register(): [esp32c6] Read s5: 0x0 Debug: 673 3861 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s5 (valid=1). Debug: 674 3861 esp_riscv.c:593 esp_riscv_start_algorithm(): save s6 Debug: 675 3861 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s6 from target Debug: 676 3861 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s6 Debug: 677 3861 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s6 Debug: 678 3861 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016 Debug: 679 3869 riscv-013.c:1561 register_read_direct(): [esp32c6] s6 = 0x0 Debug: 680 3869 riscv.c:4831 riscv_get_register(): [esp32c6] Read s6: 0x0 Debug: 681 3869 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s6 (valid=1). Debug: 682 3869 esp_riscv.c:593 esp_riscv_start_algorithm(): save s7 Debug: 683 3869 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s7 from target Debug: 684 3869 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s7 Debug: 685 3869 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s7 Debug: 686 3869 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017 Debug: 687 3879 riscv-013.c:1561 register_read_direct(): [esp32c6] s7 = 0x0 Debug: 688 3879 riscv.c:4831 riscv_get_register(): [esp32c6] Read s7: 0x0 Debug: 689 3879 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s7 (valid=1). Debug: 690 3879 esp_riscv.c:593 esp_riscv_start_algorithm(): save s8 Debug: 691 3879 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s8 from target Debug: 692 3879 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s8 Debug: 693 3879 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s8 Debug: 694 3879 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018 Debug: 695 3936 riscv-013.c:1561 register_read_direct(): [esp32c6] s8 = 0x0 Debug: 696 3936 riscv.c:4831 riscv_get_register(): [esp32c6] Read s8: 0x0 Debug: 697 3936 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s8 (valid=1). Debug: 698 3936 esp_riscv.c:593 esp_riscv_start_algorithm(): save s9 Debug: 699 3936 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s9 from target Debug: 700 3936 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s9 Debug: 701 3936 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s9 Debug: 702 3936 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019 [OpenOCD] Debug: 703 3945 riscv-013.c:1561 register_read_direct(): [esp32c6] s9 = 0x0 Debug: 704 3945 riscv.c:4831 riscv_get_register(): [esp32c6] Read s9: 0x0 Debug: 705 3945 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s9 (valid=1). Debug: 706 3945 esp_riscv.c:593 esp_riscv_start_algorithm(): save s10 Debug: 707 3945 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s10 from target Debug: 708 3945 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s10 Debug: 709 3945 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s10 Debug: 710 3945 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a Debug: 711 3954 riscv-013.c:1561 register_read_direct(): [esp32c6] s10 = 0x0 Debug: 712 3954 riscv.c:4831 riscv_get_register(): [esp32c6] Read s10: 0x0 Debug: 713 3954 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s10 (valid=1). Debug: 714 3954 esp_riscv.c:593 esp_riscv_start_algorithm(): save s11 Debug: 715 3954 riscv.c:4823 riscv_get_register(): [esp32c6] Reading s11 from target Debug: 716 3954 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register s11 Debug: 717 3954 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading s11 Debug: 718 3954 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b Debug: 719 3974 riscv-013.c:1561 register_read_direct(): [esp32c6] s11 = 0x0 Debug: 720 3974 riscv.c:4831 riscv_get_register(): [esp32c6] Read s11: 0x0 Debug: 721 3974 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s11 (valid=1). Debug: 722 3974 esp_riscv.c:593 esp_riscv_start_algorithm(): save t3 Debug: 723 3974 riscv.c:4823 riscv_get_register(): [esp32c6] Reading t3 from target Debug: 724 3974 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register t3 Debug: 725 3974 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading t3 Debug: 726 3974 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c Debug: 727 3990 riscv-013.c:1561 register_read_direct(): [esp32c6] t3 = 0x0 Debug: 728 3990 riscv.c:4831 riscv_get_register(): [esp32c6] Read t3: 0x0 Debug: 729 3990 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t3 (valid=1). Debug: 730 3990 esp_riscv.c:593 esp_riscv_start_algorithm(): save t4 Debug: 731 3990 riscv.c:4823 riscv_get_register(): [esp32c6] Reading t4 from target Debug: 732 3990 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register t4 Debug: 733 3990 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading t4 Debug: 734 3990 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d Debug: 735 3999 riscv-013.c:1561 register_read_direct(): [esp32c6] t4 = 0x0 Debug: 736 3999 riscv.c:4831 riscv_get_register(): [esp32c6] Read t4: 0x0 Debug: 737 3999 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t4 (valid=1). Debug: 738 3999 esp_riscv.c:593 esp_riscv_start_algorithm(): save t5 Debug: 739 3999 riscv.c:4823 riscv_get_register(): [esp32c6] Reading t5 from target Debug: 740 3999 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register t5 Debug: 741 3999 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading t5 Debug: 742 3999 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e Debug: 743 4006 riscv-013.c:1561 register_read_direct(): [esp32c6] t5 = 0x0 Debug: 744 4006 riscv.c:4831 riscv_get_register(): [esp32c6] Read t5: 0x0 Debug: 745 4006 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t5 (valid=1). Debug: 746 4006 esp_riscv.c:593 esp_riscv_start_algorithm(): save t6 Debug: 747 4006 riscv.c:4823 riscv_get_register(): [esp32c6] Reading t6 from target Debug: 748 4006 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register t6 Debug: 749 4006 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading t6 Debug: 750 4006 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f Debug: 751 4013 riscv-013.c:1561 register_read_direct(): [esp32c6] t6 = 0x0 Debug: 752 4013 riscv.c:4831 riscv_get_register(): [esp32c6] Read t6: 0x0 Debug: 753 4013 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t6 (valid=1). Debug: 754 4013 esp_riscv.c:593 esp_riscv_start_algorithm(): save pc Debug: 755 4013 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 756 4013 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 757 4013 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 758 4013 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 [OpenOCD] Debug: 759 4021 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40000000 Debug: 760 4021 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40000000 Debug: 761 4021 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40000000 Debug: 762 4021 riscv.c:5259 register_get(): [esp32c6] Read 0x40000000 from pc (valid=0). Debug: 763 4021 esp_riscv.c:593 esp_riscv_start_algorithm(): save mstatus Debug: 764 4021 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mstatus from target Debug: 765 4021 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mstatus Debug: 766 4021 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mstatus Debug: 767 4021 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 768 4028 riscv-013.c:1561 register_read_direct(): [esp32c6] mstatus = 0x201800 Debug: 769 4028 riscv.c:4831 riscv_get_register(): [esp32c6] Read mstatus: 0x201800 Debug: 770 4028 riscv.c:5259 register_get(): [esp32c6] Read 0x00201800 from mstatus (valid=1). Debug: 771 4028 esp_riscv.c:593 esp_riscv_start_algorithm(): save misa Debug: 772 4028 riscv.c:4823 riscv_get_register(): [esp32c6] Reading misa from target Debug: 773 4028 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register misa Debug: 774 4028 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading misa Debug: 775 4028 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 776 4039 riscv-013.c:1561 register_read_direct(): [esp32c6] misa = 0x40903105 Debug: 777 4039 riscv.c:4831 riscv_get_register(): [esp32c6] Read misa: 0x40903105 Debug: 778 4039 riscv.c:5259 register_get(): [esp32c6] Read 0x40903105 from misa (valid=1). Debug: 779 4039 esp_riscv.c:593 esp_riscv_start_algorithm(): save mtvec Debug: 780 4039 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mtvec from target Debug: 781 4039 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr773 Debug: 782 4039 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr773 Debug: 783 4039 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305 Debug: 784 4055 riscv-013.c:1561 register_read_direct(): [esp32c6] csr773 = 0x1 Debug: 785 4055 riscv.c:4831 riscv_get_register(): [esp32c6] Read mtvec: 0x1 Debug: 786 4055 riscv.c:5259 register_get(): [esp32c6] Read 0x00000001 from mtvec (valid=0). Debug: 787 4055 esp_riscv.c:593 esp_riscv_start_algorithm(): save mscratch Debug: 788 4055 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mscratch from target Debug: 789 4055 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr832 Debug: 790 4055 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr832 Debug: 791 4055 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340 [OpenOCD] Debug: 792 4102 riscv-013.c:1561 register_read_direct(): [esp32c6] csr832 = 0x0 Debug: 793 4102 riscv.c:4831 riscv_get_register(): [esp32c6] Read mscratch: 0x0 Debug: 794 4102 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mscratch (valid=0). Debug: 795 4102 esp_riscv.c:593 esp_riscv_start_algorithm(): save mepc Debug: 796 4102 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mepc from target Debug: 797 4102 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mepc Debug: 798 4102 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mepc Debug: 799 4102 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 800 4111 riscv-013.c:1561 register_read_direct(): [esp32c6] mepc = 0x0 Debug: 801 4111 riscv.c:4831 riscv_get_register(): [esp32c6] Read mepc: 0x0 Debug: 802 4111 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mepc (valid=1). Debug: 803 4111 esp_riscv.c:593 esp_riscv_start_algorithm(): save mcause Debug: 804 4111 riscv.c:4819 riscv_get_register(): [esp32c6] Read mcause: 0x0 (cached) Debug: 805 4111 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mcause (valid=1). Debug: 806 4112 esp_riscv.c:593 esp_riscv_start_algorithm(): save mtval Debug: 807 4112 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mtval from target Debug: 808 4112 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr835 Debug: 809 4112 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr835 Debug: 810 4112 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343 Debug: 811 4128 riscv-013.c:1561 register_read_direct(): [esp32c6] csr835 = 0x0 Debug: 812 4128 riscv.c:4831 riscv_get_register(): [esp32c6] Read mtval: 0x0 Debug: 813 4128 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mtval (valid=0). Debug: 814 4128 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg0 Debug: 815 4128 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg0 from target Debug: 816 4128 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr928 Debug: 817 4128 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr928 Debug: 818 4128 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0 Debug: 819 4140 riscv-013.c:1561 register_read_direct(): [esp32c6] csr928 = 0x0 Debug: 820 4140 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg0: 0x0 Debug: 821 4140 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg0 (valid=0). Debug: 822 4140 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg1 Debug: 823 4140 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg1 from target Debug: 824 4140 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr929 Debug: 825 4140 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr929 Debug: 826 4140 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1 Debug: 827 4147 riscv-013.c:1561 register_read_direct(): [esp32c6] csr929 = 0x0 Debug: 828 4147 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg1: 0x0 Debug: 829 4148 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg1 (valid=0). Debug: 830 4148 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg2 Debug: 831 4148 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg2 from target Debug: 832 4148 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr930 Debug: 833 4148 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr930 Debug: 834 4148 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2 Debug: 835 4156 riscv-013.c:1561 register_read_direct(): [esp32c6] csr930 = 0x0 Debug: 836 4156 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg2: 0x0 Debug: 837 4156 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg2 (valid=0). Debug: 838 4156 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg3 Debug: 839 4156 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg3 from target Debug: 840 4156 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr931 Debug: 841 4156 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr931 Debug: 842 4156 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3 [OpenOCD] Debug: 843 4168 riscv-013.c:1561 register_read_direct(): [esp32c6] csr931 = 0x0 Debug: 844 4168 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg3: 0x0 Debug: 845 4168 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg3 (valid=0). Debug: 846 4168 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr0 Debug: 847 4168 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr0 from target Debug: 848 4168 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr944 Debug: 849 4168 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr944 Debug: 850 4168 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0 Debug: 851 4211 riscv-013.c:1561 register_read_direct(): [esp32c6] csr944 = 0x0 Debug: 852 4211 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr0: 0x0 Debug: 853 4211 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr0 (valid=0). Debug: 854 4211 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr1 Debug: 855 4211 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr1 from target Debug: 856 4211 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr945 Debug: 857 4211 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr945 Debug: 858 4211 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1 Debug: 859 4231 riscv-013.c:1561 register_read_direct(): [esp32c6] csr945 = 0x0 Debug: 860 4231 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr1: 0x0 Debug: 861 4231 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr1 (valid=0). Debug: 862 4231 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr2 Debug: 863 4231 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr2 from target Debug: 864 4231 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr946 Debug: 865 4231 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr946 Debug: 866 4231 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2 Debug: 867 4240 riscv-013.c:1561 register_read_direct(): [esp32c6] csr946 = 0x0 Debug: 868 4240 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr2: 0x0 Debug: 869 4240 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr2 (valid=0). Debug: 870 4240 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr3 Debug: 871 4240 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr3 from target Debug: 872 4240 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr947 Debug: 873 4240 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr947 Debug: 874 4240 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3 Debug: 875 4247 riscv-013.c:1561 register_read_direct(): [esp32c6] csr947 = 0x0 Debug: 876 4247 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr3: 0x0 Debug: 877 4247 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr3 (valid=0). Debug: 878 4247 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr4 Debug: 879 4247 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr4 from target Debug: 880 4247 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr948 Debug: 881 4247 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr948 Debug: 882 4247 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4 Debug: 883 4254 riscv-013.c:1561 register_read_direct(): [esp32c6] csr948 = 0x0 Debug: 884 4254 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr4: 0x0 Debug: 885 4254 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr4 (valid=0). Debug: 886 4254 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr5 Debug: 887 4254 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr5 from target Debug: 888 4254 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr949 Debug: 889 4254 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr949 Debug: 890 4254 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5 [OpenOCD] Debug: 891 4261 riscv-013.c:1561 register_read_direct(): [esp32c6] csr949 = 0x0 Debug: 892 4261 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr5: 0x0 Debug: 893 4261 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr5 (valid=0). Debug: 894 4261 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr6 Debug: 895 4261 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr6 from target Debug: 896 4261 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr950 Debug: 897 4261 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr950 Debug: 898 4261 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6 Debug: 899 4271 riscv-013.c:1561 register_read_direct(): [esp32c6] csr950 = 0x0 Debug: 900 4271 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr6: 0x0 Debug: 901 4271 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr6 (valid=0). Debug: 902 4271 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr7 Debug: 903 4271 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr7 from target Debug: 904 4271 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr951 Debug: 905 4271 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr951 Debug: 906 4271 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7 Debug: 907 4280 riscv-013.c:1561 register_read_direct(): [esp32c6] csr951 = 0x0 Debug: 908 4280 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr7: 0x0 Debug: 909 4280 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr7 (valid=0). Debug: 910 4280 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr8 Debug: 911 4280 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr8 from target Debug: 912 4280 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr952 Debug: 913 4280 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr952 Debug: 914 4280 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8 Debug: 915 4291 riscv-013.c:1561 register_read_direct(): [esp32c6] csr952 = 0x0 Debug: 916 4291 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr8: 0x0 Debug: 917 4291 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr8 (valid=0). Debug: 918 4291 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr9 Debug: 919 4291 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr9 from target Debug: 920 4291 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr953 Debug: 921 4291 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr953 Debug: 922 4291 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9 Debug: 923 4319 riscv-013.c:1561 register_read_direct(): [esp32c6] csr953 = 0x0 Debug: 924 4319 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr9: 0x0 Debug: 925 4319 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr9 (valid=0). Debug: 926 4319 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr10 Debug: 927 4319 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr10 from target Debug: 928 4319 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr954 Debug: 929 4319 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr954 Debug: 930 4319 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba [OpenOCD] Debug: 931 4339 riscv-013.c:1561 register_read_direct(): [esp32c6] csr954 = 0x0 Debug: 932 4339 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr10: 0x0 Debug: 933 4339 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr10 (valid=0). Debug: 934 4339 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr11 Debug: 935 4339 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr11 from target Debug: 936 4339 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr955 Debug: 937 4339 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr955 Debug: 938 4339 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb Debug: 939 4348 riscv-013.c:1561 register_read_direct(): [esp32c6] csr955 = 0x0 Debug: 940 4348 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr11: 0x0 Debug: 941 4348 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr11 (valid=0). Debug: 942 4348 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr12 Debug: 943 4348 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr12 from target Debug: 944 4348 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr956 Debug: 945 4348 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr956 Debug: 946 4348 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc Debug: 947 4375 riscv-013.c:1561 register_read_direct(): [esp32c6] csr956 = 0x0 Debug: 948 4375 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr12: 0x0 Debug: 949 4375 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr12 (valid=0). Debug: 950 4375 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr13 Debug: 951 4375 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr13 from target Debug: 952 4375 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr957 Debug: 953 4375 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr957 Debug: 954 4375 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd Debug: 955 4385 riscv-013.c:1561 register_read_direct(): [esp32c6] csr957 = 0x0 Debug: 956 4385 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr13: 0x0 Debug: 957 4385 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr13 (valid=0). Debug: 958 4385 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr14 Debug: 959 4385 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr14 from target Debug: 960 4385 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr958 Debug: 961 4385 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr958 Debug: 962 4385 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be Debug: 963 4391 riscv-013.c:1561 register_read_direct(): [esp32c6] csr958 = 0x0 Debug: 964 4391 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr14: 0x0 Debug: 965 4391 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr14 (valid=0). Debug: 966 4391 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr15 Debug: 967 4391 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr15 from target Debug: 968 4391 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr959 Debug: 969 4391 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr959 Debug: 970 4391 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf [OpenOCD] Debug: 971 4398 riscv-013.c:1561 register_read_direct(): [esp32c6] csr959 = 0x0 Debug: 972 4398 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr15: 0x0 Debug: 973 4398 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr15 (valid=0). Debug: 974 4398 esp_riscv.c:593 esp_riscv_start_algorithm(): save tselect Debug: 975 4398 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 976 4398 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 977 4398 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 978 4398 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 979 4409 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x0 Debug: 980 4409 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x0 Debug: 981 4409 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tselect (valid=0). Debug: 982 4409 esp_riscv.c:593 esp_riscv_start_algorithm(): save tdata1 Debug: 983 4409 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata1 from target Debug: 984 4409 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata1 Debug: 985 4409 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata1 Debug: 986 4409 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 987 4421 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata1 = 0x23e00000 Debug: 988 4421 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata1: 0x23e00000 Debug: 989 4421 riscv.c:5259 register_get(): [esp32c6] Read 0x23e00000 from tdata1 (valid=0). Debug: 990 4421 esp_riscv.c:593 esp_riscv_start_algorithm(): save tdata2 Debug: 991 4421 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata2 from target Debug: 992 4421 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata2 Debug: 993 4421 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata2 Debug: 994 4421 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2 Debug: 995 4431 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata2 = 0x0 Debug: 996 4431 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata2: 0x0 Debug: 997 4431 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tdata2 (valid=0). Debug: 998 4431 esp_riscv.c:593 esp_riscv_start_algorithm(): save tcontrol Debug: 999 4431 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tcontrol from target Debug: 1000 4431 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr1957 Debug: 1001 4431 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr1957 Debug: 1002 4431 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5 Debug: 1003 4441 riscv-013.c:1561 register_read_direct(): [esp32c6] csr1957 = 0x0 Debug: 1004 4441 riscv.c:4831 riscv_get_register(): [esp32c6] Read tcontrol: 0x0 Debug: 1005 4441 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tcontrol (valid=0). Debug: 1006 4441 esp_riscv.c:593 esp_riscv_start_algorithm(): save dcsr Debug: 1007 4441 riscv.c:4819 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 (cached) Debug: 1008 4441 riscv.c:5259 register_get(): [esp32c6] Read 0x400090c3 from dcsr (valid=1). Debug: 1009 4441 esp_riscv.c:593 esp_riscv_start_algorithm(): save dpc Debug: 1010 4441 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dpc from target Debug: 1011 4441 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dpc Debug: 1012 4441 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 1013 4441 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 1014 4449 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40000000 Debug: 1015 4449 riscv.c:4831 riscv_get_register(): [esp32c6] Read dpc: 0x40000000 Debug: 1016 4449 riscv.c:5259 register_get(): [esp32c6] Read 0x40000000 from dpc (valid=1). Debug: 1017 4449 esp_riscv.c:593 esp_riscv_start_algorithm(): save dscratch0 Debug: 1018 4449 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dscratch0 from target Debug: 1019 4449 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dscratch0 Debug: 1020 4449 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dscratch0 Debug: 1021 4449 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2 Debug: 1022 4458 riscv-013.c:1561 register_read_direct(): [esp32c6] dscratch0 = 0x0 Debug: 1023 4458 riscv.c:4831 riscv_get_register(): [esp32c6] Read dscratch0: 0x0 Debug: 1024 4458 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from dscratch0 (valid=1). Debug: 1025 4458 esp_riscv.c:593 esp_riscv_start_algorithm(): save dscratch1 Debug: 1026 4458 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dscratch1 from target Debug: 1027 4458 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr1971 Debug: 1028 4458 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr1971 Debug: 1029 4458 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3 Debug: 1030 4463 riscv-013.c:1561 register_read_direct(): [esp32c6] csr1971 = 0x20000000 Debug: 1031 4463 riscv.c:4831 riscv_get_register(): [esp32c6] Read dscratch1: 0x20000000 Debug: 1032 4463 riscv.c:5259 register_get(): [esp32c6] Read 0x20000000 from dscratch1 (valid=0). Debug: 1033 4463 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpcer Debug: 1034 4463 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpcer from target Debug: 1035 4463 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2016 Debug: 1036 4463 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2016 Debug: 1037 4463 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e0 Debug: 1038 4471 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2016 = 0x0 Debug: 1039 4471 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpcer: 0x0 Debug: 1040 4471 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_mpcer (valid=0). Debug: 1041 4471 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpcmr Debug: 1042 4471 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpcmr from target Debug: 1043 4471 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2017 Debug: 1044 4471 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2017 Debug: 1045 4471 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e1 [OpenOCD] Debug: 1046 4478 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2017 = 0x3 Debug: 1047 4478 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpcmr: 0x3 Debug: 1048 4478 riscv.c:5259 register_get(): [esp32c6] Read 0x00000003 from csr_mpcmr (valid=0). Debug: 1049 4478 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpccr Debug: 1050 4478 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpccr from target Debug: 1051 4478 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2018 Debug: 1052 4478 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2018 Debug: 1053 4478 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e2 Debug: 1054 4487 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2018 = 0x0 Debug: 1055 4487 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpccr: 0x0 Debug: 1056 4487 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_mpccr (valid=0). Debug: 1057 4487 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_oen Debug: 1058 4487 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_oen from target Debug: 1059 4487 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2051 Debug: 1060 4487 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2051 Debug: 1061 4487 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220803; access register, size=32, postexec=0, transfer=1, write=0, regno=0x803 Debug: 1062 4494 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2051 = 0x0 Debug: 1063 4494 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_oen: 0x0 Debug: 1064 4494 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_oen (valid=0). Debug: 1065 4494 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_in Debug: 1066 4494 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_in from target Debug: 1067 4494 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2052 Debug: 1068 4494 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2052 Debug: 1069 4494 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220804; access register, size=32, postexec=0, transfer=1, write=0, regno=0x804 Debug: 1070 4504 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2052 = 0x0 Debug: 1071 4504 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_in: 0x0 Debug: 1072 4504 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_in (valid=0). Debug: 1073 4504 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_out Debug: 1074 4504 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_out from target Debug: 1075 4504 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2053 Debug: 1076 4504 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2053 Debug: 1077 4504 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220805; access register, size=32, postexec=0, transfer=1, write=0, regno=0x805 Debug: 1078 4511 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2053 = 0x0 Debug: 1079 4511 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_out: 0x0 Debug: 1080 4511 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_out (valid=0). Debug: 1081 4511 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg0 Debug: 1082 4511 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg0 from target Debug: 1083 4511 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3008 Debug: 1084 4511 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3008 Debug: 1085 4511 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc0 Debug: 1086 4516 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3008 = 0x0 Debug: 1087 4516 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg0: 0x0 Debug: 1088 4516 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg0 (valid=0). Debug: 1089 4516 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg1 Debug: 1090 4516 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg1 from target Debug: 1091 4516 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3009 Debug: 1092 4516 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3009 Debug: 1093 4516 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc1; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc1 [OpenOCD] Debug: 1094 4522 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3009 = 0x0 Debug: 1095 4522 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg1: 0x0 Debug: 1096 4522 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg1 (valid=0). Debug: 1097 4522 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg2 Debug: 1098 4522 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg2 from target Debug: 1099 4522 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3010 Debug: 1100 4522 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3010 Debug: 1101 4522 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc2; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc2 Debug: 1102 4580 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3010 = 0x0 Debug: 1103 4580 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg2: 0x0 Debug: 1104 4580 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg2 (valid=0). Debug: 1105 4580 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg3 Debug: 1106 4580 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg3 from target Debug: 1107 4580 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3011 Debug: 1108 4580 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3011 Debug: 1109 4580 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc3; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc3 Debug: 1110 4609 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3011 = 0x0 Debug: 1111 4609 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg3: 0x0 Debug: 1112 4609 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg3 (valid=0). Debug: 1113 4609 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg4 Debug: 1114 4609 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg4 from target Debug: 1115 4609 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3012 Debug: 1116 4609 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3012 Debug: 1117 4609 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc4; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc4 Debug: 1118 4620 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3012 = 0x0 Debug: 1119 4620 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg4: 0x0 Debug: 1120 4620 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg4 (valid=0). Debug: 1121 4620 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg5 Debug: 1122 4620 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg5 from target Debug: 1123 4620 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3013 Debug: 1124 4620 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3013 Debug: 1125 4620 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc5; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc5 Debug: 1126 4628 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3013 = 0x0 Debug: 1127 4629 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg5: 0x0 Debug: 1128 4629 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg5 (valid=0). Debug: 1129 4629 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg6 Debug: 1130 4629 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg6 from target Debug: 1131 4629 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3014 Debug: 1132 4629 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3014 Debug: 1133 4629 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc6; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc6 [OpenOCD] Debug: 1134 4640 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3014 = 0x0 Debug: 1135 4640 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg6: 0x0 Debug: 1136 4640 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg6 (valid=0). Debug: 1137 4640 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg7 Debug: 1138 4640 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg7 from target Debug: 1139 4640 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3015 Debug: 1140 4640 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3015 Debug: 1141 4640 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc7; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc7 Debug: 1142 4648 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3015 = 0x0 Debug: 1143 4648 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg7: 0x0 Debug: 1144 4648 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg7 (valid=0). Debug: 1145 4648 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg8 Debug: 1146 4648 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg8 from target Debug: 1147 4648 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3016 Debug: 1148 4648 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3016 Debug: 1149 4648 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc8; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc8 Debug: 1150 4659 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3016 = 0x0 Debug: 1151 4659 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg8: 0x0 Debug: 1152 4659 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg8 (valid=0). Debug: 1153 4659 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg9 Debug: 1154 4659 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg9 from target Debug: 1155 4659 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3017 Debug: 1156 4659 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3017 Debug: 1157 4659 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc9; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc9 Debug: 1158 4669 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3017 = 0x0 Debug: 1159 4669 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg9: 0x0 Debug: 1160 4669 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg9 (valid=0). Debug: 1161 4669 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg10 Debug: 1162 4669 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg10 from target Debug: 1163 4669 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3018 Debug: 1164 4669 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3018 Debug: 1165 4669 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bca; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbca Debug: 1166 4678 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3018 = 0x0 Debug: 1167 4678 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg10: 0x0 Debug: 1168 4678 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg10 (valid=0). Debug: 1169 4678 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg11 Debug: 1170 4678 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg11 from target Debug: 1171 4678 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3019 Debug: 1172 4678 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3019 Debug: 1173 4678 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcb; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcb Debug: 1174 4685 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3019 = 0x0 Debug: 1175 4685 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg11: 0x0 Debug: 1176 4685 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg11 (valid=0). Debug: 1177 4685 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg12 Debug: 1178 4685 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg12 from target Debug: 1179 4685 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3020 Debug: 1180 4685 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3020 Debug: 1181 4685 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcc; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcc Debug: 1182 4691 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3020 = 0x0 Debug: 1183 4691 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg12: 0x0 Debug: 1184 4691 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg12 (valid=0). Debug: 1185 4691 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg13 Debug: 1186 4691 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg13 from target Debug: 1187 4691 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3021 Debug: 1188 4691 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3021 Debug: 1189 4691 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcd; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcd Debug: 1190 4697 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3021 = 0x0 Debug: 1191 4697 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg13: 0x0 Debug: 1192 4697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg13 (valid=0). Debug: 1193 4697 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg14 Debug: 1194 4697 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg14 from target Debug: 1195 4697 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3022 Debug: 1196 4697 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3022 Debug: 1197 4697 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bce; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbce Debug: 1198 4704 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3022 = 0x0 Debug: 1199 4704 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg14: 0x0 Debug: 1200 4704 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg14 (valid=0). Debug: 1201 4704 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg15 Debug: 1202 4704 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg15 from target Debug: 1203 4704 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3023 Debug: 1204 4704 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3023 Debug: 1205 4704 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcf; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcf [OpenOCD] Debug: 1206 4712 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3023 = 0x0 Debug: 1207 4712 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg15: 0x0 Debug: 1208 4712 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg15 (valid=0). Debug: 1209 4712 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr0 Debug: 1210 4712 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr0 from target Debug: 1211 4712 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3024 Debug: 1212 4712 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3024 Debug: 1213 4712 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd0 Debug: 1214 4722 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3024 = 0x0 Debug: 1215 4722 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr0: 0x0 Debug: 1216 4722 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr0 (valid=0). Debug: 1217 4722 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr1 Debug: 1218 4722 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr1 from target Debug: 1219 4722 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3025 Debug: 1220 4722 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3025 Debug: 1221 4722 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd1; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd1 Debug: 1222 4732 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3025 = 0x0 Debug: 1223 4732 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr1: 0x0 Debug: 1224 4732 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr1 (valid=0). Debug: 1225 4732 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr2 Debug: 1226 4732 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr2 from target Debug: 1227 4732 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3026 Debug: 1228 4732 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3026 Debug: 1229 4732 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd2; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd2 Debug: 1230 4792 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3026 = 0x0 Debug: 1231 4792 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr2: 0x0 Debug: 1232 4792 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr2 (valid=0). Debug: 1233 4792 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr3 Debug: 1234 4792 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr3 from target Debug: 1235 4792 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3027 Debug: 1236 4792 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3027 Debug: 1237 4792 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd3; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd3 [OpenOCD] Debug: 1238 4804 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3027 = 0x0 Debug: 1239 4804 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr3: 0x0 Debug: 1240 4804 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr3 (valid=0). Debug: 1241 4804 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr4 Debug: 1242 4804 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr4 from target Debug: 1243 4804 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3028 Debug: 1244 4804 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3028 Debug: 1245 4804 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd4; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd4 Debug: 1246 4830 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3028 = 0x0 Debug: 1247 4830 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr4: 0x0 Debug: 1248 4830 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr4 (valid=0). Debug: 1249 4830 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr5 Debug: 1250 4830 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr5 from target Debug: 1251 4830 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3029 Debug: 1252 4830 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3029 Debug: 1253 4830 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd5; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd5 Debug: 1254 4844 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3029 = 0x0 Debug: 1255 4844 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr5: 0x0 Debug: 1256 4844 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr5 (valid=0). Debug: 1257 4844 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr6 Debug: 1258 4844 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr6 from target Debug: 1259 4844 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3030 Debug: 1260 4844 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3030 Debug: 1261 4844 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd6; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd6 Debug: 1262 4850 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3030 = 0x0 Debug: 1263 4850 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr6: 0x0 Debug: 1264 4850 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr6 (valid=0). Debug: 1265 4850 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr7 Debug: 1266 4850 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr7 from target Debug: 1267 4850 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3031 Debug: 1268 4850 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3031 Debug: 1269 4850 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd7; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd7 Debug: 1270 4856 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3031 = 0x0 Debug: 1271 4856 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr7: 0x0 Debug: 1272 4856 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr7 (valid=0). Debug: 1273 4856 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr8 Debug: 1274 4856 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr8 from target Debug: 1275 4856 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3032 Debug: 1276 4856 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3032 Debug: 1277 4856 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd8; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd8 [OpenOCD] Debug: 1278 4861 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3032 = 0x0 Debug: 1279 4861 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr8: 0x0 Debug: 1280 4861 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr8 (valid=0). Debug: 1281 4861 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr9 Debug: 1282 4861 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr9 from target Debug: 1283 4861 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3033 Debug: 1284 4861 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3033 Debug: 1285 4861 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd9; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd9 Debug: 1286 4869 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3033 = 0x0 Debug: 1287 4869 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr9: 0x0 Debug: 1288 4869 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr9 (valid=0). Debug: 1289 4869 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr10 Debug: 1290 4869 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr10 from target Debug: 1291 4869 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3034 Debug: 1292 4869 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3034 Debug: 1293 4869 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bda; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbda Debug: 1294 4878 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3034 = 0x0 Debug: 1295 4878 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr10: 0x0 Debug: 1296 4878 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr10 (valid=0). Debug: 1297 4878 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr11 Debug: 1298 4878 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr11 from target Debug: 1299 4878 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3035 Debug: 1300 4878 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3035 Debug: 1301 4878 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdb; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdb Debug: 1302 4889 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3035 = 0x0 Debug: 1303 4889 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr11: 0x0 Debug: 1304 4889 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr11 (valid=0). Debug: 1305 4889 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr12 Debug: 1306 4889 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr12 from target Debug: 1307 4889 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3036 Debug: 1308 4889 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3036 Debug: 1309 4889 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdc; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdc Debug: 1310 4896 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3036 = 0x0 Debug: 1311 4896 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr12: 0x0 Debug: 1312 4896 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr12 (valid=0). Debug: 1313 4896 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr13 Debug: 1314 4896 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr13 from target Debug: 1315 4896 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3037 Debug: 1316 4896 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3037 Debug: 1317 4896 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdd; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdd Debug: 1318 4905 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3037 = 0x0 Debug: 1319 4905 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr13: 0x0 Debug: 1320 4905 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr13 (valid=0). Debug: 1321 4905 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr14 Debug: 1322 4905 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr14 from target Debug: 1323 4905 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3038 Debug: 1324 4905 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3038 Debug: 1325 4905 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bde; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbde Debug: 1326 4911 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3038 = 0x0 Debug: 1327 4911 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr14: 0x0 Debug: 1328 4911 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr14 (valid=0). Debug: 1329 4911 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr15 Debug: 1330 4911 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr15 from target Debug: 1331 4911 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3039 Debug: 1332 4911 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3039 Debug: 1333 4911 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdf; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdf Debug: 1334 4917 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3039 = 0x0 Debug: 1335 4917 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr15: 0x0 Debug: 1336 4917 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr15 (valid=0). Debug: 1337 4917 esp_riscv.c:593 esp_riscv_start_algorithm(): save hpmcounter16 Debug: 1338 4917 riscv.c:4823 riscv_get_register(): [esp32c6] Reading hpmcounter16 from target Debug: 1339 4917 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3088 Debug: 1340 4917 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3088 Debug: 1341 4917 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10 [OpenOCD] Debug: 1342 4923 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3088 = 0x3 Debug: 1343 4923 riscv.c:4831 riscv_get_register(): [esp32c6] Read hpmcounter16: 0x3 Debug: 1344 4923 riscv.c:5259 register_get(): [esp32c6] Read 0x00000003 from hpmcounter16 (valid=0). Debug: 1345 4923 esp_riscv.c:593 esp_riscv_start_algorithm(): save priv Debug: 1346 4923 riscv.c:4823 riscv_get_register(): [esp32c6] Reading priv from target Debug: 1347 4923 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register priv Debug: 1348 4923 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 1349 4923 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 1350 4930 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 1351 4930 riscv.c:4831 riscv_get_register(): [esp32c6] Read priv: 0x3 Debug: 1352 4930 riscv.c:5259 register_get(): [esp32c6] Read 0x03 from priv (valid=0). Debug: 1353 4930 esp_riscv.c:622 esp_riscv_start_algorithm(): set sp Debug: 1354 4930 riscv.c:5274 register_set(): [esp32c6] Write 0x40804780 to sp (valid=1). Debug: 1355 4930 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804780 to sp (cacheable=true, valid=true, dirty=false) Debug: 1356 4930 esp_riscv.c:622 esp_riscv_start_algorithm(): set a7 Debug: 1357 4930 riscv.c:5274 register_set(): [esp32c6] Write 0x4080110c to a7 (valid=1). Debug: 1358 4930 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4080110c to a7 (cacheable=true, valid=true, dirty=true) Debug: 1359 4930 esp_riscv.c:622 esp_riscv_start_algorithm(): set a0 Debug: 1360 4930 riscv.c:5274 register_set(): [esp32c6] Write 0x00000005 to a0 (valid=1). Debug: 1361 4930 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x5 to a0 (cacheable=true, valid=true, dirty=true) Debug: 1362 4930 esp_riscv.c:622 esp_riscv_start_algorithm(): set a1 Debug: 1363 4930 riscv.c:5274 register_set(): [esp32c6] Write 0xffffffff to a1 (valid=1). Debug: 1364 4930 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0xffffffff to a1 (cacheable=true, valid=true, dirty=true) Debug: 1365 4930 esp_riscv.c:622 esp_riscv_start_algorithm(): set a2 Debug: 1366 4930 riscv.c:5274 register_set(): [esp32c6] Write 0x40804794 to a2 (valid=1). Debug: 1367 4930 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804794 to a2 (cacheable=true, valid=true, dirty=true) Debug: 1368 4930 riscv.c:4550 riscv_interrupts_disable(): [esp32c6] Disabling interrupts. Debug: 1369 4930 riscv.c:4819 riscv_get_register(): [esp32c6] Read mstatus: 0x201800 (cached) Debug: 1370 4930 riscv.c:5259 register_get(): [esp32c6] Read 0x00201800 from mstatus (valid=1). Debug: 1371 4930 riscv.c:5274 register_set(): [esp32c6] Write 0x00201800 to mstatus (valid=1). Debug: 1372 4930 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x201800 to mstatus (cacheable=true, valid=true, dirty=false) Debug: 1373 4930 esp_riscv.c:659 esp_riscv_start_algorithm(): resume at 0x40801454 Debug: 1374 4930 riscv.c:1932 riscv_resume(): [esp32c6] current=false, address=0x40801454, handle_breakpoints=false, debug_exec=true Debug: 1375 4930 riscv.c:1937 riscv_resume(): [esp32c6] target->state=halted Debug: 1376 4930 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pc <- 0x40801454 (cacheable=false, valid=false, dirty=false) Debug: 1377 4930 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40801454 to register pc Debug: 1378 4930 riscv-013.c:4562 riscv013_set_register(): [esp32c6] writing PC to DPC: 0x40801454 Debug: 1379 4930 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40801454 to dpc Debug: 1380 4935 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 1381 4939 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40801454 Debug: 1382 4939 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40801454 to pc (cacheable=false, valid=false, dirty=false) Debug: 1383 4939 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[00] = DASM(0x0000100f) Debug: 1384 4942 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[01] = DASM(0x0330000f) Debug: 1385 4944 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[02] = DASM(0x00100073) Debug: 1386 4947 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 1387 4971 riscv-013.c:1591 set_dcsr_ebreak(): [esp32c6] Set dcsr.ebreak* Debug: 1388 4971 riscv.c:4819 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 (cached) Debug: 1389 4971 riscv.c:1575 riscv_flush_registers(): [esp32c6] a7 is dirty; write back 0x4080110c Debug: 1390 4971 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4080110c to register a7 Debug: 1391 4971 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4080110c to a7 [OpenOCD] Debug: 1392 4984 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 1393 4997 riscv-013.c:1532 register_write_direct(): [esp32c6] a7 <- 0x4080110c Debug: 1394 4997 riscv.c:1575 riscv_flush_registers(): [esp32c6] a2 is dirty; write back 0x40804794 Debug: 1395 4997 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40804794 to register a2 Debug: 1396 4997 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40804794 to a2 Debug: 1397 5009 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 1398 5018 riscv-013.c:1532 register_write_direct(): [esp32c6] a2 <- 0x40804794 Debug: 1399 5018 riscv.c:1575 riscv_flush_registers(): [esp32c6] a1 is dirty; write back 0xffffffff Debug: 1400 5018 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0xffffffff to register a1 Debug: 1401 5018 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0xffffffff to a1 Debug: 1402 5023 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 1403 5029 riscv-013.c:1532 register_write_direct(): [esp32c6] a1 <- 0xffffffff Debug: 1404 5029 riscv.c:1575 riscv_flush_registers(): [esp32c6] a0 is dirty; write back 0x5 Debug: 1405 5029 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x5 to register a0 Debug: 1406 5029 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x5 to a0 Debug: 1407 5046 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 1408 5051 riscv-013.c:1532 register_write_direct(): [esp32c6] a0 <- 0x5 Debug: 1409 5051 riscv.c:1858 resume_prep(): [esp32c6] Mark as prepped. Debug: 1410 5051 riscv.c:4536 riscv_resume_go_all_harts(): [esp32c6] Resuming hart, state=2. Debug: 1411 5051 riscv-013.c:4625 select_prepped_harts(): [esp32c6] index=0, coreid=0, prepped=1 Debug: 1412 5051 riscv-013.c:4922 riscv013_step_or_resume_current_hart(): [esp32c6] resuming (for step?=0) Debug: 1413 5060 riscv.c:4640 riscv_invalidate_register_cache(): [esp32c6] Invalidating register cache. Debug: 1414 5060 target.c:1812 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c6 Debug: 1415 5060 esp_algorithm.c:111 algorithm_run_image(): Wait algorithm completion Debug: 1416 5063 riscv.c:2779 riscv_poll_hart(): [esp32c6] triggered a halt; previous_target_state=4 Debug: 1417 5063 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 1418 5063 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 [OpenOCD] Debug: 1419 5072 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x40009043 Debug: 1420 5072 riscv-013.c:4791 riscv013_halt_reason(): [esp32c6] dcsr.cause: 0x1 Debug: 1421 5072 riscv.c:1621 set_debug_reason(): [esp32c6] debug_reason=1 Debug: 1422 5072 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 1423 5072 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 1424 5072 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 1425 5072 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 1426 5081 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40801456 Debug: 1427 5081 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40801456 Debug: 1428 5081 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40801456 Debug: 1429 5081 esp_riscv.c:799 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40801452 Debug: 1430 5108 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 1431 5108 riscv_semihosting.c:94 riscv_semihosting(): [esp32c6] compare 0x98820613 from 0x40801452 against 0x01f01013 Debug: 1432 5108 riscv_semihosting.c:96 riscv_semihosting(): [esp32c6] -> NONE (no magic) Debug: 1433 5108 target.c:1812 target_call_event_callbacks(): target event 17 (debug-halted) for core esp32c6 Debug: 1434 5108 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 1435 5108 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 1436 5108 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 1437 5108 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 1438 5114 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40801456 Debug: 1439 5114 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40801456 Debug: 1440 5114 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40801456 Debug: 1441 5114 riscv.c:5259 register_get(): [esp32c6] Read 0x40801456 from pc (valid=0). Debug: 1442 5114 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a0 from target Debug: 1443 5114 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a0 Debug: 1444 5114 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a0 Debug: 1445 5114 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 1446 5119 riscv-013.c:1561 register_read_direct(): [esp32c6] a0 = 0x0 Debug: 1447 5119 riscv.c:4831 riscv_get_register(): [esp32c6] Read a0: 0x0 Debug: 1448 5119 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from a0 (valid=1). Debug: 1449 5119 esp_riscv.c:733 esp_riscv_wait_algorithm(): Read mem params Debug: 1450 5119 esp_riscv.c:735 esp_riscv_wait_algorithm(): Check mem param @ 0x40804794 Debug: 1451 5119 esp_riscv.c:737 esp_riscv_wait_algorithm(): Read mem param @ 0x40804794 Debug: 1452 5119 target.c:2444 target_read_buffer(): reading buffer of 28 byte at 0x40804794 [OpenOCD] Debug: 1453 5147 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 1454 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore ra Debug: 1455 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x40801456 to ra (valid=0). Debug: 1456 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40801456 to ra (cacheable=true, valid=true, dirty=true) Debug: 1457 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore sp Debug: 1458 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x40804780 to sp (valid=0). Debug: 1459 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804780 to sp (cacheable=true, valid=true, dirty=true) Debug: 1460 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore gp Debug: 1461 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to gp (valid=0). Debug: 1462 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to gp (cacheable=true, valid=true, dirty=true) Debug: 1463 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tp Debug: 1464 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tp (valid=0). Debug: 1465 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tp (cacheable=true, valid=true, dirty=true) Debug: 1466 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t0 Debug: 1467 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x40027bd4 to t0 (valid=0). Debug: 1468 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40027bd4 to t0 (cacheable=true, valid=true, dirty=true) Debug: 1469 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t1 Debug: 1470 5147 riscv.c:5274 register_set(): [esp32c6] Write 0xffffffe0 to t1 (valid=0). Debug: 1471 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0xffffffe0 to t1 (cacheable=true, valid=true, dirty=true) Debug: 1472 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t2 Debug: 1473 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t2 (valid=0). Debug: 1474 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t2 (cacheable=true, valid=true, dirty=true) Debug: 1475 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore fp Debug: 1476 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to fp (valid=0). Debug: 1477 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to fp (cacheable=true, valid=true, dirty=true) Debug: 1478 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s1 Debug: 1479 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s1 (valid=0). Debug: 1480 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s1 (cacheable=true, valid=true, dirty=true) Debug: 1481 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a0 Debug: 1482 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x20000000 to a0 (valid=1). Debug: 1483 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x20000000 to a0 (cacheable=true, valid=true, dirty=true) Debug: 1484 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a1 Debug: 1485 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x60002000 to a1 (valid=0). Debug: 1486 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x60002000 to a1 (cacheable=true, valid=true, dirty=true) Debug: 1487 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a2 Debug: 1488 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000010 to a2 (valid=0). Debug: 1489 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x10 to a2 (cacheable=true, valid=true, dirty=true) Debug: 1490 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a3 Debug: 1491 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00010000 to a3 (valid=0). Debug: 1492 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x10000 to a3 (cacheable=true, valid=true, dirty=true) Debug: 1493 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a4 Debug: 1494 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x408021e0 to a4 (valid=0). Debug: 1495 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x408021e0 to a4 (cacheable=true, valid=true, dirty=true) Debug: 1496 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a5 Debug: 1497 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000004 to a5 (valid=0). Debug: 1498 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4 to a5 (cacheable=true, valid=true, dirty=true) Debug: 1499 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a6 Debug: 1500 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000008 to a6 (valid=0). Debug: 1501 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x8 to a6 (cacheable=true, valid=true, dirty=true) Debug: 1502 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a7 Debug: 1503 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x80000000 to a7 (valid=0). Debug: 1504 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x80000000 to a7 (cacheable=true, valid=true, dirty=true) Debug: 1505 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s2 Debug: 1506 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s2 (valid=0). Debug: 1507 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s2 (cacheable=true, valid=true, dirty=true) Debug: 1508 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s3 Debug: 1509 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s3 (valid=0). Debug: 1510 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s3 (cacheable=true, valid=true, dirty=true) Debug: 1511 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s4 Debug: 1512 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s4 (valid=0). Debug: 1513 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s4 (cacheable=true, valid=true, dirty=true) Debug: 1514 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s5 Debug: 1515 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s5 (valid=0). Debug: 1516 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s5 (cacheable=true, valid=true, dirty=true) Debug: 1517 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s6 Debug: 1518 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s6 (valid=0). Debug: 1519 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s6 (cacheable=true, valid=true, dirty=true) Debug: 1520 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s7 Debug: 1521 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s7 (valid=0). Debug: 1522 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s7 (cacheable=true, valid=true, dirty=true) Debug: 1523 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s8 Debug: 1524 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s8 (valid=0). Debug: 1525 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s8 (cacheable=true, valid=true, dirty=true) Debug: 1526 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s9 Debug: 1527 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s9 (valid=0). Debug: 1528 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s9 (cacheable=true, valid=true, dirty=true) Debug: 1529 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s10 Debug: 1530 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s10 (valid=0). Debug: 1531 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s10 (cacheable=true, valid=true, dirty=true) Debug: 1532 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s11 Debug: 1533 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s11 (valid=0). Debug: 1534 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s11 (cacheable=true, valid=true, dirty=true) Debug: 1535 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t3 Debug: 1536 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t3 (valid=0). Debug: 1537 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t3 (cacheable=true, valid=true, dirty=true) Debug: 1538 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t4 Debug: 1539 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t4 (valid=0). Debug: 1540 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t4 (cacheable=true, valid=true, dirty=true) Debug: 1541 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t5 Debug: 1542 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t5 (valid=0). Debug: 1543 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t5 (cacheable=true, valid=true, dirty=true) Debug: 1544 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t6 Debug: 1545 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t6 (valid=0). Debug: 1546 5147 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t6 (cacheable=true, valid=true, dirty=true) Debug: 1547 5147 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pc Debug: 1548 5147 riscv.c:5274 register_set(): [esp32c6] Write 0x40000000 to pc (valid=0). Debug: 1549 5147 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pc <- 0x40000000 (cacheable=false, valid=false, dirty=false) Debug: 1550 5147 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40000000 to register pc Debug: 1551 5147 riscv-013.c:4562 riscv013_set_register(): [esp32c6] writing PC to DPC: 0x40000000 Debug: 1552 5147 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40000000 to dpc Debug: 1553 5159 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 1554 5206 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40000000 Debug: 1555 5206 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40000000 to pc (cacheable=false, valid=false, dirty=false) Debug: 1556 5206 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mstatus Debug: 1557 5206 riscv.c:5274 register_set(): [esp32c6] Write 0x00201800 to mstatus (valid=0). Debug: 1558 5206 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mstatus <- 0x201800 (cacheable=false, valid=false, dirty=false) Debug: 1559 5206 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x201800 to register mstatus Debug: 1560 5206 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x201800 to mstatus [OpenOCD] Debug: 1561 5231 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 1562 5246 riscv-013.c:1532 register_write_direct(): [esp32c6] mstatus <- 0x201800 Debug: 1563 5246 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x201800 to mstatus (cacheable=false, valid=false, dirty=false) Debug: 1564 5246 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore misa Debug: 1565 5246 riscv.c:5274 register_set(): [esp32c6] Write 0x40903105 to misa (valid=0). Debug: 1566 5246 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: misa <- 0x40903105 (cacheable=false, valid=false, dirty=false) Debug: 1567 5246 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40903105 to register misa Debug: 1568 5246 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40903105 to misa Debug: 1569 5253 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301 Debug: 1570 5260 riscv-013.c:1532 register_write_direct(): [esp32c6] misa <- 0x40903105 Debug: 1571 5260 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40903105 to misa (cacheable=false, valid=false, dirty=false) Debug: 1572 5260 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mtvec Debug: 1573 5260 riscv.c:5274 register_set(): [esp32c6] Write 0x00000001 to mtvec (valid=0). Debug: 1574 5260 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mtvec <- 0x1 (cacheable=false, valid=false, dirty=false) Debug: 1575 5260 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x1 to register csr773 Debug: 1576 5260 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x1 to csr773 Debug: 1577 5265 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305 Debug: 1578 5272 riscv-013.c:1532 register_write_direct(): [esp32c6] csr773 <- 0x1 Debug: 1579 5272 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x1 to mtvec (cacheable=false, valid=false, dirty=false) Debug: 1580 5272 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mscratch Debug: 1581 5272 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mscratch (valid=0). Debug: 1582 5272 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mscratch <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1583 5272 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr832 Debug: 1584 5272 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr832 Debug: 1585 5275 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340 Debug: 1586 5283 riscv-013.c:1532 register_write_direct(): [esp32c6] csr832 <- 0x0 Debug: 1587 5283 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mscratch (cacheable=false, valid=false, dirty=false) Debug: 1588 5283 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mepc Debug: 1589 5283 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mepc (valid=0). Debug: 1590 5283 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mepc <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1591 5283 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register mepc Debug: 1592 5283 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to mepc Debug: 1593 5286 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341 Debug: 1594 5290 riscv-013.c:1532 register_write_direct(): [esp32c6] mepc <- 0x0 Debug: 1595 5290 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mepc (cacheable=false, valid=false, dirty=false) Debug: 1596 5290 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mcause Debug: 1597 5290 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mcause (valid=0). Debug: 1598 5290 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mcause <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1599 5290 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register mcause Debug: 1600 5290 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to mcause Debug: 1601 5293 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342 [OpenOCD] Debug: 1602 5297 riscv-013.c:1532 register_write_direct(): [esp32c6] mcause <- 0x0 Debug: 1603 5297 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mcause (cacheable=false, valid=false, dirty=false) Debug: 1604 5297 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mtval Debug: 1605 5297 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mtval (valid=0). Debug: 1606 5297 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mtval <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1607 5297 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr835 Debug: 1608 5297 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr835 Debug: 1609 5301 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343 Debug: 1610 5305 riscv-013.c:1532 register_write_direct(): [esp32c6] csr835 <- 0x0 Debug: 1611 5305 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mtval (cacheable=false, valid=false, dirty=false) Debug: 1612 5305 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg0 Debug: 1613 5305 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg0 (valid=0). Debug: 1614 5305 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1615 5305 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr928 Debug: 1616 5305 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr928 Debug: 1617 5308 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0 Debug: 1618 5313 riscv-013.c:1532 register_write_direct(): [esp32c6] csr928 <- 0x0 Debug: 1619 5313 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg0 (cacheable=false, valid=false, dirty=false) Debug: 1620 5313 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg1 Debug: 1621 5313 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg1 (valid=0). Debug: 1622 5313 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1623 5313 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr929 Debug: 1624 5313 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr929 Debug: 1625 5316 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1 Debug: 1626 5321 riscv-013.c:1532 register_write_direct(): [esp32c6] csr929 <- 0x0 Debug: 1627 5321 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg1 (cacheable=false, valid=false, dirty=false) Debug: 1628 5321 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg2 Debug: 1629 5321 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg2 (valid=0). Debug: 1630 5321 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1631 5321 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr930 Debug: 1632 5321 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr930 Debug: 1633 5325 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2 Debug: 1634 5330 riscv-013.c:1532 register_write_direct(): [esp32c6] csr930 <- 0x0 Debug: 1635 5330 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg2 (cacheable=false, valid=false, dirty=false) Debug: 1636 5330 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg3 Debug: 1637 5330 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg3 (valid=0). Debug: 1638 5330 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1639 5330 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr931 Debug: 1640 5330 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr931 Debug: 1641 5334 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3 Debug: 1642 5338 riscv-013.c:1532 register_write_direct(): [esp32c6] csr931 <- 0x0 Debug: 1643 5338 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg3 (cacheable=false, valid=false, dirty=false) Debug: 1644 5338 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr0 Debug: 1645 5338 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr0 (valid=0). Debug: 1646 5338 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1647 5338 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr944 Debug: 1648 5338 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr944 Debug: 1649 5341 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0 Debug: 1650 5345 riscv-013.c:1532 register_write_direct(): [esp32c6] csr944 <- 0x0 Debug: 1651 5345 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr0 (cacheable=false, valid=false, dirty=false) Debug: 1652 5345 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr1 Debug: 1653 5345 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr1 (valid=0). Debug: 1654 5345 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1655 5345 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr945 Debug: 1656 5345 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr945 Debug: 1657 5347 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1 Debug: 1658 5352 riscv-013.c:1532 register_write_direct(): [esp32c6] csr945 <- 0x0 Debug: 1659 5352 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr1 (cacheable=false, valid=false, dirty=false) Debug: 1660 5352 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr2 Debug: 1661 5352 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr2 (valid=0). Debug: 1662 5352 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1663 5352 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr946 Debug: 1664 5352 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr946 [OpenOCD] Debug: 1665 5355 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2 Debug: 1666 5359 riscv-013.c:1532 register_write_direct(): [esp32c6] csr946 <- 0x0 Debug: 1667 5359 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr2 (cacheable=false, valid=false, dirty=false) Debug: 1668 5359 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr3 Debug: 1669 5359 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr3 (valid=0). Debug: 1670 5359 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1671 5359 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr947 Debug: 1672 5359 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr947 Debug: 1673 5362 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3 Debug: 1674 5367 riscv-013.c:1532 register_write_direct(): [esp32c6] csr947 <- 0x0 Debug: 1675 5367 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr3 (cacheable=false, valid=false, dirty=false) Debug: 1676 5367 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr4 Debug: 1677 5367 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr4 (valid=0). Debug: 1678 5367 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1679 5367 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr948 Debug: 1680 5367 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr948 Debug: 1681 5372 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4 Debug: 1682 5411 riscv-013.c:1532 register_write_direct(): [esp32c6] csr948 <- 0x0 Debug: 1683 5411 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr4 (cacheable=false, valid=false, dirty=false) Debug: 1684 5411 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr5 Debug: 1685 5411 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr5 (valid=0). Debug: 1686 5411 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1687 5411 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr949 Debug: 1688 5411 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr949 Debug: 1689 5425 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5 [OpenOCD] Debug: 1690 5435 riscv-013.c:1532 register_write_direct(): [esp32c6] csr949 <- 0x0 Debug: 1691 5435 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr5 (cacheable=false, valid=false, dirty=false) Debug: 1692 5435 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr6 Debug: 1693 5435 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr6 (valid=0). Debug: 1694 5435 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1695 5435 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr950 Debug: 1696 5435 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr950 Debug: 1697 5440 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6 Debug: 1698 5448 riscv-013.c:1532 register_write_direct(): [esp32c6] csr950 <- 0x0 Debug: 1699 5448 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr6 (cacheable=false, valid=false, dirty=false) Debug: 1700 5448 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr7 Debug: 1701 5448 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr7 (valid=0). Debug: 1702 5448 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1703 5448 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr951 Debug: 1704 5448 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr951 Debug: 1705 5455 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7 Debug: 1706 5464 riscv-013.c:1532 register_write_direct(): [esp32c6] csr951 <- 0x0 Debug: 1707 5464 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr7 (cacheable=false, valid=false, dirty=false) Debug: 1708 5464 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr8 Debug: 1709 5464 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr8 (valid=0). Debug: 1710 5464 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1711 5464 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr952 Debug: 1712 5464 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr952 Debug: 1713 5480 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8 Debug: 1714 5489 riscv-013.c:1532 register_write_direct(): [esp32c6] csr952 <- 0x0 Debug: 1715 5489 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr8 (cacheable=false, valid=false, dirty=false) Debug: 1716 5489 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr9 Debug: 1717 5489 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr9 (valid=0). Debug: 1718 5489 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1719 5489 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr953 Debug: 1720 5489 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr953 Debug: 1721 5493 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9 Debug: 1722 5498 riscv-013.c:1532 register_write_direct(): [esp32c6] csr953 <- 0x0 Debug: 1723 5498 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr9 (cacheable=false, valid=false, dirty=false) Debug: 1724 5498 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr10 Debug: 1725 5498 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr10 (valid=0). Debug: 1726 5498 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1727 5498 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr954 Debug: 1728 5498 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr954 Debug: 1729 5502 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba Debug: 1730 5506 riscv-013.c:1532 register_write_direct(): [esp32c6] csr954 <- 0x0 Debug: 1731 5506 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr10 (cacheable=false, valid=false, dirty=false) Debug: 1732 5506 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr11 Debug: 1733 5506 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr11 (valid=0). Debug: 1734 5506 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1735 5506 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr955 Debug: 1736 5506 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr955 Debug: 1737 5510 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb Debug: 1738 5513 riscv-013.c:1532 register_write_direct(): [esp32c6] csr955 <- 0x0 Debug: 1739 5513 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr11 (cacheable=false, valid=false, dirty=false) Debug: 1740 5513 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr12 Debug: 1741 5513 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr12 (valid=0). Debug: 1742 5513 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1743 5513 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr956 Debug: 1744 5513 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr956 Debug: 1745 5516 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc [OpenOCD] Debug: 1746 5520 riscv-013.c:1532 register_write_direct(): [esp32c6] csr956 <- 0x0 Debug: 1747 5520 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr12 (cacheable=false, valid=false, dirty=false) Debug: 1748 5520 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr13 Debug: 1749 5520 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr13 (valid=0). Debug: 1750 5520 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1751 5520 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr957 Debug: 1752 5520 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr957 Debug: 1753 5523 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd Debug: 1754 5530 riscv-013.c:1532 register_write_direct(): [esp32c6] csr957 <- 0x0 Debug: 1755 5530 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr13 (cacheable=false, valid=false, dirty=false) Debug: 1756 5530 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr14 Debug: 1757 5530 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr14 (valid=0). Debug: 1758 5530 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1759 5530 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr958 Debug: 1760 5530 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr958 Debug: 1761 5534 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be Debug: 1762 5539 riscv-013.c:1532 register_write_direct(): [esp32c6] csr958 <- 0x0 Debug: 1763 5539 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr14 (cacheable=false, valid=false, dirty=false) Debug: 1764 5539 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr15 Debug: 1765 5539 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr15 (valid=0). Debug: 1766 5539 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1767 5539 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr959 Debug: 1768 5539 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr959 Debug: 1769 5542 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf Debug: 1770 5547 riscv-013.c:1532 register_write_direct(): [esp32c6] csr959 <- 0x0 Debug: 1771 5547 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr15 (cacheable=false, valid=false, dirty=false) Debug: 1772 5547 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tselect Debug: 1773 5547 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tselect (valid=0). Debug: 1774 5547 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1775 5547 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tselect Debug: 1776 5547 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tselect Debug: 1777 5551 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 1778 5556 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x0 Debug: 1779 5556 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tselect (cacheable=false, valid=false, dirty=false) Debug: 1780 5556 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tdata1 Debug: 1781 5556 riscv.c:5274 register_set(): [esp32c6] Write 0x23e00000 to tdata1 (valid=0). Debug: 1782 5556 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 1783 5556 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 1784 5556 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 1785 5556 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 1786 5562 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x0 Debug: 1787 5562 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x0 Debug: 1788 5562 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1789 5562 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tselect Debug: 1790 5562 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tselect Debug: 1791 5564 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 1792 5567 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x0 Debug: 1793 5567 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tselect (cacheable=false, valid=false, dirty=false) Debug: 1794 5567 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 1795 5567 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 1796 5567 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 1797 5567 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 [OpenOCD] Debug: 1798 5575 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x0 Debug: 1799 5575 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x0 Debug: 1800 5575 riscv.c:4812 riscv_get_register(): [esp32c6] Register tinfo does not exist. Debug: 1801 5575 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata1 from target Debug: 1802 5575 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata1 Debug: 1803 5575 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata1 Debug: 1804 5575 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 1805 5584 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata1 = 0x23e00000 Debug: 1806 5584 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata1: 0x23e00000 Debug: 1807 5584 riscv.c:5030 riscv_enumerate_triggers(): [esp32c6] Trigger 0: supported types (mask) = 0x00000004 Debug: 1808 5584 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x1 (cacheable=false, valid=false, dirty=false) Debug: 1809 5584 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x1 to register tselect Debug: 1810 5584 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x1 to tselect Debug: 1811 5590 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 1812 5596 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x1 Debug: 1813 5596 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x1 to tselect (cacheable=false, valid=false, dirty=false) Debug: 1814 5596 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 1815 5596 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 1816 5596 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 1817 5596 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 1818 5611 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x1 Debug: 1819 5611 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x1 Debug: 1820 5611 riscv.c:4812 riscv_get_register(): [esp32c6] Register tinfo does not exist. Debug: 1821 5611 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata1 from target Debug: 1822 5611 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata1 Debug: 1823 5611 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata1 Debug: 1824 5611 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 1825 5625 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata1 = 0x23e00000 Debug: 1826 5626 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata1: 0x23e00000 Debug: 1827 5626 riscv.c:5030 riscv_enumerate_triggers(): [esp32c6] Trigger 1: supported types (mask) = 0x00000004 Debug: 1828 5626 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x2 (cacheable=false, valid=false, dirty=false) Debug: 1829 5626 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x2 to register tselect Debug: 1830 5626 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x2 to tselect Debug: 1831 5637 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 [OpenOCD] Debug: 1832 5694 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x2 Debug: 1833 5694 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x2 to tselect (cacheable=false, valid=false, dirty=false) Debug: 1834 5694 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 1835 5694 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 1836 5694 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 1837 5694 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 1838 5711 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x2 Debug: 1839 5711 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x2 Debug: 1840 5711 riscv.c:4812 riscv_get_register(): [esp32c6] Register tinfo does not exist. Debug: 1841 5711 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata1 from target Debug: 1842 5711 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata1 Debug: 1843 5711 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata1 Debug: 1844 5711 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 1845 5727 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata1 = 0x23e00000 Debug: 1846 5727 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata1: 0x23e00000 Debug: 1847 5727 riscv.c:5030 riscv_enumerate_triggers(): [esp32c6] Trigger 2: supported types (mask) = 0x00000004 Debug: 1848 5727 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 1849 5727 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register tselect Debug: 1850 5727 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to tselect Debug: 1851 5731 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 1852 5756 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x3 Debug: 1853 5756 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to tselect (cacheable=false, valid=false, dirty=false) Debug: 1854 5756 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 1855 5756 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 1856 5756 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 1857 5756 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 1858 5764 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x3 Debug: 1859 5764 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x3 Debug: 1860 5764 riscv.c:4812 riscv_get_register(): [esp32c6] Register tinfo does not exist. Debug: 1861 5764 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata1 from target Debug: 1862 5764 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata1 Debug: 1863 5764 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata1 Debug: 1864 5764 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 1865 5773 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata1 = 0x23e00000 Debug: 1866 5773 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata1: 0x23e00000 Debug: 1867 5773 riscv.c:5030 riscv_enumerate_triggers(): [esp32c6] Trigger 3: supported types (mask) = 0x00000004 Debug: 1868 5773 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x4 (cacheable=false, valid=false, dirty=false) Debug: 1869 5773 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4 to register tselect Debug: 1870 5773 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4 to tselect Debug: 1871 5775 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 [OpenOCD] Debug: 1872 5781 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x4 Debug: 1873 5781 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4 to tselect (cacheable=false, valid=false, dirty=false) Debug: 1874 5781 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 1875 5781 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 1876 5781 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 1877 5781 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 1878 5791 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x3 Debug: 1879 5791 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x3 Debug: 1880 5791 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1881 5791 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tselect Debug: 1882 5791 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tselect Debug: 1883 5796 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 1884 5804 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x0 Debug: 1885 5804 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tselect (cacheable=false, valid=false, dirty=false) Info : 1886 5804 riscv.c:5035 riscv_enumerate_triggers(): [esp32c6] Found 4 triggers. Debug: 1887 5804 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tdata1 <- 0x23e00000 (cacheable=false, valid=false, dirty=false) Debug: 1888 5804 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x23e00000 to register tdata1 Debug: 1889 5804 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x23e00000 to tdata1 Debug: 1890 5808 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1 Debug: 1891 5814 riscv-013.c:1532 register_write_direct(): [esp32c6] tdata1 <- 0x23e00000 Debug: 1892 5814 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x23e00000 to tdata1 (cacheable=false, valid=false, dirty=false) Debug: 1893 5814 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tdata2 Debug: 1894 5814 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tdata2 (valid=0). Debug: 1895 5814 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tdata2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1896 5814 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tdata2 Debug: 1897 5814 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tdata2 Debug: 1898 5822 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2 Debug: 1899 5826 riscv-013.c:1532 register_write_direct(): [esp32c6] tdata2 <- 0x0 Debug: 1900 5826 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tdata2 (cacheable=false, valid=false, dirty=false) Debug: 1901 5826 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tcontrol Debug: 1902 5826 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tcontrol (valid=0). Debug: 1903 5826 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tcontrol <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1904 5826 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr1957 Debug: 1905 5826 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr1957 Debug: 1906 5829 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5 Debug: 1907 5832 riscv-013.c:1532 register_write_direct(): [esp32c6] csr1957 <- 0x0 Debug: 1908 5832 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tcontrol (cacheable=false, valid=false, dirty=false) Debug: 1909 5832 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dcsr Debug: 1910 5832 riscv.c:5274 register_set(): [esp32c6] Write 0x400090c3 to dcsr (valid=0). Debug: 1911 5832 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dcsr <- 0x400090c3 (cacheable=false, valid=false, dirty=false) Debug: 1912 5832 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x400090c3 to register dcsr Debug: 1913 5832 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x400090c3 to dcsr Debug: 1914 5836 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 1915 5839 riscv-013.c:1532 register_write_direct(): [esp32c6] dcsr <- 0x400090c3 Debug: 1916 5839 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x400090c3 to dcsr (cacheable=false, valid=false, dirty=false) Debug: 1917 5839 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dpc Debug: 1918 5839 riscv.c:5274 register_set(): [esp32c6] Write 0x40000000 to dpc (valid=0). Debug: 1919 5839 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40000000 to dpc (cacheable=true, valid=true, dirty=true) Debug: 1920 5839 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dscratch0 Debug: 1921 5839 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to dscratch0 (valid=0). Debug: 1922 5839 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dscratch0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1923 5839 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register dscratch0 Debug: 1924 5839 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to dscratch0 Debug: 1925 5841 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2 Debug: 1926 5845 riscv-013.c:1532 register_write_direct(): [esp32c6] dscratch0 <- 0x0 Debug: 1927 5845 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to dscratch0 (cacheable=false, valid=false, dirty=false) Debug: 1928 5845 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dscratch1 Debug: 1929 5845 riscv.c:5274 register_set(): [esp32c6] Write 0x20000000 to dscratch1 (valid=0). Debug: 1930 5845 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dscratch1 <- 0x20000000 (cacheable=false, valid=false, dirty=false) Debug: 1931 5845 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x20000000 to register csr1971 Debug: 1932 5845 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x20000000 to csr1971 Debug: 1933 5846 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3 Debug: 1934 5850 riscv-013.c:1532 register_write_direct(): [esp32c6] csr1971 <- 0x20000000 Debug: 1935 5850 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x20000000 to dscratch1 (cacheable=false, valid=false, dirty=false) Debug: 1936 5850 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpcer Debug: 1937 5850 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_mpcer (valid=0). Debug: 1938 5850 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpcer <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1939 5850 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2016 Debug: 1940 5850 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2016 Debug: 1941 5854 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e0 Debug: 1942 5858 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2016 <- 0x0 Debug: 1943 5858 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_mpcer (cacheable=false, valid=false, dirty=false) Debug: 1944 5858 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpcmr Debug: 1945 5858 riscv.c:5274 register_set(): [esp32c6] Write 0x00000003 to csr_mpcmr (valid=0). Debug: 1946 5858 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpcmr <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 1947 5858 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register csr2017 Debug: 1948 5858 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to csr2017 Debug: 1949 5861 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e1 Debug: 1950 5864 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2017 <- 0x3 Debug: 1951 5864 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to csr_mpcmr (cacheable=false, valid=false, dirty=false) Debug: 1952 5864 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpccr Debug: 1953 5864 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_mpccr (valid=0). Debug: 1954 5864 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpccr <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1955 5864 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2018 Debug: 1956 5864 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2018 Debug: 1957 5867 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e2 Debug: 1958 5871 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2018 <- 0x0 Debug: 1959 5871 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_mpccr (cacheable=false, valid=false, dirty=false) Debug: 1960 5871 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_oen Debug: 1961 5871 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_oen (valid=0). Debug: 1962 5871 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_oen <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1963 5871 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2051 Debug: 1964 5871 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2051 Debug: 1965 5874 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230803; access register, size=32, postexec=0, transfer=1, write=1, regno=0x803 [OpenOCD] Debug: 1966 5878 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2051 <- 0x0 Debug: 1967 5878 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_oen (cacheable=false, valid=false, dirty=false) Debug: 1968 5878 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_in Debug: 1969 5878 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_in (valid=0). Debug: 1970 5878 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_in <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1971 5878 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2052 Debug: 1972 5878 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2052 Debug: 1973 5882 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230804; access register, size=32, postexec=0, transfer=1, write=1, regno=0x804 Debug: 1974 5895 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2052 <- 0x0 Debug: 1975 5895 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_in (cacheable=false, valid=false, dirty=false) Debug: 1976 5895 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_out Debug: 1977 5895 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_out (valid=0). Debug: 1978 5895 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_out <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1979 5895 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2053 Debug: 1980 5895 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2053 Debug: 1981 5937 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230805; access register, size=32, postexec=0, transfer=1, write=1, regno=0x805 Debug: 1982 5943 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2053 <- 0x0 Debug: 1983 5943 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_out (cacheable=false, valid=false, dirty=false) Debug: 1984 5943 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg0 Debug: 1985 5943 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg0 (valid=0). Debug: 1986 5943 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1987 5943 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3008 Debug: 1988 5943 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3008 Debug: 1989 5946 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc0; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc0 Debug: 1990 5952 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3008 <- 0x0 Debug: 1991 5952 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg0 (cacheable=false, valid=false, dirty=false) Debug: 1992 5952 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg1 Debug: 1993 5952 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg1 (valid=0). Debug: 1994 5952 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 1995 5952 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3009 Debug: 1996 5952 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3009 Debug: 1997 5973 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc1; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc1 [OpenOCD] Debug: 1998 5979 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3009 <- 0x0 Debug: 1999 5979 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg1 (cacheable=false, valid=false, dirty=false) Debug: 2000 5979 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg2 Debug: 2001 5979 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg2 (valid=0). Debug: 2002 5979 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2003 5979 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3010 Debug: 2004 5979 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3010 Debug: 2005 5987 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc2; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc2 Debug: 2006 5998 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3010 <- 0x0 Debug: 2007 5998 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg2 (cacheable=false, valid=false, dirty=false) Debug: 2008 5998 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg3 Debug: 2009 5998 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg3 (valid=0). Debug: 2010 5998 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2011 5998 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3011 Debug: 2012 5998 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3011 Debug: 2013 6020 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc3; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc3 Debug: 2014 6037 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3011 <- 0x0 Debug: 2015 6037 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg3 (cacheable=false, valid=false, dirty=false) Debug: 2016 6037 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg4 Debug: 2017 6037 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg4 (valid=0). Debug: 2018 6037 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2019 6037 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3012 Debug: 2020 6037 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3012 Debug: 2021 6042 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc4; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc4 Debug: 2022 6047 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3012 <- 0x0 Debug: 2023 6047 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg4 (cacheable=false, valid=false, dirty=false) Debug: 2024 6047 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg5 Debug: 2025 6047 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg5 (valid=0). Debug: 2026 6047 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2027 6047 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3013 Debug: 2028 6047 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3013 Debug: 2029 6050 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc5; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc5 Debug: 2030 6054 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3013 <- 0x0 Debug: 2031 6054 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg5 (cacheable=false, valid=false, dirty=false) Debug: 2032 6054 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg6 Debug: 2033 6054 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg6 (valid=0). Debug: 2034 6054 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2035 6054 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3014 Debug: 2036 6054 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3014 Debug: 2037 6056 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc6; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc6 Debug: 2038 6061 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3014 <- 0x0 Debug: 2039 6061 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg6 (cacheable=false, valid=false, dirty=false) Debug: 2040 6061 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg7 Debug: 2041 6061 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg7 (valid=0). Debug: 2042 6061 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2043 6061 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3015 Debug: 2044 6061 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3015 [OpenOCD] Debug: 2045 6064 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc7; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc7 Debug: 2046 6068 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3015 <- 0x0 Debug: 2047 6068 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg7 (cacheable=false, valid=false, dirty=false) Debug: 2048 6068 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg8 Debug: 2049 6068 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg8 (valid=0). Debug: 2050 6068 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2051 6068 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3016 Debug: 2052 6068 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3016 Debug: 2053 6072 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc8; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc8 Debug: 2054 6079 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3016 <- 0x0 Debug: 2055 6079 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg8 (cacheable=false, valid=false, dirty=false) Debug: 2056 6079 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg9 Debug: 2057 6079 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg9 (valid=0). Debug: 2058 6079 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2059 6079 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3017 Debug: 2060 6079 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3017 Debug: 2061 6085 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc9; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc9 Debug: 2062 6093 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3017 <- 0x0 Debug: 2063 6093 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg9 (cacheable=false, valid=false, dirty=false) Debug: 2064 6093 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg10 Debug: 2065 6093 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg10 (valid=0). Debug: 2066 6093 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2067 6093 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3018 Debug: 2068 6093 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3018 Debug: 2069 6098 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bca; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbca Debug: 2070 6107 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3018 <- 0x0 Debug: 2071 6107 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg10 (cacheable=false, valid=false, dirty=false) Debug: 2072 6107 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg11 Debug: 2073 6107 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg11 (valid=0). Debug: 2074 6107 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2075 6107 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3019 Debug: 2076 6107 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3019 Debug: 2077 6109 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcb; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcb Debug: 2078 6113 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3019 <- 0x0 Debug: 2079 6113 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg11 (cacheable=false, valid=false, dirty=false) Debug: 2080 6113 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg12 Debug: 2081 6113 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg12 (valid=0). Debug: 2082 6113 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2083 6113 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3020 Debug: 2084 6113 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3020 Debug: 2085 6115 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcc; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcc Debug: 2086 6119 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3020 <- 0x0 Debug: 2087 6119 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg12 (cacheable=false, valid=false, dirty=false) Debug: 2088 6119 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg13 Debug: 2089 6119 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg13 (valid=0). Debug: 2090 6119 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2091 6119 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3021 Debug: 2092 6119 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3021 Debug: 2093 6121 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcd; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcd Debug: 2094 6124 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3021 <- 0x0 Debug: 2095 6124 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg13 (cacheable=false, valid=false, dirty=false) Debug: 2096 6124 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg14 Debug: 2097 6124 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg14 (valid=0). Debug: 2098 6124 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2099 6124 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3022 Debug: 2100 6124 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3022 [OpenOCD] Debug: 2101 6127 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bce; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbce Debug: 2102 6131 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3022 <- 0x0 Debug: 2103 6131 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg14 (cacheable=false, valid=false, dirty=false) Debug: 2104 6131 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg15 Debug: 2105 6131 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg15 (valid=0). Debug: 2106 6131 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2107 6131 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3023 Debug: 2108 6131 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3023 Debug: 2109 6146 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcf; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcf Debug: 2110 6173 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3023 <- 0x0 Debug: 2111 6173 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg15 (cacheable=false, valid=false, dirty=false) Debug: 2112 6173 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr0 Debug: 2113 6173 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr0 (valid=0). Debug: 2114 6173 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2115 6173 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3024 Debug: 2116 6173 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3024 Debug: 2117 6190 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd0; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd0 Debug: 2118 6195 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3024 <- 0x0 Debug: 2119 6195 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr0 (cacheable=false, valid=false, dirty=false) Debug: 2120 6195 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr1 Debug: 2121 6195 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr1 (valid=0). Debug: 2122 6195 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2123 6195 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3025 Debug: 2124 6195 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3025 Debug: 2125 6200 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd1; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd1 Debug: 2126 6212 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3025 <- 0x0 Debug: 2127 6212 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr1 (cacheable=false, valid=false, dirty=false) Debug: 2128 6212 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr2 Debug: 2129 6212 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr2 (valid=0). Debug: 2130 6212 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2131 6212 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3026 Debug: 2132 6212 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3026 Debug: 2133 6216 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd2; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd2 Debug: 2134 6222 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3026 <- 0x0 Debug: 2135 6222 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr2 (cacheable=false, valid=false, dirty=false) Debug: 2136 6222 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr3 Debug: 2137 6222 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr3 (valid=0). Debug: 2138 6222 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2139 6222 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3027 Debug: 2140 6222 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3027 Debug: 2141 6225 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd3; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd3 Debug: 2142 6231 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3027 <- 0x0 Debug: 2143 6231 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr3 (cacheable=false, valid=false, dirty=false) Debug: 2144 6231 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr4 Debug: 2145 6231 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr4 (valid=0). Debug: 2146 6231 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2147 6231 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3028 Debug: 2148 6231 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3028 [OpenOCD] Debug: 2149 6235 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd4; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd4 Debug: 2150 6239 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3028 <- 0x0 Debug: 2151 6239 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr4 (cacheable=false, valid=false, dirty=false) Debug: 2152 6239 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr5 Debug: 2153 6239 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr5 (valid=0). Debug: 2154 6239 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2155 6239 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3029 Debug: 2156 6239 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3029 Debug: 2157 6243 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd5; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd5 Debug: 2158 6248 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3029 <- 0x0 Debug: 2159 6248 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr5 (cacheable=false, valid=false, dirty=false) Debug: 2160 6248 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr6 Debug: 2161 6248 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr6 (valid=0). Debug: 2162 6248 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2163 6248 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3030 Debug: 2164 6248 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3030 Debug: 2165 6255 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd6; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd6 Debug: 2166 6262 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3030 <- 0x0 Debug: 2167 6262 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr6 (cacheable=false, valid=false, dirty=false) Debug: 2168 6262 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr7 Debug: 2169 6262 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr7 (valid=0). Debug: 2170 6262 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2171 6262 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3031 Debug: 2172 6262 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3031 Debug: 2173 6266 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd7; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd7 Debug: 2174 6272 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3031 <- 0x0 Debug: 2175 6272 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr7 (cacheable=false, valid=false, dirty=false) Debug: 2176 6272 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr8 Debug: 2177 6272 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr8 (valid=0). Debug: 2178 6272 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2179 6272 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3032 Debug: 2180 6272 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3032 Debug: 2181 6275 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd8; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd8 Debug: 2182 6282 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3032 <- 0x0 Debug: 2183 6282 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr8 (cacheable=false, valid=false, dirty=false) Debug: 2184 6282 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr9 Debug: 2185 6282 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr9 (valid=0). Debug: 2186 6282 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2187 6282 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3033 Debug: 2188 6282 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3033 Debug: 2189 6285 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd9; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd9 Debug: 2190 6288 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3033 <- 0x0 Debug: 2191 6288 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr9 (cacheable=false, valid=false, dirty=false) Debug: 2192 6288 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr10 Debug: 2193 6288 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr10 (valid=0). Debug: 2194 6288 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2195 6288 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3034 Debug: 2196 6288 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3034 [OpenOCD] Debug: 2197 6291 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bda; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbda Debug: 2198 6295 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3034 <- 0x0 Debug: 2199 6295 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr10 (cacheable=false, valid=false, dirty=false) Debug: 2200 6295 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr11 Debug: 2201 6295 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr11 (valid=0). Debug: 2202 6295 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2203 6295 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3035 Debug: 2204 6295 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3035 Debug: 2205 6297 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdb; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdb Debug: 2206 6303 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3035 <- 0x0 Debug: 2207 6303 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr11 (cacheable=false, valid=false, dirty=false) Debug: 2208 6303 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr12 Debug: 2209 6303 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr12 (valid=0). Debug: 2210 6303 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2211 6303 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3036 Debug: 2212 6303 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3036 Debug: 2213 6307 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdc; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdc Debug: 2214 6313 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3036 <- 0x0 Debug: 2215 6313 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr12 (cacheable=false, valid=false, dirty=false) Debug: 2216 6313 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr13 Debug: 2217 6313 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr13 (valid=0). Debug: 2218 6313 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2219 6313 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3037 Debug: 2220 6313 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3037 Debug: 2221 6318 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdd; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdd Debug: 2222 6323 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3037 <- 0x0 Debug: 2223 6323 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr13 (cacheable=false, valid=false, dirty=false) Debug: 2224 6323 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr14 Debug: 2225 6323 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr14 (valid=0). Debug: 2226 6323 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2227 6323 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3038 Debug: 2228 6323 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3038 Debug: 2229 6326 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bde; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbde Debug: 2230 6332 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3038 <- 0x0 Debug: 2231 6332 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr14 (cacheable=false, valid=false, dirty=false) Debug: 2232 6332 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr15 Debug: 2233 6332 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr15 (valid=0). Debug: 2234 6332 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 2235 6332 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3039 Debug: 2236 6332 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3039 Debug: 2237 6336 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdf; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdf Debug: 2238 6340 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3039 <- 0x0 Debug: 2239 6340 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr15 (cacheable=false, valid=false, dirty=false) Debug: 2240 6340 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore hpmcounter16 Debug: 2241 6340 riscv.c:5274 register_set(): [esp32c6] Write 0x00000003 to hpmcounter16 (valid=0). Debug: 2242 6340 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: hpmcounter16 <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 2243 6340 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register csr3088 Debug: 2244 6340 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to csr3088 Debug: 2245 6342 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10 Debug: 2246 6347 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3088 <- 0x3 Debug: 2247 6347 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to hpmcounter16 (cacheable=false, valid=false, dirty=false) Debug: 2248 6347 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore priv Debug: 2249 6347 riscv.c:5274 register_set(): [esp32c6] Write 0x03 to priv (valid=0). Debug: 2250 6347 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: priv <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 2251 6347 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register priv Debug: 2252 6347 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 2253 6347 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 [OpenOCD] Debug: 2254 6354 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 2255 6354 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x400090c3 to dcsr Debug: 2256 6357 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 2257 6361 riscv-013.c:1532 register_write_direct(): [esp32c6] dcsr <- 0x400090c3 Debug: 2258 6361 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to priv (cacheable=false, valid=false, dirty=false) Debug: 2259 6361 riscv.c:1575 riscv_flush_registers(): [esp32c6] dpc is dirty; write back 0x40000000 Debug: 2260 6361 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40000000 to register dpc Debug: 2261 6361 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40000000 to dpc Debug: 2262 6364 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 2263 6419 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40000000 Debug: 2264 6419 riscv.c:1575 riscv_flush_registers(): [esp32c6] t6 is dirty; write back 0x0 Debug: 2265 6419 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t6 Debug: 2266 6419 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t6 Debug: 2267 6422 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f Debug: 2268 6428 riscv-013.c:1532 register_write_direct(): [esp32c6] t6 <- 0x0 Debug: 2269 6428 riscv.c:1575 riscv_flush_registers(): [esp32c6] t5 is dirty; write back 0x0 Debug: 2270 6428 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t5 Debug: 2271 6428 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t5 Debug: 2272 6431 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e [OpenOCD] Debug: 2273 6439 riscv-013.c:1532 register_write_direct(): [esp32c6] t5 <- 0x0 Debug: 2274 6439 riscv.c:1575 riscv_flush_registers(): [esp32c6] t4 is dirty; write back 0x0 Debug: 2275 6439 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t4 Debug: 2276 6439 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t4 Debug: 2277 6441 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d Debug: 2278 6451 riscv-013.c:1532 register_write_direct(): [esp32c6] t4 <- 0x0 Debug: 2279 6451 riscv.c:1575 riscv_flush_registers(): [esp32c6] t3 is dirty; write back 0x0 Debug: 2280 6451 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t3 Debug: 2281 6451 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t3 Debug: 2282 6462 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c Debug: 2283 6472 riscv-013.c:1532 register_write_direct(): [esp32c6] t3 <- 0x0 Debug: 2284 6473 riscv.c:1575 riscv_flush_registers(): [esp32c6] s11 is dirty; write back 0x0 Debug: 2285 6473 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s11 Debug: 2286 6473 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s11 Debug: 2287 6482 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b Debug: 2288 6491 riscv-013.c:1532 register_write_direct(): [esp32c6] s11 <- 0x0 Debug: 2289 6491 riscv.c:1575 riscv_flush_registers(): [esp32c6] s10 is dirty; write back 0x0 Debug: 2290 6491 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s10 Debug: 2291 6491 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s10 Debug: 2292 6494 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a Debug: 2293 6497 riscv-013.c:1532 register_write_direct(): [esp32c6] s10 <- 0x0 Debug: 2294 6497 riscv.c:1575 riscv_flush_registers(): [esp32c6] s9 is dirty; write back 0x0 Debug: 2295 6497 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s9 Debug: 2296 6497 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s9 Debug: 2297 6502 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019 Debug: 2298 6506 riscv-013.c:1532 register_write_direct(): [esp32c6] s9 <- 0x0 Debug: 2299 6506 riscv.c:1575 riscv_flush_registers(): [esp32c6] s8 is dirty; write back 0x0 Debug: 2300 6506 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s8 Debug: 2301 6506 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s8 Debug: 2302 6509 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018 Debug: 2303 6513 riscv-013.c:1532 register_write_direct(): [esp32c6] s8 <- 0x0 Debug: 2304 6513 riscv.c:1575 riscv_flush_registers(): [esp32c6] s7 is dirty; write back 0x0 Debug: 2305 6513 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s7 Debug: 2306 6513 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s7 [OpenOCD] Debug: 2307 6515 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017 Debug: 2308 6521 riscv-013.c:1532 register_write_direct(): [esp32c6] s7 <- 0x0 Debug: 2309 6521 riscv.c:1575 riscv_flush_registers(): [esp32c6] s6 is dirty; write back 0x0 Debug: 2310 6521 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s6 Debug: 2311 6521 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s6 Debug: 2312 6525 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016 Debug: 2313 6530 riscv-013.c:1532 register_write_direct(): [esp32c6] s6 <- 0x0 Debug: 2314 6530 riscv.c:1575 riscv_flush_registers(): [esp32c6] s5 is dirty; write back 0x0 Debug: 2315 6530 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s5 Debug: 2316 6530 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s5 Debug: 2317 6534 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015 Debug: 2318 6539 riscv-013.c:1532 register_write_direct(): [esp32c6] s5 <- 0x0 Debug: 2319 6540 riscv.c:1575 riscv_flush_registers(): [esp32c6] s4 is dirty; write back 0x0 Debug: 2320 6540 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s4 Debug: 2321 6540 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s4 Debug: 2322 6543 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014 Debug: 2323 6549 riscv-013.c:1532 register_write_direct(): [esp32c6] s4 <- 0x0 Debug: 2324 6549 riscv.c:1575 riscv_flush_registers(): [esp32c6] s3 is dirty; write back 0x0 Debug: 2325 6549 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s3 Debug: 2326 6549 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s3 Debug: 2327 6552 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013 Debug: 2328 6556 riscv-013.c:1532 register_write_direct(): [esp32c6] s3 <- 0x0 Debug: 2329 6556 riscv.c:1575 riscv_flush_registers(): [esp32c6] s2 is dirty; write back 0x0 Debug: 2330 6556 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s2 Debug: 2331 6556 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s2 Debug: 2332 6558 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012 Debug: 2333 6562 riscv-013.c:1532 register_write_direct(): [esp32c6] s2 <- 0x0 Debug: 2334 6562 riscv.c:1575 riscv_flush_registers(): [esp32c6] a7 is dirty; write back 0x80000000 Debug: 2335 6562 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x80000000 to register a7 Debug: 2336 6562 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x80000000 to a7 Debug: 2337 6564 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 [OpenOCD] Debug: 2338 6569 riscv-013.c:1532 register_write_direct(): [esp32c6] a7 <- 0x80000000 Debug: 2339 6569 riscv.c:1575 riscv_flush_registers(): [esp32c6] a6 is dirty; write back 0x8 Debug: 2340 6569 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x8 to register a6 Debug: 2341 6569 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x8 to a6 Debug: 2342 6572 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010 Debug: 2343 6577 riscv-013.c:1532 register_write_direct(): [esp32c6] a6 <- 0x8 Debug: 2344 6577 riscv.c:1575 riscv_flush_registers(): [esp32c6] a5 is dirty; write back 0x4 Debug: 2345 6577 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4 to register a5 Debug: 2346 6577 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4 to a5 Debug: 2347 6581 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f Debug: 2348 6586 riscv-013.c:1532 register_write_direct(): [esp32c6] a5 <- 0x4 Debug: 2349 6586 riscv.c:1575 riscv_flush_registers(): [esp32c6] a4 is dirty; write back 0x408021e0 Debug: 2350 6586 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x408021e0 to register a4 Debug: 2351 6586 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x408021e0 to a4 Debug: 2352 6590 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e Debug: 2353 6596 riscv-013.c:1532 register_write_direct(): [esp32c6] a4 <- 0x408021e0 Debug: 2354 6596 riscv.c:1575 riscv_flush_registers(): [esp32c6] a3 is dirty; write back 0x10000 Debug: 2355 6596 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x10000 to register a3 Debug: 2356 6596 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x10000 to a3 Debug: 2357 6600 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d Debug: 2358 6629 riscv-013.c:1532 register_write_direct(): [esp32c6] a3 <- 0x10000 Debug: 2359 6629 riscv.c:1575 riscv_flush_registers(): [esp32c6] a2 is dirty; write back 0x10 Debug: 2360 6629 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x10 to register a2 Debug: 2361 6629 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x10 to a2 [OpenOCD] Debug: 2362 6658 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 2363 6665 riscv-013.c:1532 register_write_direct(): [esp32c6] a2 <- 0x10 Debug: 2364 6665 riscv.c:1575 riscv_flush_registers(): [esp32c6] a1 is dirty; write back 0x60002000 Debug: 2365 6665 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x60002000 to register a1 Debug: 2366 6665 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x60002000 to a1 Debug: 2367 6672 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 2368 6693 riscv-013.c:1532 register_write_direct(): [esp32c6] a1 <- 0x60002000 Debug: 2369 6693 riscv.c:1575 riscv_flush_registers(): [esp32c6] a0 is dirty; write back 0x20000000 Debug: 2370 6693 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x20000000 to register a0 Debug: 2371 6693 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x20000000 to a0 Debug: 2372 6697 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 2373 6705 riscv-013.c:1532 register_write_direct(): [esp32c6] a0 <- 0x20000000 Debug: 2374 6705 riscv.c:1575 riscv_flush_registers(): [esp32c6] s1 is dirty; write back 0x0 Debug: 2375 6705 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s1 Debug: 2376 6705 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s1 Debug: 2377 6711 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 2378 6717 riscv-013.c:1532 register_write_direct(): [esp32c6] s1 <- 0x0 Debug: 2379 6717 riscv.c:1575 riscv_flush_registers(): [esp32c6] fp is dirty; write back 0x0 Debug: 2380 6717 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s0 Debug: 2381 6717 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s0 Debug: 2382 6720 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 2383 6723 riscv-013.c:1532 register_write_direct(): [esp32c6] s0 <- 0x0 Debug: 2384 6723 riscv.c:1575 riscv_flush_registers(): [esp32c6] t2 is dirty; write back 0x0 Debug: 2385 6723 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t2 Debug: 2386 6723 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t2 Debug: 2387 6726 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007 [OpenOCD] Debug: 2388 6731 riscv-013.c:1532 register_write_direct(): [esp32c6] t2 <- 0x0 Debug: 2389 6731 riscv.c:1575 riscv_flush_registers(): [esp32c6] t1 is dirty; write back 0xffffffe0 Debug: 2390 6731 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0xffffffe0 to register t1 Debug: 2391 6731 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0xffffffe0 to t1 Debug: 2392 6735 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006 Debug: 2393 6739 riscv-013.c:1532 register_write_direct(): [esp32c6] t1 <- 0xffffffe0 Debug: 2394 6739 riscv.c:1575 riscv_flush_registers(): [esp32c6] t0 is dirty; write back 0x40027bd4 Debug: 2395 6739 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40027bd4 to register t0 Debug: 2396 6739 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40027bd4 to t0 Debug: 2397 6743 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005 Debug: 2398 6753 riscv-013.c:1532 register_write_direct(): [esp32c6] t0 <- 0x40027bd4 Debug: 2399 6753 riscv.c:1575 riscv_flush_registers(): [esp32c6] tp is dirty; write back 0x0 Debug: 2400 6753 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tp Debug: 2401 6753 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tp Debug: 2402 6756 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004 Debug: 2403 6761 riscv-013.c:1532 register_write_direct(): [esp32c6] tp <- 0x0 Debug: 2404 6761 riscv.c:1575 riscv_flush_registers(): [esp32c6] gp is dirty; write back 0x0 Debug: 2405 6761 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register gp Debug: 2406 6761 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to gp Debug: 2407 6764 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003 Debug: 2408 6769 riscv-013.c:1532 register_write_direct(): [esp32c6] gp <- 0x0 Debug: 2409 6769 riscv.c:1575 riscv_flush_registers(): [esp32c6] sp is dirty; write back 0x40804780 Debug: 2410 6769 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40804780 to register sp Debug: 2411 6769 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40804780 to sp Debug: 2412 6772 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 2413 6775 riscv-013.c:1532 register_write_direct(): [esp32c6] sp <- 0x40804780 Debug: 2414 6775 riscv.c:1575 riscv_flush_registers(): [esp32c6] ra is dirty; write back 0x40801456 Debug: 2415 6775 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40801456 to register ra Debug: 2416 6775 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40801456 to ra Debug: 2417 6777 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001 Debug: 2418 6781 riscv-013.c:1532 register_write_direct(): [esp32c6] ra <- 0x40801456 Debug: 2419 6781 esp_algorithm.c:130 algorithm_run_image(): Got algorithm RC 0x0 Debug: 2420 6786 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804794 Debug: 2421 6790 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2422 6790 target.c:2138 target_free_working_area_restore(): freed 28 bytes of working area at address 0x40804794 Debug: 2423 6790 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 2424 6790 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 2425 6790 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 2426 6790 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 2427 6790 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 2428 6790 target.c:1938 print_wa_layout(): 0x40804794-0x40823fff (129132 bytes) Debug: 2429 6790 esp.c:259 esp_common_assist_debug_monitor_restore(): [esp32c6] value 0x00000000 addr 0x600c2000 Debug: 2430 6790 target.c:2686 target_write_u32(): address: 0x600c2000, value: 0x00000000 Debug: 2431 6794 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600c2000 Debug: 2432 6798 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2433 6798 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 2434 6807 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800000 [OpenOCD] Debug: 2435 6868 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800200 Debug: 2436 6891 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800400 Debug: 2437 6908 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800600 Debug: 2438 6918 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800800 [OpenOCD] Debug: 2439 6929 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800a00 Debug: 2440 6939 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800c00 Debug: 2441 6949 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800e00 Debug: 2442 6959 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801000 Debug: 2443 6969 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801200 Debug: 2444 6976 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801400 Debug: 2445 6980 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. [OpenOCD] Debug: 2446 6986 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801454 Debug: 2447 6989 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2448 6995 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804000 Debug: 2449 7003 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804200 Debug: 2450 7008 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2451 7014 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804280 Debug: 2452 7067 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804480 [OpenOCD] Debug: 2453 7076 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804680 Debug: 2454 7082 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2455 7082 target.c:1938 print_wa_layout(): 0x40800000-0x40823fff (147456 bytes) Info : 2456 7082 esp_flash.c:412 esp_algo_flash_get_mappings(): Flash mapping 0: 0x20020 -> 0x42020020, 55 KB Info : 2457 7082 esp_flash.c:412 esp_algo_flash_get_mappings(): Flash mapping 1: 0x30020 -> 0x42000020, 109 KB Debug: 2458 7082 esp_flash.c:245 esp_algo_flasher_algorithm_init(): base=00000000 set=0 Debug: 2459 7082 esp_algorithm.c:290 algorithm_load_func_image(): stub: base 0x0, start 0x4080110c, 2 sections Debug: 2460 7082 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 5202, flags 1 Debug: 2461 7082 target.c:2017 target_alloc_working_area_try(): MMU disabled, using physical address for working memory 0x40800000 Debug: 2462 7082 target.c:2070 target_alloc_working_area_try(): allocated new working area of 5204 bytes at address 0x40800000 [OpenOCD] Debug: 2463 8685 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 2464 8685 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 2465 8685 target.c:1938 print_wa_layout(): 0x40801454-0x40823fff (142252 bytes) Debug: 2466 8685 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800000 [OpenOCD] Debug: 2467 8690 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800000 Debug: 2468 8698 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800200 Debug: 2469 8706 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2470 8706 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800400 Debug: 2471 8710 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800400 Debug: 2472 8719 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800600 Debug: 2473 8726 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2474 8726 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800800 Debug: 2475 8730 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800800 [OpenOCD] Debug: 2476 8737 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800a00 Debug: 2477 8746 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2478 8746 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800c00 Debug: 2479 8752 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800c00 Debug: 2480 8761 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800e00 Debug: 2481 8771 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2482 8771 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40801000 Debug: 2483 8776 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801000 [OpenOCD] Debug: 2484 8785 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801200 Debug: 2485 8795 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2486 8795 target.c:2379 target_write_buffer(): writing buffer of 82 byte at 0x40801400 Debug: 2487 8804 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801400 Debug: 2488 8810 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2489 8810 esp_riscv.c:826 esp_riscv_write_memory(): Use 32-bit access: size: 2 count:1 start address: 0x40801450 Debug: 2490 8824 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 2491 8831 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801450 [OpenOCD] Debug: 2492 8838 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2493 8838 target.c:2070 target_alloc_working_area_try(): allocated new working area of 4 bytes at address 0x40801454 Debug: 2494 8855 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 2495 8855 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 2496 8855 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 2497 8855 target.c:1938 print_wa_layout(): 0x40801458-0x40823fff (142248 bytes) Debug: 2498 8855 esp_algorithm.c:377 algorithm_load_func_image(): Write tramp to addr 0x40801454, sz 4 Debug: 2499 8855 target.c:2379 target_write_buffer(): writing buffer of 4 byte at 0x40801454 Debug: 2500 8866 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801454 Debug: 2501 8873 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2502 8873 esp_algorithm.c:388 algorithm_load_func_image(): Tramp mapped to addr 0x40801454 Debug: 2503 8873 target.c:2070 target_alloc_working_area_try(): allocated new working area of 11176 bytes at address 0x40801458 Debug: 2504 8873 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 2505 8873 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 2506 8873 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 2507 8873 target.c:1938 print_wa_layout(): 0x40804000-0x40823fff (131072 bytes) Debug: 2508 8873 esp_algorithm.c:413 algorithm_load_func_image(): addr 0x00000000, sz 321, flags 0 Debug: 2509 8873 esp_algorithm.c:417 algorithm_load_func_image(): DATA sec size 321 -> 324 Debug: 2510 8873 esp_algorithm.c:419 algorithm_load_func_image(): BSS sec size 316 -> 316 Debug: 2511 8873 target.c:2070 target_alloc_working_area_try(): allocated new working area of 640 bytes at address 0x40804000 [OpenOCD] Debug: 2512 9186 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 2513 9186 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 2514 9186 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 2515 9186 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 2516 9186 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 2517 9186 target.c:1938 print_wa_layout(): 0x40804280-0x40823fff (130432 bytes) Debug: 2518 9186 target.c:2379 target_write_buffer(): writing buffer of 321 byte at 0x40804000 [OpenOCD] Debug: 2519 9194 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804000 Debug: 2520 9207 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2521 9207 esp_riscv.c:826 esp_riscv_write_memory(): Use 32-bit access: size: 1 count:1 start address: 0x40804140 Debug: 2522 9224 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. [OpenOCD] Debug: 2523 9231 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804140 Debug: 2524 9235 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2525 9235 target.c:2070 target_alloc_working_area_try(): allocated new working area of 1024 bytes at address 0x40804280 [OpenOCD] Debug: 2526 9675 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 2527 9675 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 2528 9675 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 2529 9675 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 2530 9675 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 2531 9675 target.c:1938 print_wa_layout(): b* 0x40804280-0x4080467f (1024 bytes) Debug: 2532 9675 target.c:1938 print_wa_layout(): 0x40804680-0x40823fff (129408 bytes) Debug: 2533 9675 esp_algorithm.c:460 algorithm_load_func_image(): Stub loaded in 2593.04 ms Debug: 2534 9675 esp_riscv_algorithm.c:43 esp_riscv_algo_regs_init_start(): Check stack addr 0x40804680 Debug: 2535 9675 esp_riscv_algorithm.c:84 esp_riscv_algo_init(): Set arg[0] = 4 (a0) Debug: 2536 9675 esp.c:240 esp_common_assist_debug_monitor_disable(): [esp32c6] addr 0x600c2000 [OpenOCD] Debug: 2537 9687 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 2538 9687 target.c:2598 target_read_u32(): address: 0x600c2000, value: 0x00000000 Debug: 2539 9688 esp.c:248 esp_common_assist_debug_monitor_disable(): Saved register value 0x00000000 Debug: 2540 9688 target.c:2686 target_write_u32(): address: 0x600c2000, value: 0x00000000 Debug: 2541 9693 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600c2000 Debug: 2542 9697 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 2543 9697 esp_algorithm.c:90 algorithm_run_image(): Algorithm start @ 0x40801454, stack 1024 bytes @ 0x40804680 Debug: 2544 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save ra Debug: 2545 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read ra: 0x40801456 (cached) Debug: 2546 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x40801456 from ra (valid=1). Debug: 2547 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save sp Debug: 2548 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read sp: 0x40804780 (cached) Debug: 2549 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x40804780 from sp (valid=1). Debug: 2550 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save gp Debug: 2551 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read gp: 0x0 (cached) Debug: 2552 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from gp (valid=1). Debug: 2553 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save tp Debug: 2554 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read tp: 0x0 (cached) Debug: 2555 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tp (valid=1). Debug: 2556 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save t0 Debug: 2557 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read t0: 0x40027bd4 (cached) Debug: 2558 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x40027bd4 from t0 (valid=1). Debug: 2559 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save t1 Debug: 2560 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read t1: 0xffffffe0 (cached) Debug: 2561 9697 riscv.c:5259 register_get(): [esp32c6] Read 0xffffffe0 from t1 (valid=1). Debug: 2562 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save t2 Debug: 2563 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read t2: 0x0 (cached) Debug: 2564 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t2 (valid=1). Debug: 2565 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save fp Debug: 2566 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read fp: 0x0 (cached) Debug: 2567 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from fp (valid=1). Debug: 2568 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s1 Debug: 2569 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s1: 0x0 (cached) Debug: 2570 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s1 (valid=1). Debug: 2571 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save a0 Debug: 2572 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read a0: 0x20000000 (cached) Debug: 2573 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x20000000 from a0 (valid=1). Debug: 2574 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save a1 Debug: 2575 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read a1: 0x60002000 (cached) Debug: 2576 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x60002000 from a1 (valid=1). Debug: 2577 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save a2 Debug: 2578 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read a2: 0x10 (cached) Debug: 2579 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000010 from a2 (valid=1). Debug: 2580 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save a3 Debug: 2581 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read a3: 0x10000 (cached) Debug: 2582 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00010000 from a3 (valid=1). Debug: 2583 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save a4 Debug: 2584 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read a4: 0x408021e0 (cached) Debug: 2585 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x408021e0 from a4 (valid=1). Debug: 2586 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save a5 Debug: 2587 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read a5: 0x4 (cached) Debug: 2588 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000004 from a5 (valid=1). Debug: 2589 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save a6 Debug: 2590 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read a6: 0x8 (cached) Debug: 2591 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000008 from a6 (valid=1). Debug: 2592 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save a7 Debug: 2593 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read a7: 0x80000000 (cached) Debug: 2594 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x80000000 from a7 (valid=1). Debug: 2595 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s2 Debug: 2596 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s2: 0x0 (cached) Debug: 2597 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s2 (valid=1). Debug: 2598 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s3 Debug: 2599 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s3: 0x0 (cached) Debug: 2600 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s3 (valid=1). Debug: 2601 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s4 Debug: 2602 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s4: 0x0 (cached) Debug: 2603 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s4 (valid=1). Debug: 2604 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s5 Debug: 2605 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s5: 0x0 (cached) Debug: 2606 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s5 (valid=1). Debug: 2607 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s6 Debug: 2608 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s6: 0x0 (cached) Debug: 2609 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s6 (valid=1). Debug: 2610 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s7 Debug: 2611 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s7: 0x0 (cached) Debug: 2612 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s7 (valid=1). Debug: 2613 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s8 Debug: 2614 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s8: 0x0 (cached) Debug: 2615 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s8 (valid=1). Debug: 2616 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s9 Debug: 2617 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s9: 0x0 (cached) Debug: 2618 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s9 (valid=1). Debug: 2619 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s10 Debug: 2620 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s10: 0x0 (cached) Debug: 2621 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s10 (valid=1). Debug: 2622 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save s11 Debug: 2623 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read s11: 0x0 (cached) Debug: 2624 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s11 (valid=1). Debug: 2625 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save t3 Debug: 2626 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read t3: 0x0 (cached) Debug: 2627 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t3 (valid=1). Debug: 2628 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save t4 Debug: 2629 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read t4: 0x0 (cached) Debug: 2630 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t4 (valid=1). Debug: 2631 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save t5 Debug: 2632 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read t5: 0x0 (cached) Debug: 2633 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t5 (valid=1). Debug: 2634 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save t6 Debug: 2635 9697 riscv.c:4819 riscv_get_register(): [esp32c6] Read t6: 0x0 (cached) Debug: 2636 9697 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t6 (valid=1). Debug: 2637 9697 esp_riscv.c:593 esp_riscv_start_algorithm(): save pc Debug: 2638 9697 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 2639 9697 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 2640 9697 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 2641 9697 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 2642 9708 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40000000 Debug: 2643 9708 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40000000 Debug: 2644 9708 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40000000 Debug: 2645 9708 riscv.c:5259 register_get(): [esp32c6] Read 0x40000000 from pc (valid=0). Debug: 2646 9708 esp_riscv.c:593 esp_riscv_start_algorithm(): save mstatus Debug: 2647 9708 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mstatus from target Debug: 2648 9708 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mstatus Debug: 2649 9708 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mstatus Debug: 2650 9708 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 2651 9714 riscv-013.c:1561 register_read_direct(): [esp32c6] mstatus = 0x201800 Debug: 2652 9714 riscv.c:4831 riscv_get_register(): [esp32c6] Read mstatus: 0x201800 Debug: 2653 9714 riscv.c:5259 register_get(): [esp32c6] Read 0x00201800 from mstatus (valid=1). Debug: 2654 9714 esp_riscv.c:593 esp_riscv_start_algorithm(): save misa Debug: 2655 9714 riscv.c:4823 riscv_get_register(): [esp32c6] Reading misa from target Debug: 2656 9714 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register misa Debug: 2657 9714 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading misa Debug: 2658 9714 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 2659 9720 riscv-013.c:1561 register_read_direct(): [esp32c6] misa = 0x40903105 Debug: 2660 9720 riscv.c:4831 riscv_get_register(): [esp32c6] Read misa: 0x40903105 Debug: 2661 9720 riscv.c:5259 register_get(): [esp32c6] Read 0x40903105 from misa (valid=1). Debug: 2662 9720 esp_riscv.c:593 esp_riscv_start_algorithm(): save mtvec Debug: 2663 9720 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mtvec from target Debug: 2664 9720 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr773 Debug: 2665 9720 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr773 Debug: 2666 9720 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305 [OpenOCD] Debug: 2667 9726 riscv-013.c:1561 register_read_direct(): [esp32c6] csr773 = 0x1 Debug: 2668 9726 riscv.c:4831 riscv_get_register(): [esp32c6] Read mtvec: 0x1 Debug: 2669 9726 riscv.c:5259 register_get(): [esp32c6] Read 0x00000001 from mtvec (valid=0). Debug: 2670 9726 esp_riscv.c:593 esp_riscv_start_algorithm(): save mscratch Debug: 2671 9726 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mscratch from target Debug: 2672 9726 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr832 Debug: 2673 9726 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr832 Debug: 2674 9726 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340 Debug: 2675 9730 riscv-013.c:1561 register_read_direct(): [esp32c6] csr832 = 0x0 Debug: 2676 9730 riscv.c:4831 riscv_get_register(): [esp32c6] Read mscratch: 0x0 Debug: 2677 9730 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mscratch (valid=0). Debug: 2678 9730 esp_riscv.c:593 esp_riscv_start_algorithm(): save mepc Debug: 2679 9730 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mepc from target Debug: 2680 9730 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mepc Debug: 2681 9730 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mepc Debug: 2682 9730 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 2683 9738 riscv-013.c:1561 register_read_direct(): [esp32c6] mepc = 0x0 Debug: 2684 9738 riscv.c:4831 riscv_get_register(): [esp32c6] Read mepc: 0x0 Debug: 2685 9738 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mepc (valid=1). Debug: 2686 9738 esp_riscv.c:593 esp_riscv_start_algorithm(): save mcause Debug: 2687 9738 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mcause from target Debug: 2688 9738 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mcause Debug: 2689 9738 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mcause Debug: 2690 9738 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 Debug: 2691 9746 riscv-013.c:1561 register_read_direct(): [esp32c6] mcause = 0x0 Debug: 2692 9746 riscv.c:4831 riscv_get_register(): [esp32c6] Read mcause: 0x0 Debug: 2693 9746 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mcause (valid=1). Debug: 2694 9746 esp_riscv.c:593 esp_riscv_start_algorithm(): save mtval Debug: 2695 9746 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mtval from target Debug: 2696 9746 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr835 Debug: 2697 9746 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr835 Debug: 2698 9746 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343 Debug: 2699 9754 riscv-013.c:1561 register_read_direct(): [esp32c6] csr835 = 0x0 Debug: 2700 9754 riscv.c:4831 riscv_get_register(): [esp32c6] Read mtval: 0x0 Debug: 2701 9754 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mtval (valid=0). Debug: 2702 9754 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg0 Debug: 2703 9754 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg0 from target Debug: 2704 9754 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr928 Debug: 2705 9754 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr928 Debug: 2706 9754 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0 Debug: 2707 9760 riscv-013.c:1561 register_read_direct(): [esp32c6] csr928 = 0x0 Debug: 2708 9760 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg0: 0x0 Debug: 2709 9760 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg0 (valid=0). Debug: 2710 9760 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg1 Debug: 2711 9760 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg1 from target Debug: 2712 9760 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr929 Debug: 2713 9760 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr929 Debug: 2714 9760 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1 Debug: 2715 9767 riscv-013.c:1561 register_read_direct(): [esp32c6] csr929 = 0x0 Debug: 2716 9767 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg1: 0x0 Debug: 2717 9767 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg1 (valid=0). Debug: 2718 9767 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg2 Debug: 2719 9767 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg2 from target Debug: 2720 9767 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr930 Debug: 2721 9767 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr930 Debug: 2722 9767 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2 Debug: 2723 9774 riscv-013.c:1561 register_read_direct(): [esp32c6] csr930 = 0x0 Debug: 2724 9774 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg2: 0x0 Debug: 2725 9774 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg2 (valid=0). Debug: 2726 9774 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg3 Debug: 2727 9774 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg3 from target Debug: 2728 9774 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr931 Debug: 2729 9774 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr931 Debug: 2730 9774 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3 [OpenOCD] Debug: 2731 9780 riscv-013.c:1561 register_read_direct(): [esp32c6] csr931 = 0x0 Debug: 2732 9780 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg3: 0x0 Debug: 2733 9780 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg3 (valid=0). Debug: 2734 9780 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr0 Debug: 2735 9780 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr0 from target Debug: 2736 9780 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr944 Debug: 2737 9780 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr944 Debug: 2738 9780 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0 Debug: 2739 9788 riscv-013.c:1561 register_read_direct(): [esp32c6] csr944 = 0x0 Debug: 2740 9788 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr0: 0x0 Debug: 2741 9788 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr0 (valid=0). Debug: 2742 9788 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr1 Debug: 2743 9788 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr1 from target Debug: 2744 9788 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr945 Debug: 2745 9788 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr945 Debug: 2746 9788 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1 Debug: 2747 9797 riscv-013.c:1561 register_read_direct(): [esp32c6] csr945 = 0x0 Debug: 2748 9797 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr1: 0x0 Debug: 2749 9797 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr1 (valid=0). Debug: 2750 9797 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr2 Debug: 2751 9797 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr2 from target Debug: 2752 9797 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr946 Debug: 2753 9797 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr946 Debug: 2754 9797 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2 Debug: 2755 9828 riscv-013.c:1561 register_read_direct(): [esp32c6] csr946 = 0x0 Debug: 2756 9828 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr2: 0x0 Debug: 2757 9828 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr2 (valid=0). Debug: 2758 9828 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr3 Debug: 2759 9828 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr3 from target Debug: 2760 9828 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr947 Debug: 2761 9828 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr947 Debug: 2762 9828 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3 Debug: 2763 9839 riscv-013.c:1561 register_read_direct(): [esp32c6] csr947 = 0x0 Debug: 2764 9839 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr3: 0x0 Debug: 2765 9839 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr3 (valid=0). Debug: 2766 9839 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr4 Debug: 2767 9839 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr4 from target Debug: 2768 9839 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr948 Debug: 2769 9839 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr948 Debug: 2770 9839 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4 Debug: 2771 9848 riscv-013.c:1561 register_read_direct(): [esp32c6] csr948 = 0x0 Debug: 2772 9848 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr4: 0x0 Debug: 2773 9848 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr4 (valid=0). Debug: 2774 9848 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr5 Debug: 2775 9848 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr5 from target Debug: 2776 9848 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr949 Debug: 2777 9848 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr949 Debug: 2778 9848 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5 Debug: 2779 9857 riscv-013.c:1561 register_read_direct(): [esp32c6] csr949 = 0x0 Debug: 2780 9857 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr5: 0x0 Debug: 2781 9857 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr5 (valid=0). Debug: 2782 9857 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr6 Debug: 2783 9857 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr6 from target Debug: 2784 9857 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr950 Debug: 2785 9857 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr950 Debug: 2786 9857 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6 Debug: 2787 9865 riscv-013.c:1561 register_read_direct(): [esp32c6] csr950 = 0x0 Debug: 2788 9865 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr6: 0x0 Debug: 2789 9865 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr6 (valid=0). Debug: 2790 9865 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr7 Debug: 2791 9865 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr7 from target Debug: 2792 9865 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr951 [OpenOCD] Debug: 2793 9865 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr951 Debug: 2794 9865 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7 Debug: 2795 9875 riscv-013.c:1561 register_read_direct(): [esp32c6] csr951 = 0x0 Debug: 2796 9875 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr7: 0x0 Debug: 2797 9875 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr7 (valid=0). Debug: 2798 9875 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr8 Debug: 2799 9875 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr8 from target Debug: 2800 9875 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr952 Debug: 2801 9875 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr952 Debug: 2802 9875 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8 Debug: 2803 9884 riscv-013.c:1561 register_read_direct(): [esp32c6] csr952 = 0x0 Debug: 2804 9884 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr8: 0x0 Debug: 2805 9884 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr8 (valid=0). Debug: 2806 9884 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr9 Debug: 2807 9884 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr9 from target Debug: 2808 9884 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr953 Debug: 2809 9884 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr953 Debug: 2810 9884 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9 Debug: 2811 9891 riscv-013.c:1561 register_read_direct(): [esp32c6] csr953 = 0x0 Debug: 2812 9891 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr9: 0x0 Debug: 2813 9891 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr9 (valid=0). Debug: 2814 9891 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr10 Debug: 2815 9891 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr10 from target Debug: 2816 9891 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr954 Debug: 2817 9891 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr954 Debug: 2818 9891 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba Debug: 2819 9900 riscv-013.c:1561 register_read_direct(): [esp32c6] csr954 = 0x0 Debug: 2820 9900 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr10: 0x0 Debug: 2821 9900 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr10 (valid=0). Debug: 2822 9900 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr11 Debug: 2823 9900 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr11 from target Debug: 2824 9900 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr955 Debug: 2825 9900 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr955 Debug: 2826 9900 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb Debug: 2827 9908 riscv-013.c:1561 register_read_direct(): [esp32c6] csr955 = 0x0 Debug: 2828 9908 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr11: 0x0 Debug: 2829 9908 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr11 (valid=0). Debug: 2830 9908 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr12 Debug: 2831 9908 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr12 from target Debug: 2832 9908 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr956 Debug: 2833 9908 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr956 Debug: 2834 9908 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc Debug: 2835 9914 riscv-013.c:1561 register_read_direct(): [esp32c6] csr956 = 0x0 Debug: 2836 9914 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr12: 0x0 Debug: 2837 9914 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr12 (valid=0). Debug: 2838 9914 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr13 Debug: 2839 9914 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr13 from target Debug: 2840 9914 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr957 Debug: 2841 9914 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr957 Debug: 2842 9914 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd [OpenOCD] Debug: 2843 9921 riscv-013.c:1561 register_read_direct(): [esp32c6] csr957 = 0x0 Debug: 2844 9921 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr13: 0x0 Debug: 2845 9921 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr13 (valid=0). Debug: 2846 9921 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr14 Debug: 2847 9921 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr14 from target Debug: 2848 9921 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr958 Debug: 2849 9921 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr958 Debug: 2850 9921 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be Debug: 2851 9928 riscv-013.c:1561 register_read_direct(): [esp32c6] csr958 = 0x0 Debug: 2852 9928 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr14: 0x0 Debug: 2853 9928 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr14 (valid=0). Debug: 2854 9928 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr15 Debug: 2855 9928 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr15 from target Debug: 2856 9928 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr959 Debug: 2857 9928 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr959 Debug: 2858 9928 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf Debug: 2859 9944 riscv-013.c:1561 register_read_direct(): [esp32c6] csr959 = 0x0 Debug: 2860 9944 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr15: 0x0 Debug: 2861 9944 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr15 (valid=0). Debug: 2862 9944 esp_riscv.c:593 esp_riscv_start_algorithm(): save tselect Debug: 2863 9944 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 2864 9944 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 2865 9944 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 2866 9944 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 2867 10001 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x0 Debug: 2868 10001 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x0 Debug: 2869 10001 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tselect (valid=0). Debug: 2870 10001 esp_riscv.c:593 esp_riscv_start_algorithm(): save tdata1 Debug: 2871 10001 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata1 from target Debug: 2872 10001 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata1 Debug: 2873 10001 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata1 Debug: 2874 10001 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 [OpenOCD] Debug: 2875 10026 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata1 = 0x23e00000 Debug: 2876 10026 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata1: 0x23e00000 Debug: 2877 10026 riscv.c:5259 register_get(): [esp32c6] Read 0x23e00000 from tdata1 (valid=0). Debug: 2878 10026 esp_riscv.c:593 esp_riscv_start_algorithm(): save tdata2 Debug: 2879 10026 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata2 from target Debug: 2880 10026 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata2 Debug: 2881 10026 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata2 Debug: 2882 10026 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2 Debug: 2883 10036 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata2 = 0x0 Debug: 2884 10036 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata2: 0x0 Debug: 2885 10036 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tdata2 (valid=0). Debug: 2886 10036 esp_riscv.c:593 esp_riscv_start_algorithm(): save tcontrol Debug: 2887 10036 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tcontrol from target Debug: 2888 10036 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr1957 Debug: 2889 10036 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr1957 Debug: 2890 10036 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5 Debug: 2891 10048 riscv-013.c:1561 register_read_direct(): [esp32c6] csr1957 = 0x0 Debug: 2892 10048 riscv.c:4831 riscv_get_register(): [esp32c6] Read tcontrol: 0x0 Debug: 2893 10048 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tcontrol (valid=0). Debug: 2894 10048 esp_riscv.c:593 esp_riscv_start_algorithm(): save dcsr Debug: 2895 10048 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dcsr from target Debug: 2896 10048 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dcsr Debug: 2897 10048 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 2898 10048 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 2899 10060 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 2900 10060 riscv.c:4831 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 Debug: 2901 10060 riscv.c:5259 register_get(): [esp32c6] Read 0x400090c3 from dcsr (valid=1). Debug: 2902 10060 esp_riscv.c:593 esp_riscv_start_algorithm(): save dpc Debug: 2903 10060 riscv.c:4819 riscv_get_register(): [esp32c6] Read dpc: 0x40000000 (cached) Debug: 2904 10060 riscv.c:5259 register_get(): [esp32c6] Read 0x40000000 from dpc (valid=1). Debug: 2905 10060 esp_riscv.c:593 esp_riscv_start_algorithm(): save dscratch0 Debug: 2906 10060 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dscratch0 from target Debug: 2907 10060 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dscratch0 Debug: 2908 10060 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dscratch0 Debug: 2909 10060 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2 Debug: 2910 10066 riscv-013.c:1561 register_read_direct(): [esp32c6] dscratch0 = 0x0 Debug: 2911 10066 riscv.c:4831 riscv_get_register(): [esp32c6] Read dscratch0: 0x0 Debug: 2912 10066 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from dscratch0 (valid=1). Debug: 2913 10066 esp_riscv.c:593 esp_riscv_start_algorithm(): save dscratch1 Debug: 2914 10066 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dscratch1 from target Debug: 2915 10066 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr1971 Debug: 2916 10066 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr1971 Debug: 2917 10066 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3 Debug: 2918 10073 riscv-013.c:1561 register_read_direct(): [esp32c6] csr1971 = 0x20000000 Debug: 2919 10073 riscv.c:4831 riscv_get_register(): [esp32c6] Read dscratch1: 0x20000000 Debug: 2920 10073 riscv.c:5259 register_get(): [esp32c6] Read 0x20000000 from dscratch1 (valid=0). Debug: 2921 10073 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpcer Debug: 2922 10073 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpcer from target Debug: 2923 10073 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2016 Debug: 2924 10073 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2016 Debug: 2925 10073 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e0 Debug: 2926 10080 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2016 = 0x0 Debug: 2927 10080 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpcer: 0x0 Debug: 2928 10080 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_mpcer (valid=0). Debug: 2929 10080 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpcmr Debug: 2930 10080 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpcmr from target Debug: 2931 10080 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2017 Debug: 2932 10080 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2017 Debug: 2933 10080 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e1 [OpenOCD] Debug: 2934 10088 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2017 = 0x3 Debug: 2935 10088 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpcmr: 0x3 Debug: 2936 10088 riscv.c:5259 register_get(): [esp32c6] Read 0x00000003 from csr_mpcmr (valid=0). Debug: 2937 10088 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpccr Debug: 2938 10088 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpccr from target Debug: 2939 10088 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2018 Debug: 2940 10088 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2018 Debug: 2941 10088 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e2 Debug: 2942 10097 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2018 = 0x0 Debug: 2943 10097 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpccr: 0x0 Debug: 2944 10097 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_mpccr (valid=0). Debug: 2945 10097 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_oen Debug: 2946 10097 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_oen from target Debug: 2947 10097 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2051 Debug: 2948 10097 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2051 Debug: 2949 10097 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220803; access register, size=32, postexec=0, transfer=1, write=0, regno=0x803 Debug: 2950 10109 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2051 = 0x0 Debug: 2951 10109 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_oen: 0x0 Debug: 2952 10109 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_oen (valid=0). Debug: 2953 10109 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_in Debug: 2954 10109 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_in from target Debug: 2955 10109 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2052 Debug: 2956 10109 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2052 Debug: 2957 10109 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220804; access register, size=32, postexec=0, transfer=1, write=0, regno=0x804 Debug: 2958 10120 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2052 = 0x0 Debug: 2959 10120 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_in: 0x0 Debug: 2960 10120 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_in (valid=0). Debug: 2961 10120 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_out Debug: 2962 10120 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_out from target Debug: 2963 10120 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2053 Debug: 2964 10120 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2053 Debug: 2965 10120 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220805; access register, size=32, postexec=0, transfer=1, write=0, regno=0x805 Debug: 2966 10129 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2053 = 0x0 Debug: 2967 10129 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_out: 0x0 Debug: 2968 10129 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_out (valid=0). Debug: 2969 10129 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg0 Debug: 2970 10129 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg0 from target Debug: 2971 10129 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3008 Debug: 2972 10129 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3008 Debug: 2973 10129 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc0 Debug: 2974 10135 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3008 = 0x0 Debug: 2975 10135 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg0: 0x0 Debug: 2976 10135 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg0 (valid=0). Debug: 2977 10135 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg1 Debug: 2978 10135 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg1 from target Debug: 2979 10135 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3009 Debug: 2980 10135 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3009 Debug: 2981 10135 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc1; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc1 Debug: 2982 10141 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3009 = 0x0 Debug: 2983 10141 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg1: 0x0 Debug: 2984 10141 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg1 (valid=0). Debug: 2985 10141 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg2 Debug: 2986 10141 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg2 from target Debug: 2987 10141 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3010 Debug: 2988 10141 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3010 Debug: 2989 10141 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc2; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc2 [OpenOCD] Debug: 2990 10147 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3010 = 0x0 Debug: 2991 10147 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg2: 0x0 Debug: 2992 10147 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg2 (valid=0). Debug: 2993 10147 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg3 Debug: 2994 10147 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg3 from target Debug: 2995 10147 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3011 Debug: 2996 10147 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3011 Debug: 2997 10147 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc3; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc3 Debug: 2998 10203 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3011 = 0x0 Debug: 2999 10203 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg3: 0x0 Debug: 3000 10203 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg3 (valid=0). Debug: 3001 10203 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg4 Debug: 3002 10203 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg4 from target Debug: 3003 10203 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3012 Debug: 3004 10203 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3012 Debug: 3005 10203 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc4; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc4 Debug: 3006 10214 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3012 = 0x0 Debug: 3007 10214 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg4: 0x0 Debug: 3008 10214 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg4 (valid=0). Debug: 3009 10214 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg5 Debug: 3010 10214 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg5 from target Debug: 3011 10214 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3013 Debug: 3012 10214 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3013 Debug: 3013 10214 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc5; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc5 Debug: 3014 10226 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3013 = 0x0 Debug: 3015 10226 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg5: 0x0 Debug: 3016 10226 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg5 (valid=0). Debug: 3017 10226 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg6 Debug: 3018 10226 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg6 from target Debug: 3019 10226 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3014 Debug: 3020 10226 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3014 Debug: 3021 10226 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc6; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc6 Debug: 3022 10233 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3014 = 0x0 Debug: 3023 10233 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg6: 0x0 Debug: 3024 10233 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg6 (valid=0). Debug: 3025 10233 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg7 Debug: 3026 10233 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg7 from target Debug: 3027 10233 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3015 Debug: 3028 10233 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3015 Debug: 3029 10233 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc7; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc7 Debug: 3030 10239 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3015 = 0x0 Debug: 3031 10239 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg7: 0x0 Debug: 3032 10239 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg7 (valid=0). Debug: 3033 10239 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg8 Debug: 3034 10239 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg8 from target Debug: 3035 10239 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3016 Debug: 3036 10239 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3016 Debug: 3037 10239 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc8; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc8 Debug: 3038 10245 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3016 = 0x0 Debug: 3039 10245 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg8: 0x0 Debug: 3040 10245 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg8 (valid=0). Debug: 3041 10245 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg9 Debug: 3042 10245 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg9 from target Debug: 3043 10245 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3017 Debug: 3044 10245 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3017 Debug: 3045 10245 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc9; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc9 Debug: 3046 10253 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3017 = 0x0 Debug: 3047 10253 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg9: 0x0 Debug: 3048 10253 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg9 (valid=0). Debug: 3049 10253 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg10 Debug: 3050 10253 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg10 from target Debug: 3051 10253 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3018 Debug: 3052 10253 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3018 Debug: 3053 10253 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bca; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbca [OpenOCD] Debug: 3054 10261 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3018 = 0x0 Debug: 3055 10261 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg10: 0x0 Debug: 3056 10261 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg10 (valid=0). Debug: 3057 10261 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg11 Debug: 3058 10261 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg11 from target Debug: 3059 10261 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3019 Debug: 3060 10261 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3019 Debug: 3061 10261 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcb; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcb Debug: 3062 10270 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3019 = 0x0 Debug: 3063 10270 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg11: 0x0 Debug: 3064 10270 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg11 (valid=0). Debug: 3065 10270 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg12 Debug: 3066 10270 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg12 from target Debug: 3067 10270 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3020 Debug: 3068 10270 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3020 Debug: 3069 10270 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcc; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcc Debug: 3070 10279 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3020 = 0x0 Debug: 3071 10279 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg12: 0x0 Debug: 3072 10279 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg12 (valid=0). Debug: 3073 10279 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg13 Debug: 3074 10279 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg13 from target Debug: 3075 10279 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3021 Debug: 3076 10279 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3021 Debug: 3077 10279 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcd; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcd Debug: 3078 10292 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3021 = 0x0 Debug: 3079 10292 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg13: 0x0 Debug: 3080 10292 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg13 (valid=0). Debug: 3081 10292 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg14 Debug: 3082 10292 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg14 from target Debug: 3083 10292 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3022 Debug: 3084 10292 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3022 Debug: 3085 10292 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bce; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbce Debug: 3086 10300 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3022 = 0x0 Debug: 3087 10300 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg14: 0x0 Debug: 3088 10300 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg14 (valid=0). Debug: 3089 10300 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg15 Debug: 3090 10300 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg15 from target Debug: 3091 10300 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3023 Debug: 3092 10300 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3023 Debug: 3093 10300 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcf; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcf Debug: 3094 10307 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3023 = 0x0 Debug: 3095 10308 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg15: 0x0 Debug: 3096 10308 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg15 (valid=0). Debug: 3097 10308 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr0 Debug: 3098 10308 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr0 from target Debug: 3099 10308 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3024 Debug: 3100 10308 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3024 Debug: 3101 10308 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd0 [OpenOCD] Debug: 3102 10315 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3024 = 0x0 Debug: 3103 10315 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr0: 0x0 Debug: 3104 10315 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr0 (valid=0). Debug: 3105 10315 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr1 Debug: 3106 10315 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr1 from target Debug: 3107 10315 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3025 Debug: 3108 10315 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3025 Debug: 3109 10315 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd1; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd1 Debug: 3110 10327 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3025 = 0x0 Debug: 3111 10327 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr1: 0x0 Debug: 3112 10327 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr1 (valid=0). Debug: 3113 10327 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr2 Debug: 3114 10327 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr2 from target Debug: 3115 10327 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3026 Debug: 3116 10327 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3026 Debug: 3117 10327 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd2; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd2 Debug: 3118 10337 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3026 = 0x0 Debug: 3119 10337 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr2: 0x0 Debug: 3120 10337 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr2 (valid=0). Debug: 3121 10337 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr3 Debug: 3122 10337 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr3 from target Debug: 3123 10337 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3027 Debug: 3124 10337 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3027 Debug: 3125 10337 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd3; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd3 Debug: 3126 10348 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3027 = 0x0 Debug: 3127 10348 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr3: 0x0 Debug: 3128 10348 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr3 (valid=0). Debug: 3129 10348 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr4 Debug: 3130 10348 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr4 from target Debug: 3131 10348 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3028 Debug: 3132 10348 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3028 Debug: 3133 10348 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd4; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd4 Debug: 3134 10357 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3028 = 0x0 Debug: 3135 10357 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr4: 0x0 Debug: 3136 10357 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr4 (valid=0). Debug: 3137 10357 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr5 Debug: 3138 10357 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr5 from target Debug: 3139 10357 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3029 Debug: 3140 10357 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3029 Debug: 3141 10357 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd5; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd5 Debug: 3142 10362 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3029 = 0x0 Debug: 3143 10362 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr5: 0x0 Debug: 3144 10362 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr5 (valid=0). Debug: 3145 10362 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr6 Debug: 3146 10362 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr6 from target Debug: 3147 10362 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3030 Debug: 3148 10362 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3030 Debug: 3149 10362 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd6; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd6 [OpenOCD] Debug: 3150 10368 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3030 = 0x0 Debug: 3151 10368 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr6: 0x0 Debug: 3152 10368 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr6 (valid=0). Debug: 3153 10368 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr7 Debug: 3154 10368 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr7 from target Debug: 3155 10368 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3031 Debug: 3156 10368 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3031 Debug: 3157 10368 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd7; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd7 Debug: 3158 10375 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3031 = 0x0 Debug: 3159 10375 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr7: 0x0 Debug: 3160 10375 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr7 (valid=0). Debug: 3161 10375 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr8 Debug: 3162 10375 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr8 from target Debug: 3163 10375 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3032 Debug: 3164 10375 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3032 Debug: 3165 10375 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd8; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd8 Debug: 3166 10385 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3032 = 0x0 Debug: 3167 10385 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr8: 0x0 Debug: 3168 10385 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr8 (valid=0). Debug: 3169 10385 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr9 Debug: 3170 10385 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr9 from target Debug: 3171 10385 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3033 Debug: 3172 10385 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3033 Debug: 3173 10385 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd9; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd9 Debug: 3174 10396 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3033 = 0x0 Debug: 3175 10396 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr9: 0x0 Debug: 3176 10396 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr9 (valid=0). Debug: 3177 10396 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr10 Debug: 3178 10396 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr10 from target Debug: 3179 10396 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3034 Debug: 3180 10396 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3034 Debug: 3181 10396 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bda; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbda Debug: 3182 10407 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3034 = 0x0 Debug: 3183 10407 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr10: 0x0 Debug: 3184 10407 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr10 (valid=0). Debug: 3185 10407 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr11 Debug: 3186 10407 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr11 from target Debug: 3187 10407 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3035 Debug: 3188 10407 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3035 Debug: 3189 10407 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdb; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdb Debug: 3190 10415 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3035 = 0x0 Debug: 3191 10415 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr11: 0x0 Debug: 3192 10415 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr11 (valid=0). Debug: 3193 10415 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr12 Debug: 3194 10415 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr12 from target Debug: 3195 10415 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3036 Debug: 3196 10415 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3036 Debug: 3197 10415 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdc; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdc Debug: 3198 10422 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3036 = 0x0 Debug: 3199 10422 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr12: 0x0 Debug: 3200 10422 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr12 (valid=0). Debug: 3201 10422 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr13 Debug: 3202 10422 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr13 from target Debug: 3203 10422 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3037 Debug: 3204 10422 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3037 Debug: 3205 10422 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdd; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdd [OpenOCD] Debug: 3206 10431 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3037 = 0x0 Debug: 3207 10431 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr13: 0x0 Debug: 3208 10431 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr13 (valid=0). Debug: 3209 10431 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr14 Debug: 3210 10431 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr14 from target Debug: 3211 10431 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3038 Debug: 3212 10431 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3038 Debug: 3213 10431 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bde; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbde Debug: 3214 10496 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3038 = 0x0 Debug: 3215 10496 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr14: 0x0 Debug: 3216 10496 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr14 (valid=0). Debug: 3217 10496 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr15 Debug: 3218 10496 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr15 from target Debug: 3219 10496 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3039 Debug: 3220 10496 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3039 Debug: 3221 10496 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdf; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdf Debug: 3222 10506 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3039 = 0x0 Debug: 3223 10506 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr15: 0x0 Debug: 3224 10507 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr15 (valid=0). Debug: 3225 10507 esp_riscv.c:593 esp_riscv_start_algorithm(): save hpmcounter16 Debug: 3226 10507 riscv.c:4823 riscv_get_register(): [esp32c6] Reading hpmcounter16 from target Debug: 3227 10507 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3088 Debug: 3228 10507 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3088 Debug: 3229 10507 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10 Debug: 3230 10519 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3088 = 0x3 Debug: 3231 10519 riscv.c:4831 riscv_get_register(): [esp32c6] Read hpmcounter16: 0x3 Debug: 3232 10519 riscv.c:5259 register_get(): [esp32c6] Read 0x00000003 from hpmcounter16 (valid=0). Debug: 3233 10519 esp_riscv.c:593 esp_riscv_start_algorithm(): save priv Debug: 3234 10519 riscv.c:4823 riscv_get_register(): [esp32c6] Reading priv from target Debug: 3235 10519 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register priv Debug: 3236 10519 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 3237 10519 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 [OpenOCD] Debug: 3238 10530 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 3239 10530 riscv.c:4831 riscv_get_register(): [esp32c6] Read priv: 0x3 Debug: 3240 10530 riscv.c:5259 register_get(): [esp32c6] Read 0x03 from priv (valid=0). Debug: 3241 10530 esp_riscv.c:622 esp_riscv_start_algorithm(): set sp Debug: 3242 10530 riscv.c:5274 register_set(): [esp32c6] Write 0x40804670 to sp (valid=1). Debug: 3243 10530 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804670 to sp (cacheable=true, valid=true, dirty=true) Debug: 3244 10530 esp_riscv.c:622 esp_riscv_start_algorithm(): set a7 Debug: 3245 10530 riscv.c:5274 register_set(): [esp32c6] Write 0x4080110c to a7 (valid=1). Debug: 3246 10530 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4080110c to a7 (cacheable=true, valid=true, dirty=true) Debug: 3247 10530 esp_riscv.c:622 esp_riscv_start_algorithm(): set a0 Debug: 3248 10530 riscv.c:5274 register_set(): [esp32c6] Write 0x00000004 to a0 (valid=1). Debug: 3249 10530 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4 to a0 (cacheable=true, valid=true, dirty=true) Debug: 3250 10530 riscv.c:4550 riscv_interrupts_disable(): [esp32c6] Disabling interrupts. Debug: 3251 10530 riscv.c:4819 riscv_get_register(): [esp32c6] Read mstatus: 0x201800 (cached) Debug: 3252 10530 riscv.c:5259 register_get(): [esp32c6] Read 0x00201800 from mstatus (valid=1). Debug: 3253 10530 riscv.c:5274 register_set(): [esp32c6] Write 0x00201800 to mstatus (valid=1). Debug: 3254 10530 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x201800 to mstatus (cacheable=true, valid=true, dirty=false) Debug: 3255 10530 esp_riscv.c:659 esp_riscv_start_algorithm(): resume at 0x40801454 Debug: 3256 10530 riscv.c:1932 riscv_resume(): [esp32c6] current=false, address=0x40801454, handle_breakpoints=false, debug_exec=true Debug: 3257 10530 riscv.c:1937 riscv_resume(): [esp32c6] target->state=halted Debug: 3258 10530 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pc <- 0x40801454 (cacheable=false, valid=false, dirty=false) Debug: 3259 10530 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40801454 to register pc Debug: 3260 10530 riscv-013.c:4562 riscv013_set_register(): [esp32c6] writing PC to DPC: 0x40801454 Debug: 3261 10530 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40801454 to dpc Debug: 3262 10536 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 3263 10542 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40801454 Debug: 3264 10542 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40801454 to pc (cacheable=false, valid=false, dirty=false) Debug: 3265 10542 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[00] = DASM(0x0000100f) Debug: 3266 10542 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x100f @0 Debug: 3267 10542 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[01] = DASM(0x0330000f) Debug: 3268 10542 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x330000f @1 Debug: 3269 10542 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[02] = DASM(0x00100073) Debug: 3270 10542 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x100073 @2 Debug: 3271 10542 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 3272 10548 riscv-013.c:1591 set_dcsr_ebreak(): [esp32c6] Set dcsr.ebreak* Debug: 3273 10548 riscv.c:4819 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 (cached) Debug: 3274 10548 riscv.c:1575 riscv_flush_registers(): [esp32c6] a7 is dirty; write back 0x4080110c Debug: 3275 10548 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4080110c to register a7 Debug: 3276 10548 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4080110c to a7 Debug: 3277 10552 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 3278 10558 riscv-013.c:1532 register_write_direct(): [esp32c6] a7 <- 0x4080110c Debug: 3279 10558 riscv.c:1575 riscv_flush_registers(): [esp32c6] a0 is dirty; write back 0x4 Debug: 3280 10558 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4 to register a0 Debug: 3281 10558 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4 to a0 Debug: 3282 10561 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 3283 10566 riscv-013.c:1532 register_write_direct(): [esp32c6] a0 <- 0x4 Debug: 3284 10566 riscv.c:1575 riscv_flush_registers(): [esp32c6] sp is dirty; write back 0x40804670 Debug: 3285 10566 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40804670 to register sp Debug: 3286 10566 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40804670 to sp Debug: 3287 10570 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 3288 10574 riscv-013.c:1532 register_write_direct(): [esp32c6] sp <- 0x40804670 Debug: 3289 10574 riscv.c:1858 resume_prep(): [esp32c6] Mark as prepped. Debug: 3290 10574 riscv.c:4536 riscv_resume_go_all_harts(): [esp32c6] Resuming hart, state=2. Debug: 3291 10574 riscv-013.c:4625 select_prepped_harts(): [esp32c6] index=0, coreid=0, prepped=1 Debug: 3292 10574 riscv-013.c:4922 riscv013_step_or_resume_current_hart(): [esp32c6] resuming (for step?=0) Debug: 3293 10581 riscv.c:4640 riscv_invalidate_register_cache(): [esp32c6] Invalidating register cache. Debug: 3294 10581 target.c:1812 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c6 Debug: 3295 10581 esp_algorithm.c:111 algorithm_run_image(): Wait algorithm completion Debug: 3296 10585 riscv.c:2779 riscv_poll_hart(): [esp32c6] triggered a halt; previous_target_state=4 Debug: 3297 10585 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 3298 10585 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 [OpenOCD] Debug: 3299 10594 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x40009043 Debug: 3300 10594 riscv-013.c:4791 riscv013_halt_reason(): [esp32c6] dcsr.cause: 0x1 Debug: 3301 10594 riscv.c:1621 set_debug_reason(): [esp32c6] debug_reason=1 Debug: 3302 10594 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 3303 10594 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 3304 10594 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 3305 10594 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 3306 10604 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40801456 Debug: 3307 10604 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40801456 Debug: 3308 10604 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40801456 Debug: 3309 10604 esp_riscv.c:799 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40801452 Debug: 3310 10630 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 3311 10630 riscv_semihosting.c:94 riscv_semihosting(): [esp32c6] compare 0x98820613 from 0x40801452 against 0x01f01013 Debug: 3312 10630 riscv_semihosting.c:96 riscv_semihosting(): [esp32c6] -> NONE (no magic) Debug: 3313 10630 target.c:1812 target_call_event_callbacks(): target event 17 (debug-halted) for core esp32c6 Debug: 3314 10630 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 3315 10630 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 3316 10630 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 3317 10630 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 3318 10638 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40801456 Debug: 3319 10638 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40801456 Debug: 3320 10638 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40801456 Debug: 3321 10638 riscv.c:5259 register_get(): [esp32c6] Read 0x40801456 from pc (valid=0). Debug: 3322 10638 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a0 from target Debug: 3323 10638 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a0 Debug: 3324 10638 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a0 Debug: 3325 10638 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a [OpenOCD] Debug: 3326 10644 riscv-013.c:1561 register_read_direct(): [esp32c6] a0 = 0x400000 Debug: 3327 10644 riscv.c:4831 riscv_get_register(): [esp32c6] Read a0: 0x400000 Debug: 3328 10644 riscv.c:5259 register_get(): [esp32c6] Read 0x00400000 from a0 (valid=1). Debug: 3329 10644 esp_riscv.c:733 esp_riscv_wait_algorithm(): Read mem params Debug: 3330 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore ra Debug: 3331 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x40801456 to ra (valid=0). Debug: 3332 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40801456 to ra (cacheable=true, valid=true, dirty=true) Debug: 3333 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore sp Debug: 3334 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x40804780 to sp (valid=0). Debug: 3335 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804780 to sp (cacheable=true, valid=true, dirty=true) Debug: 3336 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore gp Debug: 3337 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to gp (valid=0). Debug: 3338 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to gp (cacheable=true, valid=true, dirty=true) Debug: 3339 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tp Debug: 3340 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tp (valid=0). Debug: 3341 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tp (cacheable=true, valid=true, dirty=true) Debug: 3342 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t0 Debug: 3343 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x40027bd4 to t0 (valid=0). Debug: 3344 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40027bd4 to t0 (cacheable=true, valid=true, dirty=true) Debug: 3345 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t1 Debug: 3346 10644 riscv.c:5274 register_set(): [esp32c6] Write 0xffffffe0 to t1 (valid=0). Debug: 3347 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0xffffffe0 to t1 (cacheable=true, valid=true, dirty=true) Debug: 3348 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t2 Debug: 3349 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t2 (valid=0). Debug: 3350 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t2 (cacheable=true, valid=true, dirty=true) Debug: 3351 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore fp Debug: 3352 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to fp (valid=0). Debug: 3353 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to fp (cacheable=true, valid=true, dirty=true) Debug: 3354 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s1 Debug: 3355 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s1 (valid=0). Debug: 3356 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s1 (cacheable=true, valid=true, dirty=true) Debug: 3357 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a0 Debug: 3358 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x20000000 to a0 (valid=1). Debug: 3359 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x20000000 to a0 (cacheable=true, valid=true, dirty=true) Debug: 3360 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a1 Debug: 3361 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x60002000 to a1 (valid=0). Debug: 3362 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x60002000 to a1 (cacheable=true, valid=true, dirty=true) Debug: 3363 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a2 Debug: 3364 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000010 to a2 (valid=0). Debug: 3365 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x10 to a2 (cacheable=true, valid=true, dirty=true) Debug: 3366 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a3 Debug: 3367 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00010000 to a3 (valid=0). Debug: 3368 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x10000 to a3 (cacheable=true, valid=true, dirty=true) Debug: 3369 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a4 Debug: 3370 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x408021e0 to a4 (valid=0). Debug: 3371 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x408021e0 to a4 (cacheable=true, valid=true, dirty=true) Debug: 3372 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a5 Debug: 3373 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000004 to a5 (valid=0). Debug: 3374 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4 to a5 (cacheable=true, valid=true, dirty=true) Debug: 3375 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a6 Debug: 3376 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000008 to a6 (valid=0). Debug: 3377 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x8 to a6 (cacheable=true, valid=true, dirty=true) Debug: 3378 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a7 Debug: 3379 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x80000000 to a7 (valid=0). Debug: 3380 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x80000000 to a7 (cacheable=true, valid=true, dirty=true) Debug: 3381 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s2 Debug: 3382 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s2 (valid=0). Debug: 3383 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s2 (cacheable=true, valid=true, dirty=true) Debug: 3384 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s3 Debug: 3385 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s3 (valid=0). Debug: 3386 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s3 (cacheable=true, valid=true, dirty=true) Debug: 3387 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s4 Debug: 3388 10644 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s4 (valid=0). Debug: 3389 10644 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s4 (cacheable=true, valid=true, dirty=true) Debug: 3390 10644 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s5 Debug: 3391 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s5 (valid=0). Debug: 3392 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s5 (cacheable=true, valid=true, dirty=true) Debug: 3393 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s6 Debug: 3394 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s6 (valid=0). Debug: 3395 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s6 (cacheable=true, valid=true, dirty=true) Debug: 3396 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s7 Debug: 3397 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s7 (valid=0). Debug: 3398 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s7 (cacheable=true, valid=true, dirty=true) Debug: 3399 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s8 Debug: 3400 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s8 (valid=0). Debug: 3401 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s8 (cacheable=true, valid=true, dirty=true) Debug: 3402 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s9 Debug: 3403 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s9 (valid=0). Debug: 3404 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s9 (cacheable=true, valid=true, dirty=true) Debug: 3405 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s10 Debug: 3406 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s10 (valid=0). Debug: 3407 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s10 (cacheable=true, valid=true, dirty=true) Debug: 3408 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s11 Debug: 3409 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s11 (valid=0). Debug: 3410 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s11 (cacheable=true, valid=true, dirty=true) Debug: 3411 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t3 Debug: 3412 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t3 (valid=0). Debug: 3413 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t3 (cacheable=true, valid=true, dirty=true) Debug: 3414 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t4 Debug: 3415 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t4 (valid=0). Debug: 3416 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t4 (cacheable=true, valid=true, dirty=true) Debug: 3417 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t5 Debug: 3418 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t5 (valid=0). Debug: 3419 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t5 (cacheable=true, valid=true, dirty=true) Debug: 3420 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t6 Debug: 3421 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t6 (valid=0). Debug: 3422 10645 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t6 (cacheable=true, valid=true, dirty=true) Debug: 3423 10645 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pc Debug: 3424 10645 riscv.c:5274 register_set(): [esp32c6] Write 0x40000000 to pc (valid=0). Debug: 3425 10645 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pc <- 0x40000000 (cacheable=false, valid=false, dirty=false) Debug: 3426 10645 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40000000 to register pc Debug: 3427 10645 riscv-013.c:4562 riscv013_set_register(): [esp32c6] writing PC to DPC: 0x40000000 Debug: 3428 10645 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40000000 to dpc Debug: 3429 10647 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 3430 10712 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40000000 Debug: 3431 10712 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40000000 to pc (cacheable=false, valid=false, dirty=false) Debug: 3432 10712 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mstatus Debug: 3433 10712 riscv.c:5274 register_set(): [esp32c6] Write 0x00201800 to mstatus (valid=0). Debug: 3434 10712 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mstatus <- 0x201800 (cacheable=false, valid=false, dirty=false) Debug: 3435 10712 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x201800 to register mstatus Debug: 3436 10712 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x201800 to mstatus Debug: 3437 10718 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 3438 10724 riscv-013.c:1532 register_write_direct(): [esp32c6] mstatus <- 0x201800 Debug: 3439 10724 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x201800 to mstatus (cacheable=false, valid=false, dirty=false) Debug: 3440 10724 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore misa Debug: 3441 10724 riscv.c:5274 register_set(): [esp32c6] Write 0x40903105 to misa (valid=0). Debug: 3442 10724 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: misa <- 0x40903105 (cacheable=false, valid=false, dirty=false) Debug: 3443 10724 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40903105 to register misa Debug: 3444 10724 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40903105 to misa Debug: 3445 10727 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301 Debug: 3446 10730 riscv-013.c:1532 register_write_direct(): [esp32c6] misa <- 0x40903105 Debug: 3447 10730 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40903105 to misa (cacheable=false, valid=false, dirty=false) Debug: 3448 10730 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mtvec Debug: 3449 10730 riscv.c:5274 register_set(): [esp32c6] Write 0x00000001 to mtvec (valid=0). Debug: 3450 10730 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mtvec <- 0x1 (cacheable=false, valid=false, dirty=false) Debug: 3451 10730 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x1 to register csr773 Debug: 3452 10730 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x1 to csr773 Debug: 3453 10733 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305 Debug: 3454 10740 riscv-013.c:1532 register_write_direct(): [esp32c6] csr773 <- 0x1 Debug: 3455 10740 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x1 to mtvec (cacheable=false, valid=false, dirty=false) Debug: 3456 10740 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mscratch Debug: 3457 10740 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mscratch (valid=0). Debug: 3458 10740 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mscratch <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3459 10740 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr832 Debug: 3460 10740 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr832 Debug: 3461 10742 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340 [OpenOCD] Debug: 3462 10747 riscv-013.c:1532 register_write_direct(): [esp32c6] csr832 <- 0x0 Debug: 3463 10747 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mscratch (cacheable=false, valid=false, dirty=false) Debug: 3464 10747 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mepc Debug: 3465 10747 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mepc (valid=0). Debug: 3466 10747 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mepc <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3467 10747 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register mepc Debug: 3468 10747 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to mepc Debug: 3469 10760 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341 Debug: 3470 10766 riscv-013.c:1532 register_write_direct(): [esp32c6] mepc <- 0x0 Debug: 3471 10766 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mepc (cacheable=false, valid=false, dirty=false) Debug: 3472 10766 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mcause Debug: 3473 10766 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mcause (valid=0). Debug: 3474 10766 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mcause <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3475 10766 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register mcause Debug: 3476 10766 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to mcause Debug: 3477 10770 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342 Debug: 3478 10776 riscv-013.c:1532 register_write_direct(): [esp32c6] mcause <- 0x0 Debug: 3479 10776 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mcause (cacheable=false, valid=false, dirty=false) Debug: 3480 10776 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mtval Debug: 3481 10776 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mtval (valid=0). Debug: 3482 10776 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mtval <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3483 10776 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr835 Debug: 3484 10776 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr835 Debug: 3485 10780 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343 Debug: 3486 10786 riscv-013.c:1532 register_write_direct(): [esp32c6] csr835 <- 0x0 Debug: 3487 10786 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mtval (cacheable=false, valid=false, dirty=false) Debug: 3488 10786 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg0 Debug: 3489 10786 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg0 (valid=0). Debug: 3490 10786 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3491 10786 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr928 Debug: 3492 10786 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr928 Debug: 3493 10789 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0 Debug: 3494 10793 riscv-013.c:1532 register_write_direct(): [esp32c6] csr928 <- 0x0 Debug: 3495 10793 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg0 (cacheable=false, valid=false, dirty=false) Debug: 3496 10793 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg1 Debug: 3497 10793 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg1 (valid=0). Debug: 3498 10793 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3499 10793 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr929 Debug: 3500 10793 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr929 Debug: 3501 10795 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1 Debug: 3502 10799 riscv-013.c:1532 register_write_direct(): [esp32c6] csr929 <- 0x0 Debug: 3503 10799 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg1 (cacheable=false, valid=false, dirty=false) Debug: 3504 10799 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg2 Debug: 3505 10799 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg2 (valid=0). Debug: 3506 10799 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3507 10799 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr930 Debug: 3508 10799 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr930 Debug: 3509 10803 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2 Debug: 3510 10807 riscv-013.c:1532 register_write_direct(): [esp32c6] csr930 <- 0x0 Debug: 3511 10807 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg2 (cacheable=false, valid=false, dirty=false) Debug: 3512 10807 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg3 Debug: 3513 10807 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg3 (valid=0). Debug: 3514 10807 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3515 10807 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr931 Debug: 3516 10807 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr931 [OpenOCD] Debug: 3517 10810 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3 Debug: 3518 10814 riscv-013.c:1532 register_write_direct(): [esp32c6] csr931 <- 0x0 Debug: 3519 10814 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg3 (cacheable=false, valid=false, dirty=false) Debug: 3520 10814 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr0 Debug: 3521 10814 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr0 (valid=0). Debug: 3522 10814 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3523 10814 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr944 Debug: 3524 10814 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr944 Debug: 3525 10818 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0 Debug: 3526 10827 riscv-013.c:1532 register_write_direct(): [esp32c6] csr944 <- 0x0 Debug: 3527 10827 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr0 (cacheable=false, valid=false, dirty=false) Debug: 3528 10827 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr1 Debug: 3529 10827 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr1 (valid=0). Debug: 3530 10827 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3531 10827 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr945 Debug: 3532 10827 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr945 Debug: 3533 10831 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1 Debug: 3534 10839 riscv-013.c:1532 register_write_direct(): [esp32c6] csr945 <- 0x0 Debug: 3535 10839 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr1 (cacheable=false, valid=false, dirty=false) Debug: 3536 10839 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr2 Debug: 3537 10839 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr2 (valid=0). Debug: 3538 10839 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3539 10839 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr946 Debug: 3540 10839 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr946 Debug: 3541 10844 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2 Debug: 3542 10850 riscv-013.c:1532 register_write_direct(): [esp32c6] csr946 <- 0x0 Debug: 3543 10850 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr2 (cacheable=false, valid=false, dirty=false) Debug: 3544 10850 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr3 Debug: 3545 10850 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr3 (valid=0). Debug: 3546 10850 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3547 10850 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr947 Debug: 3548 10850 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr947 Debug: 3549 10856 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3 Debug: 3550 10860 riscv-013.c:1532 register_write_direct(): [esp32c6] csr947 <- 0x0 Debug: 3551 10860 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr3 (cacheable=false, valid=false, dirty=false) Debug: 3552 10860 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr4 Debug: 3553 10860 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr4 (valid=0). Debug: 3554 10860 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3555 10860 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr948 Debug: 3556 10860 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr948 Debug: 3557 10863 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4 Debug: 3558 10867 riscv-013.c:1532 register_write_direct(): [esp32c6] csr948 <- 0x0 Debug: 3559 10867 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr4 (cacheable=false, valid=false, dirty=false) Debug: 3560 10867 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr5 Debug: 3561 10867 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr5 (valid=0). Debug: 3562 10867 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3563 10867 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr949 Debug: 3564 10867 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr949 Debug: 3565 10870 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5 [OpenOCD] Debug: 3566 10875 riscv-013.c:1532 register_write_direct(): [esp32c6] csr949 <- 0x0 Debug: 3567 10875 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr5 (cacheable=false, valid=false, dirty=false) Debug: 3568 10875 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr6 Debug: 3569 10875 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr6 (valid=0). Debug: 3570 10875 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3571 10875 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr950 Debug: 3572 10875 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr950 Debug: 3573 10877 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6 Debug: 3574 10881 riscv-013.c:1532 register_write_direct(): [esp32c6] csr950 <- 0x0 Debug: 3575 10881 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr6 (cacheable=false, valid=false, dirty=false) Debug: 3576 10881 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr7 Debug: 3577 10881 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr7 (valid=0). Debug: 3578 10881 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3579 10881 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr951 Debug: 3580 10881 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr951 Debug: 3581 10886 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7 Debug: 3582 10892 riscv-013.c:1532 register_write_direct(): [esp32c6] csr951 <- 0x0 Debug: 3583 10892 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr7 (cacheable=false, valid=false, dirty=false) Debug: 3584 10892 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr8 Debug: 3585 10892 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr8 (valid=0). Debug: 3586 10892 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3587 10892 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr952 Debug: 3588 10892 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr952 Debug: 3589 10896 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8 Debug: 3590 10901 riscv-013.c:1532 register_write_direct(): [esp32c6] csr952 <- 0x0 Debug: 3591 10901 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr8 (cacheable=false, valid=false, dirty=false) Debug: 3592 10901 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr9 Debug: 3593 10901 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr9 (valid=0). Debug: 3594 10901 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3595 10901 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr953 Debug: 3596 10901 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr953 Debug: 3597 10905 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9 Debug: 3598 10909 riscv-013.c:1532 register_write_direct(): [esp32c6] csr953 <- 0x0 Debug: 3599 10909 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr9 (cacheable=false, valid=false, dirty=false) Debug: 3600 10909 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr10 Debug: 3601 10909 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr10 (valid=0). Debug: 3602 10909 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3603 10909 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr954 Debug: 3604 10909 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr954 Debug: 3605 10911 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba Debug: 3606 10915 riscv-013.c:1532 register_write_direct(): [esp32c6] csr954 <- 0x0 Debug: 3607 10915 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr10 (cacheable=false, valid=false, dirty=false) Debug: 3608 10915 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr11 Debug: 3609 10915 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr11 (valid=0). Debug: 3610 10915 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3611 10915 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr955 Debug: 3612 10915 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr955 Debug: 3613 10918 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb Debug: 3614 10921 riscv-013.c:1532 register_write_direct(): [esp32c6] csr955 <- 0x0 Debug: 3615 10921 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr11 (cacheable=false, valid=false, dirty=false) Debug: 3616 10921 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr12 Debug: 3617 10921 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr12 (valid=0). Debug: 3618 10921 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3619 10921 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr956 Debug: 3620 10921 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr956 Debug: 3621 10923 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc Debug: 3622 10927 riscv-013.c:1532 register_write_direct(): [esp32c6] csr956 <- 0x0 Debug: 3623 10927 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr12 (cacheable=false, valid=false, dirty=false) Debug: 3624 10927 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr13 Debug: 3625 10927 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr13 (valid=0). Debug: 3626 10927 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3627 10927 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr957 Debug: 3628 10927 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr957 Debug: 3629 10930 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd [OpenOCD] Debug: 3630 10936 riscv-013.c:1532 register_write_direct(): [esp32c6] csr957 <- 0x0 Debug: 3631 10936 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr13 (cacheable=false, valid=false, dirty=false) Debug: 3632 10936 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr14 Debug: 3633 10936 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr14 (valid=0). Debug: 3634 10936 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3635 10936 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr958 Debug: 3636 10936 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr958 Debug: 3637 10939 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be Debug: 3638 10950 riscv-013.c:1532 register_write_direct(): [esp32c6] csr958 <- 0x0 Debug: 3639 10950 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr14 (cacheable=false, valid=false, dirty=false) Debug: 3640 10950 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr15 Debug: 3641 10950 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr15 (valid=0). Debug: 3642 10950 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3643 10950 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr959 Debug: 3644 10950 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr959 Debug: 3645 10955 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf Debug: 3646 10966 riscv-013.c:1532 register_write_direct(): [esp32c6] csr959 <- 0x0 Debug: 3647 10966 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr15 (cacheable=false, valid=false, dirty=false) Debug: 3648 10966 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tselect Debug: 3649 10966 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tselect (valid=0). Debug: 3650 10966 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3651 10966 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tselect Debug: 3652 10966 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tselect Debug: 3653 10971 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 3654 10977 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x0 Debug: 3655 10977 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tselect (cacheable=false, valid=false, dirty=false) Debug: 3656 10977 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tdata1 Debug: 3657 10977 riscv.c:5274 register_set(): [esp32c6] Write 0x23e00000 to tdata1 (valid=0). Debug: 3658 10977 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tdata1 <- 0x23e00000 (cacheable=false, valid=false, dirty=false) Debug: 3659 10977 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x23e00000 to register tdata1 Debug: 3660 10977 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x23e00000 to tdata1 Debug: 3661 10984 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1 Debug: 3662 10990 riscv-013.c:1532 register_write_direct(): [esp32c6] tdata1 <- 0x23e00000 Debug: 3663 10990 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x23e00000 to tdata1 (cacheable=false, valid=false, dirty=false) Debug: 3664 10990 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tdata2 Debug: 3665 10990 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tdata2 (valid=0). Debug: 3666 10990 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tdata2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3667 10990 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tdata2 Debug: 3668 10990 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tdata2 Debug: 3669 10992 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2 Debug: 3670 10996 riscv-013.c:1532 register_write_direct(): [esp32c6] tdata2 <- 0x0 Debug: 3671 10996 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tdata2 (cacheable=false, valid=false, dirty=false) Debug: 3672 10996 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tcontrol Debug: 3673 10996 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tcontrol (valid=0). Debug: 3674 10996 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tcontrol <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3675 10996 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr1957 Debug: 3676 10996 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr1957 Debug: 3677 10998 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5 Debug: 3678 11007 riscv-013.c:1532 register_write_direct(): [esp32c6] csr1957 <- 0x0 Debug: 3679 11007 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tcontrol (cacheable=false, valid=false, dirty=false) Debug: 3680 11007 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dcsr Debug: 3681 11007 riscv.c:5274 register_set(): [esp32c6] Write 0x400090c3 to dcsr (valid=0). Debug: 3682 11007 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dcsr <- 0x400090c3 (cacheable=false, valid=false, dirty=false) Debug: 3683 11007 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x400090c3 to register dcsr Debug: 3684 11007 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x400090c3 to dcsr [OpenOCD] Debug: 3685 11011 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 3686 11018 riscv-013.c:1532 register_write_direct(): [esp32c6] dcsr <- 0x400090c3 Debug: 3687 11018 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x400090c3 to dcsr (cacheable=false, valid=false, dirty=false) Debug: 3688 11018 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dpc Debug: 3689 11018 riscv.c:5274 register_set(): [esp32c6] Write 0x40000000 to dpc (valid=0). Debug: 3690 11018 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40000000 to dpc (cacheable=true, valid=true, dirty=true) Debug: 3691 11018 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dscratch0 Debug: 3692 11018 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to dscratch0 (valid=0). Debug: 3693 11018 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dscratch0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3694 11018 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register dscratch0 Debug: 3695 11018 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to dscratch0 Debug: 3696 11023 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2 Debug: 3697 11029 riscv-013.c:1532 register_write_direct(): [esp32c6] dscratch0 <- 0x0 Debug: 3698 11029 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to dscratch0 (cacheable=false, valid=false, dirty=false) Debug: 3699 11029 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dscratch1 Debug: 3700 11029 riscv.c:5274 register_set(): [esp32c6] Write 0x20000000 to dscratch1 (valid=0). Debug: 3701 11029 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dscratch1 <- 0x20000000 (cacheable=false, valid=false, dirty=false) Debug: 3702 11029 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x20000000 to register csr1971 Debug: 3703 11029 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x20000000 to csr1971 Debug: 3704 11033 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3 Debug: 3705 11038 riscv-013.c:1532 register_write_direct(): [esp32c6] csr1971 <- 0x20000000 Debug: 3706 11038 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x20000000 to dscratch1 (cacheable=false, valid=false, dirty=false) Debug: 3707 11038 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpcer Debug: 3708 11038 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_mpcer (valid=0). Debug: 3709 11038 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpcer <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3710 11038 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2016 Debug: 3711 11038 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2016 Debug: 3712 11042 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e0 Debug: 3713 11048 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2016 <- 0x0 Debug: 3714 11048 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_mpcer (cacheable=false, valid=false, dirty=false) Debug: 3715 11048 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpcmr Debug: 3716 11048 riscv.c:5274 register_set(): [esp32c6] Write 0x00000003 to csr_mpcmr (valid=0). Debug: 3717 11048 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpcmr <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 3718 11048 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register csr2017 Debug: 3719 11048 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to csr2017 Debug: 3720 11052 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e1 Debug: 3721 11057 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2017 <- 0x3 Debug: 3722 11057 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to csr_mpcmr (cacheable=false, valid=false, dirty=false) Debug: 3723 11057 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpccr Debug: 3724 11057 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_mpccr (valid=0). Debug: 3725 11057 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpccr <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3726 11057 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2018 Debug: 3727 11057 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2018 Debug: 3728 11060 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e2 Debug: 3729 11064 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2018 <- 0x0 Debug: 3730 11064 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_mpccr (cacheable=false, valid=false, dirty=false) Debug: 3731 11064 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_oen Debug: 3732 11064 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_oen (valid=0). Debug: 3733 11064 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_oen <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3734 11064 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2051 Debug: 3735 11064 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2051 Debug: 3736 11067 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230803; access register, size=32, postexec=0, transfer=1, write=1, regno=0x803 Debug: 3737 11072 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2051 <- 0x0 Debug: 3738 11072 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_oen (cacheable=false, valid=false, dirty=false) Debug: 3739 11072 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_in Debug: 3740 11072 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_in (valid=0). Debug: 3741 11072 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_in <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3742 11072 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2052 Debug: 3743 11072 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2052 [OpenOCD] Debug: 3744 11075 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230804; access register, size=32, postexec=0, transfer=1, write=1, regno=0x804 Debug: 3745 11085 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2052 <- 0x0 Debug: 3746 11085 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_in (cacheable=false, valid=false, dirty=false) Debug: 3747 11085 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_out Debug: 3748 11085 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_out (valid=0). Debug: 3749 11085 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_out <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3750 11085 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2053 Debug: 3751 11085 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2053 Debug: 3752 11089 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230805; access register, size=32, postexec=0, transfer=1, write=1, regno=0x805 Debug: 3753 11139 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2053 <- 0x0 Debug: 3754 11139 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_out (cacheable=false, valid=false, dirty=false) Debug: 3755 11139 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg0 Debug: 3756 11139 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg0 (valid=0). Debug: 3757 11139 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3758 11139 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3008 Debug: 3759 11139 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3008 Debug: 3760 11143 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc0; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc0 Debug: 3761 11176 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3008 <- 0x0 Debug: 3762 11176 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg0 (cacheable=false, valid=false, dirty=false) Debug: 3763 11176 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg1 Debug: 3764 11176 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg1 (valid=0). Debug: 3765 11176 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3766 11176 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3009 Debug: 3767 11176 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3009 [OpenOCD] Debug: 3768 11180 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc1; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc1 Debug: 3769 11200 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3009 <- 0x0 Debug: 3770 11200 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg1 (cacheable=false, valid=false, dirty=false) Debug: 3771 11200 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg2 Debug: 3772 11200 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg2 (valid=0). Debug: 3773 11200 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3774 11200 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3010 Debug: 3775 11200 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3010 Debug: 3776 11205 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc2; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc2 Debug: 3777 11217 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3010 <- 0x0 Debug: 3778 11217 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg2 (cacheable=false, valid=false, dirty=false) Debug: 3779 11217 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg3 Debug: 3780 11217 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg3 (valid=0). Debug: 3781 11217 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3782 11217 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3011 Debug: 3783 11217 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3011 Debug: 3784 11223 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc3; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc3 Debug: 3785 11230 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3011 <- 0x0 Debug: 3786 11230 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg3 (cacheable=false, valid=false, dirty=false) Debug: 3787 11230 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg4 Debug: 3788 11230 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg4 (valid=0). Debug: 3789 11230 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3790 11230 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3012 Debug: 3791 11230 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3012 Debug: 3792 11236 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc4; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc4 Debug: 3793 11245 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3012 <- 0x0 Debug: 3794 11245 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg4 (cacheable=false, valid=false, dirty=false) Debug: 3795 11245 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg5 Debug: 3796 11245 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg5 (valid=0). Debug: 3797 11245 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3798 11245 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3013 Debug: 3799 11245 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3013 Debug: 3800 11247 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc5; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc5 Debug: 3801 11252 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3013 <- 0x0 Debug: 3802 11252 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg5 (cacheable=false, valid=false, dirty=false) Debug: 3803 11252 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg6 Debug: 3804 11252 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg6 (valid=0). Debug: 3805 11252 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3806 11252 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3014 Debug: 3807 11252 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3014 Debug: 3808 11255 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc6; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc6 [OpenOCD] Debug: 3809 11259 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3014 <- 0x0 Debug: 3810 11259 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg6 (cacheable=false, valid=false, dirty=false) Debug: 3811 11259 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg7 Debug: 3812 11259 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg7 (valid=0). Debug: 3813 11259 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3814 11259 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3015 Debug: 3815 11259 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3015 Debug: 3816 11262 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc7; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc7 Debug: 3817 11269 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3015 <- 0x0 Debug: 3818 11269 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg7 (cacheable=false, valid=false, dirty=false) Debug: 3819 11269 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg8 Debug: 3820 11269 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg8 (valid=0). Debug: 3821 11269 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3822 11269 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3016 Debug: 3823 11269 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3016 Debug: 3824 11275 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc8; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc8 Debug: 3825 11281 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3016 <- 0x0 Debug: 3826 11281 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg8 (cacheable=false, valid=false, dirty=false) Debug: 3827 11281 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg9 Debug: 3828 11281 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg9 (valid=0). Debug: 3829 11281 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3830 11281 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3017 Debug: 3831 11281 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3017 Debug: 3832 11285 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc9; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc9 Debug: 3833 11290 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3017 <- 0x0 Debug: 3834 11290 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg9 (cacheable=false, valid=false, dirty=false) Debug: 3835 11290 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg10 Debug: 3836 11290 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg10 (valid=0). Debug: 3837 11290 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3838 11290 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3018 Debug: 3839 11290 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3018 Debug: 3840 11293 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bca; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbca Debug: 3841 11298 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3018 <- 0x0 Debug: 3842 11298 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg10 (cacheable=false, valid=false, dirty=false) Debug: 3843 11298 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg11 Debug: 3844 11298 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg11 (valid=0). Debug: 3845 11298 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3846 11298 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3019 Debug: 3847 11298 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3019 Debug: 3848 11301 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcb; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcb Debug: 3849 11314 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3019 <- 0x0 Debug: 3850 11314 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg11 (cacheable=false, valid=false, dirty=false) Debug: 3851 11314 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg12 Debug: 3852 11314 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg12 (valid=0). Debug: 3853 11314 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3854 11314 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3020 Debug: 3855 11314 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3020 [OpenOCD] Debug: 3856 11354 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcc; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcc Debug: 3857 11365 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3020 <- 0x0 Debug: 3858 11365 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg12 (cacheable=false, valid=false, dirty=false) Debug: 3859 11365 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg13 Debug: 3860 11365 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg13 (valid=0). Debug: 3861 11365 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3862 11365 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3021 Debug: 3863 11365 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3021 Debug: 3864 11370 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcd; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcd Debug: 3865 11377 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3021 <- 0x0 Debug: 3866 11377 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg13 (cacheable=false, valid=false, dirty=false) Debug: 3867 11377 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg14 Debug: 3868 11377 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg14 (valid=0). Debug: 3869 11377 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3870 11377 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3022 Debug: 3871 11377 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3022 Debug: 3872 11381 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bce; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbce Debug: 3873 11396 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3022 <- 0x0 Debug: 3874 11396 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg14 (cacheable=false, valid=false, dirty=false) Debug: 3875 11396 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg15 Debug: 3876 11396 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg15 (valid=0). Debug: 3877 11396 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3878 11396 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3023 Debug: 3879 11396 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3023 Debug: 3880 11401 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcf; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcf Debug: 3881 11406 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3023 <- 0x0 Debug: 3882 11406 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg15 (cacheable=false, valid=false, dirty=false) Debug: 3883 11406 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr0 Debug: 3884 11406 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr0 (valid=0). Debug: 3885 11406 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3886 11406 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3024 Debug: 3887 11406 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3024 Debug: 3888 11409 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd0; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd0 Debug: 3889 11412 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3024 <- 0x0 Debug: 3890 11412 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr0 (cacheable=false, valid=false, dirty=false) Debug: 3891 11412 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr1 Debug: 3892 11412 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr1 (valid=0). Debug: 3893 11412 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3894 11412 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3025 Debug: 3895 11412 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3025 Debug: 3896 11415 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd1; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd1 Debug: 3897 11419 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3025 <- 0x0 Debug: 3898 11419 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr1 (cacheable=false, valid=false, dirty=false) Debug: 3899 11419 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr2 Debug: 3900 11419 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr2 (valid=0). Debug: 3901 11419 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3902 11419 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3026 Debug: 3903 11419 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3026 [OpenOCD] Debug: 3904 11422 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd2; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd2 Debug: 3905 11426 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3026 <- 0x0 Debug: 3906 11426 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr2 (cacheable=false, valid=false, dirty=false) Debug: 3907 11426 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr3 Debug: 3908 11426 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr3 (valid=0). Debug: 3909 11426 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3910 11426 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3027 Debug: 3911 11426 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3027 Debug: 3912 11430 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd3; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd3 Debug: 3913 11437 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3027 <- 0x0 Debug: 3914 11437 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr3 (cacheable=false, valid=false, dirty=false) Debug: 3915 11437 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr4 Debug: 3916 11437 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr4 (valid=0). Debug: 3917 11437 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3918 11437 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3028 Debug: 3919 11437 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3028 Debug: 3920 11441 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd4; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd4 Debug: 3921 11446 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3028 <- 0x0 Debug: 3922 11446 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr4 (cacheable=false, valid=false, dirty=false) Debug: 3923 11446 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr5 Debug: 3924 11446 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr5 (valid=0). Debug: 3925 11446 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3926 11446 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3029 Debug: 3927 11446 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3029 Debug: 3928 11450 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd5; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd5 Debug: 3929 11456 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3029 <- 0x0 Debug: 3930 11456 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr5 (cacheable=false, valid=false, dirty=false) Debug: 3931 11456 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr6 Debug: 3932 11456 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr6 (valid=0). Debug: 3933 11456 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3934 11456 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3030 Debug: 3935 11456 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3030 Debug: 3936 11459 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd6; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd6 Debug: 3937 11463 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3030 <- 0x0 Debug: 3938 11463 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr6 (cacheable=false, valid=false, dirty=false) Debug: 3939 11463 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr7 Debug: 3940 11463 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr7 (valid=0). Debug: 3941 11463 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3942 11463 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3031 Debug: 3943 11463 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3031 Debug: 3944 11466 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd7; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd7 Debug: 3945 11470 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3031 <- 0x0 Debug: 3946 11470 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr7 (cacheable=false, valid=false, dirty=false) Debug: 3947 11470 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr8 Debug: 3948 11470 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr8 (valid=0). Debug: 3949 11470 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3950 11470 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3032 Debug: 3951 11470 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3032 Debug: 3952 11473 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd8; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd8 [OpenOCD] Debug: 3953 11477 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3032 <- 0x0 Debug: 3954 11477 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr8 (cacheable=false, valid=false, dirty=false) Debug: 3955 11477 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr9 Debug: 3956 11477 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr9 (valid=0). Debug: 3957 11477 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3958 11477 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3033 Debug: 3959 11477 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3033 Debug: 3960 11480 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd9; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd9 Debug: 3961 11486 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3033 <- 0x0 Debug: 3962 11486 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr9 (cacheable=false, valid=false, dirty=false) Debug: 3963 11486 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr10 Debug: 3964 11486 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr10 (valid=0). Debug: 3965 11486 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3966 11486 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3034 Debug: 3967 11486 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3034 Debug: 3968 11489 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bda; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbda Debug: 3969 11493 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3034 <- 0x0 Debug: 3970 11493 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr10 (cacheable=false, valid=false, dirty=false) Debug: 3971 11493 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr11 Debug: 3972 11493 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr11 (valid=0). Debug: 3973 11493 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3974 11493 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3035 Debug: 3975 11493 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3035 Debug: 3976 11497 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdb; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdb Debug: 3977 11504 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3035 <- 0x0 Debug: 3978 11504 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr11 (cacheable=false, valid=false, dirty=false) Debug: 3979 11504 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr12 Debug: 3980 11504 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr12 (valid=0). Debug: 3981 11504 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3982 11504 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3036 Debug: 3983 11504 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3036 Debug: 3984 11507 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdc; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdc Debug: 3985 11511 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3036 <- 0x0 Debug: 3986 11512 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr12 (cacheable=false, valid=false, dirty=false) Debug: 3987 11512 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr13 Debug: 3988 11512 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr13 (valid=0). Debug: 3989 11512 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3990 11512 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3037 Debug: 3991 11512 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3037 Debug: 3992 11515 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdd; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdd Debug: 3993 11523 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3037 <- 0x0 Debug: 3994 11523 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr13 (cacheable=false, valid=false, dirty=false) Debug: 3995 11523 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr14 Debug: 3996 11523 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr14 (valid=0). Debug: 3997 11523 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 3998 11523 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3038 Debug: 3999 11523 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3038 Debug: 4000 11529 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bde; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbde Debug: 4001 11534 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3038 <- 0x0 Debug: 4002 11534 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr14 (cacheable=false, valid=false, dirty=false) Debug: 4003 11534 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr15 Debug: 4004 11534 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr15 (valid=0). Debug: 4005 11534 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 4006 11534 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3039 Debug: 4007 11534 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3039 Debug: 4008 11537 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdf; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdf [OpenOCD] Debug: 4009 11543 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3039 <- 0x0 Debug: 4010 11543 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr15 (cacheable=false, valid=false, dirty=false) Debug: 4011 11543 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore hpmcounter16 Debug: 4012 11543 riscv.c:5274 register_set(): [esp32c6] Write 0x00000003 to hpmcounter16 (valid=0). Debug: 4013 11543 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: hpmcounter16 <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 4014 11543 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register csr3088 Debug: 4015 11543 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to csr3088 Debug: 4016 11546 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10 Debug: 4017 11555 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3088 <- 0x3 Debug: 4018 11555 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to hpmcounter16 (cacheable=false, valid=false, dirty=false) Debug: 4019 11555 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore priv Debug: 4020 11555 riscv.c:5274 register_set(): [esp32c6] Write 0x03 to priv (valid=0). Debug: 4021 11555 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: priv <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 4022 11555 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register priv Debug: 4023 11555 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 4024 11555 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 4025 11571 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 4026 11571 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x400090c3 to dcsr Debug: 4027 11579 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 4028 11590 riscv-013.c:1532 register_write_direct(): [esp32c6] dcsr <- 0x400090c3 Debug: 4029 11590 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to priv (cacheable=false, valid=false, dirty=false) Debug: 4030 11590 riscv.c:1575 riscv_flush_registers(): [esp32c6] dpc is dirty; write back 0x40000000 Debug: 4031 11590 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40000000 to register dpc Debug: 4032 11590 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40000000 to dpc Debug: 4033 11599 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 4034 11607 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40000000 Debug: 4035 11607 riscv.c:1575 riscv_flush_registers(): [esp32c6] t6 is dirty; write back 0x0 Debug: 4036 11607 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t6 Debug: 4037 11607 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t6 Debug: 4038 11611 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f Debug: 4039 11614 riscv-013.c:1532 register_write_direct(): [esp32c6] t6 <- 0x0 Debug: 4040 11614 riscv.c:1575 riscv_flush_registers(): [esp32c6] t5 is dirty; write back 0x0 Debug: 4041 11614 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t5 Debug: 4042 11614 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t5 Debug: 4043 11617 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e Debug: 4044 11621 riscv-013.c:1532 register_write_direct(): [esp32c6] t5 <- 0x0 Debug: 4045 11621 riscv.c:1575 riscv_flush_registers(): [esp32c6] t4 is dirty; write back 0x0 Debug: 4046 11621 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t4 Debug: 4047 11621 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t4 Debug: 4048 11624 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d [OpenOCD] Debug: 4049 11628 riscv-013.c:1532 register_write_direct(): [esp32c6] t4 <- 0x0 Debug: 4050 11628 riscv.c:1575 riscv_flush_registers(): [esp32c6] t3 is dirty; write back 0x0 Debug: 4051 11628 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t3 Debug: 4052 11628 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t3 Debug: 4053 11631 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c Debug: 4054 11636 riscv-013.c:1532 register_write_direct(): [esp32c6] t3 <- 0x0 Debug: 4055 11636 riscv.c:1575 riscv_flush_registers(): [esp32c6] s11 is dirty; write back 0x0 Debug: 4056 11636 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s11 Debug: 4057 11636 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s11 Debug: 4058 11640 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b Debug: 4059 11645 riscv-013.c:1532 register_write_direct(): [esp32c6] s11 <- 0x0 Debug: 4060 11645 riscv.c:1575 riscv_flush_registers(): [esp32c6] s10 is dirty; write back 0x0 Debug: 4061 11645 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s10 Debug: 4062 11645 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s10 Debug: 4063 11648 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a Debug: 4064 11661 riscv-013.c:1532 register_write_direct(): [esp32c6] s10 <- 0x0 Debug: 4065 11661 riscv.c:1575 riscv_flush_registers(): [esp32c6] s9 is dirty; write back 0x0 Debug: 4066 11661 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s9 Debug: 4067 11661 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s9 Debug: 4068 11666 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019 Debug: 4069 11681 riscv-013.c:1532 register_write_direct(): [esp32c6] s9 <- 0x0 Debug: 4070 11681 riscv.c:1575 riscv_flush_registers(): [esp32c6] s8 is dirty; write back 0x0 Debug: 4071 11681 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s8 Debug: 4072 11681 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s8 Debug: 4073 11698 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018 [OpenOCD] Debug: 4074 11712 riscv-013.c:1532 register_write_direct(): [esp32c6] s8 <- 0x0 Debug: 4075 11712 riscv.c:1575 riscv_flush_registers(): [esp32c6] s7 is dirty; write back 0x0 Debug: 4076 11712 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s7 Debug: 4077 11712 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s7 Debug: 4078 11716 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017 Debug: 4079 11743 riscv-013.c:1532 register_write_direct(): [esp32c6] s7 <- 0x0 Debug: 4080 11743 riscv.c:1575 riscv_flush_registers(): [esp32c6] s6 is dirty; write back 0x0 Debug: 4081 11743 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s6 Debug: 4082 11743 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s6 Debug: 4083 11749 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016 Debug: 4084 11758 riscv-013.c:1532 register_write_direct(): [esp32c6] s6 <- 0x0 Debug: 4085 11758 riscv.c:1575 riscv_flush_registers(): [esp32c6] s5 is dirty; write back 0x0 Debug: 4086 11758 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s5 Debug: 4087 11758 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s5 Debug: 4088 11762 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015 Debug: 4089 11770 riscv-013.c:1532 register_write_direct(): [esp32c6] s5 <- 0x0 Debug: 4090 11770 riscv.c:1575 riscv_flush_registers(): [esp32c6] s4 is dirty; write back 0x0 Debug: 4091 11770 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s4 Debug: 4092 11770 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s4 Debug: 4093 11774 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014 Debug: 4094 11780 riscv-013.c:1532 register_write_direct(): [esp32c6] s4 <- 0x0 Debug: 4095 11780 riscv.c:1575 riscv_flush_registers(): [esp32c6] s3 is dirty; write back 0x0 Debug: 4096 11780 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s3 Debug: 4097 11780 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s3 Debug: 4098 11783 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013 Debug: 4099 11788 riscv-013.c:1532 register_write_direct(): [esp32c6] s3 <- 0x0 Debug: 4100 11788 riscv.c:1575 riscv_flush_registers(): [esp32c6] s2 is dirty; write back 0x0 Debug: 4101 11788 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s2 Debug: 4102 11788 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s2 Debug: 4103 11790 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012 Debug: 4104 11797 riscv-013.c:1532 register_write_direct(): [esp32c6] s2 <- 0x0 Debug: 4105 11797 riscv.c:1575 riscv_flush_registers(): [esp32c6] a7 is dirty; write back 0x80000000 Debug: 4106 11797 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x80000000 to register a7 Debug: 4107 11797 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x80000000 to a7 [OpenOCD] Debug: 4108 11802 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 4109 11807 riscv-013.c:1532 register_write_direct(): [esp32c6] a7 <- 0x80000000 Debug: 4110 11807 riscv.c:1575 riscv_flush_registers(): [esp32c6] a6 is dirty; write back 0x8 Debug: 4111 11807 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x8 to register a6 Debug: 4112 11807 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x8 to a6 Debug: 4113 11812 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010 Debug: 4114 11818 riscv-013.c:1532 register_write_direct(): [esp32c6] a6 <- 0x8 Debug: 4115 11818 riscv.c:1575 riscv_flush_registers(): [esp32c6] a5 is dirty; write back 0x4 Debug: 4116 11818 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4 to register a5 Debug: 4117 11818 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4 to a5 Debug: 4118 11822 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f Debug: 4119 11830 riscv-013.c:1532 register_write_direct(): [esp32c6] a5 <- 0x4 Debug: 4120 11830 riscv.c:1575 riscv_flush_registers(): [esp32c6] a4 is dirty; write back 0x408021e0 Debug: 4121 11830 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x408021e0 to register a4 Debug: 4122 11830 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x408021e0 to a4 Debug: 4123 11835 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e Debug: 4124 11841 riscv-013.c:1532 register_write_direct(): [esp32c6] a4 <- 0x408021e0 Debug: 4125 11841 riscv.c:1575 riscv_flush_registers(): [esp32c6] a3 is dirty; write back 0x10000 Debug: 4126 11841 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x10000 to register a3 Debug: 4127 11841 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x10000 to a3 Debug: 4128 11844 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d Debug: 4129 11848 riscv-013.c:1532 register_write_direct(): [esp32c6] a3 <- 0x10000 Debug: 4130 11849 riscv.c:1575 riscv_flush_registers(): [esp32c6] a2 is dirty; write back 0x10 Debug: 4131 11849 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x10 to register a2 Debug: 4132 11849 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x10 to a2 Debug: 4133 11851 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 4134 11855 riscv-013.c:1532 register_write_direct(): [esp32c6] a2 <- 0x10 Debug: 4135 11855 riscv.c:1575 riscv_flush_registers(): [esp32c6] a1 is dirty; write back 0x60002000 Debug: 4136 11855 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x60002000 to register a1 Debug: 4137 11855 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x60002000 to a1 Debug: 4138 11858 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b [OpenOCD] Debug: 4139 11862 riscv-013.c:1532 register_write_direct(): [esp32c6] a1 <- 0x60002000 Debug: 4140 11862 riscv.c:1575 riscv_flush_registers(): [esp32c6] a0 is dirty; write back 0x20000000 Debug: 4141 11862 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x20000000 to register a0 Debug: 4142 11862 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x20000000 to a0 Debug: 4143 11865 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 4144 11870 riscv-013.c:1532 register_write_direct(): [esp32c6] a0 <- 0x20000000 Debug: 4145 11870 riscv.c:1575 riscv_flush_registers(): [esp32c6] s1 is dirty; write back 0x0 Debug: 4146 11870 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s1 Debug: 4147 11870 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s1 Debug: 4148 11874 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 4149 11879 riscv-013.c:1532 register_write_direct(): [esp32c6] s1 <- 0x0 Debug: 4150 11879 riscv.c:1575 riscv_flush_registers(): [esp32c6] fp is dirty; write back 0x0 Debug: 4151 11879 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s0 Debug: 4152 11879 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s0 Debug: 4153 11882 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 4154 11888 riscv-013.c:1532 register_write_direct(): [esp32c6] s0 <- 0x0 Debug: 4155 11888 riscv.c:1575 riscv_flush_registers(): [esp32c6] t2 is dirty; write back 0x0 Debug: 4156 11888 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t2 Debug: 4157 11888 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t2 Debug: 4158 11892 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007 Debug: 4159 11896 riscv-013.c:1532 register_write_direct(): [esp32c6] t2 <- 0x0 Debug: 4160 11896 riscv.c:1575 riscv_flush_registers(): [esp32c6] t1 is dirty; write back 0xffffffe0 Debug: 4161 11896 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0xffffffe0 to register t1 Debug: 4162 11896 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0xffffffe0 to t1 Debug: 4163 11900 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006 Debug: 4164 11906 riscv-013.c:1532 register_write_direct(): [esp32c6] t1 <- 0xffffffe0 Debug: 4165 11906 riscv.c:1575 riscv_flush_registers(): [esp32c6] t0 is dirty; write back 0x40027bd4 Debug: 4166 11906 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40027bd4 to register t0 Debug: 4167 11906 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40027bd4 to t0 Debug: 4168 11908 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005 Debug: 4169 11915 riscv-013.c:1532 register_write_direct(): [esp32c6] t0 <- 0x40027bd4 Debug: 4170 11915 riscv.c:1575 riscv_flush_registers(): [esp32c6] tp is dirty; write back 0x0 Debug: 4171 11915 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tp Debug: 4172 11915 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tp Debug: 4173 11919 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004 Debug: 4174 11925 riscv-013.c:1532 register_write_direct(): [esp32c6] tp <- 0x0 Debug: 4175 11925 riscv.c:1575 riscv_flush_registers(): [esp32c6] gp is dirty; write back 0x0 Debug: 4176 11925 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register gp Debug: 4177 11925 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to gp Debug: 4178 11928 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003 Debug: 4179 11934 riscv-013.c:1532 register_write_direct(): [esp32c6] gp <- 0x0 Debug: 4180 11934 riscv.c:1575 riscv_flush_registers(): [esp32c6] sp is dirty; write back 0x40804780 Debug: 4181 11934 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40804780 to register sp Debug: 4182 11934 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40804780 to sp Debug: 4183 11937 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 4184 11940 riscv-013.c:1532 register_write_direct(): [esp32c6] sp <- 0x40804780 Debug: 4185 11940 riscv.c:1575 riscv_flush_registers(): [esp32c6] ra is dirty; write back 0x40801456 Debug: 4186 11940 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40801456 to register ra Debug: 4187 11940 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40801456 to ra Debug: 4188 11943 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001 [OpenOCD] Debug: 4189 11955 riscv-013.c:1532 register_write_direct(): [esp32c6] ra <- 0x40801456 Debug: 4190 11955 esp_algorithm.c:130 algorithm_run_image(): Got algorithm RC 0x400000 Debug: 4191 11955 esp.c:259 esp_common_assist_debug_monitor_restore(): [esp32c6] value 0x00000000 addr 0x600c2000 Debug: 4192 11955 target.c:2686 target_write_u32(): address: 0x600c2000, value: 0x00000000 Debug: 4193 11966 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600c2000 Debug: 4194 11979 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4195 11979 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 4196 11993 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800000 Debug: 4197 12002 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800200 Debug: 4198 12010 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800400 [OpenOCD] Debug: 4199 12022 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800600 Debug: 4200 12080 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800800 Debug: 4201 12092 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800a00 Debug: 4202 12102 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800c00 [OpenOCD] Debug: 4203 12129 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800e00 Debug: 4204 12152 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801000 Debug: 4205 12164 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801200 Debug: 4206 12179 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801400 Debug: 4207 12187 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4208 12194 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801454 Debug: 4209 12200 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4210 12212 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804000 [OpenOCD] Debug: 4211 12220 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804200 Debug: 4212 12226 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4213 12234 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804280 Debug: 4214 12246 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804480 Debug: 4215 12257 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4216 12257 target.c:1938 print_wa_layout(): 0x40800000-0x40823fff (147456 bytes) Debug: 4217 12257 esp_flash.c:350 esp_algo_flash_get_size(): esp_algo_flash_get_size size 0x400000 Info : 4218 12257 esp_flash.c:1011 esp_algo_flash_probe(): Auto-detected flash bank 'esp32c6.flash' size 4096 KB Info : 4219 12257 esp_flash.c:1013 esp_algo_flash_probe(): Using flash bank 'esp32c6.flash' size 4096 KB Debug: 4220 12257 esp_flash.c:1030 esp_algo_flash_probe(): allocated 1024 sectors Debug: 4221 12257 esp_flash.c:961 esp_algo_flash_probe(): Flash size = 0 KB @ 0x00000000 'esp32c6' - 'halted' Debug: 4222 12257 esp_flash.c:245 esp_algo_flasher_algorithm_init(): base=00000000 set=0 Debug: 4223 12257 esp_algorithm.c:290 algorithm_load_func_image(): stub: base 0x0, start 0x4080110c, 2 sections Debug: 4224 12257 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 5202, flags 1 Debug: 4225 12257 target.c:2017 target_alloc_working_area_try(): MMU disabled, using physical address for working memory 0x40800000 Debug: 4226 12257 target.c:2070 target_alloc_working_area_try(): allocated new working area of 5204 bytes at address 0x40800000 [OpenOCD] Debug: 4227 14080 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 4228 14080 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 4229 14080 target.c:1938 print_wa_layout(): 0x40801454-0x40823fff (142252 bytes) Debug: 4230 14080 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800000 [OpenOCD] Debug: 4231 14085 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800000 Debug: 4232 14093 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800200 Debug: 4233 14101 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4234 14101 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800400 Debug: 4235 14106 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800400 Debug: 4236 14116 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800600 Debug: 4237 14124 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4238 14124 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800800 Debug: 4239 14130 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800800 [OpenOCD] Debug: 4240 14138 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800a00 Debug: 4241 14144 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4242 14144 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800c00 Debug: 4243 14149 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800c00 Debug: 4244 14157 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800e00 Debug: 4245 14165 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4246 14165 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40801000 Debug: 4247 14171 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801000 Debug: 4248 14179 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801200 Debug: 4249 14187 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4250 14187 target.c:2379 target_write_buffer(): writing buffer of 82 byte at 0x40801400 Debug: 4251 14192 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801400 Debug: 4252 14196 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4253 14196 esp_riscv.c:826 esp_riscv_write_memory(): Use 32-bit access: size: 2 count:1 start address: 0x40801450 Debug: 4254 14207 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. [OpenOCD] Debug: 4255 14213 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801450 Debug: 4256 14219 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4257 14219 target.c:2070 target_alloc_working_area_try(): allocated new working area of 4 bytes at address 0x40801454 Debug: 4258 14252 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 4259 14252 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 4260 14252 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 4261 14252 target.c:1938 print_wa_layout(): 0x40801458-0x40823fff (142248 bytes) Debug: 4262 14252 esp_algorithm.c:377 algorithm_load_func_image(): Write tramp to addr 0x40801454, sz 4 Debug: 4263 14252 target.c:2379 target_write_buffer(): writing buffer of 4 byte at 0x40801454 Debug: 4264 14259 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801454 Debug: 4265 14266 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4266 14266 esp_algorithm.c:388 algorithm_load_func_image(): Tramp mapped to addr 0x40801454 Debug: 4267 14266 target.c:2070 target_alloc_working_area_try(): allocated new working area of 11176 bytes at address 0x40801458 Debug: 4268 14266 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 4269 14266 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 4270 14266 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 4271 14266 target.c:1938 print_wa_layout(): 0x40804000-0x40823fff (131072 bytes) Debug: 4272 14266 esp_algorithm.c:413 algorithm_load_func_image(): addr 0x00000000, sz 321, flags 0 Debug: 4273 14266 esp_algorithm.c:417 algorithm_load_func_image(): DATA sec size 321 -> 324 Debug: 4274 14266 esp_algorithm.c:419 algorithm_load_func_image(): BSS sec size 316 -> 316 Debug: 4275 14266 target.c:2070 target_alloc_working_area_try(): allocated new working area of 640 bytes at address 0x40804000 [OpenOCD] Debug: 4276 14590 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 4277 14590 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 4278 14590 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 4279 14590 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 4280 14590 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 4281 14590 target.c:1938 print_wa_layout(): 0x40804280-0x40823fff (130432 bytes) Debug: 4282 14590 target.c:2379 target_write_buffer(): writing buffer of 321 byte at 0x40804000 [OpenOCD] Debug: 4283 14594 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804000 Debug: 4284 14600 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4285 14600 esp_riscv.c:826 esp_riscv_write_memory(): Use 32-bit access: size: 1 count:1 start address: 0x40804140 Debug: 4286 14612 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 4287 14618 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804140 Debug: 4288 14623 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4289 14623 target.c:2070 target_alloc_working_area_try(): allocated new working area of 1300 bytes at address 0x40804280 [OpenOCD] Debug: 4290 15030 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 4291 15030 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 4292 15030 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 4293 15030 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 4294 15030 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 4295 15030 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 4296 15030 target.c:1938 print_wa_layout(): 0x40804794-0x40823fff (129132 bytes) Debug: 4297 15030 esp_algorithm.c:460 algorithm_load_func_image(): Stub loaded in 2773.24 ms Debug: 4298 15030 esp_riscv_algorithm.c:43 esp_riscv_algo_regs_init_start(): Check stack addr 0x40804794 Debug: 4299 15030 esp_riscv_algorithm.c:46 esp_riscv_algo_regs_init_start(): Adjust stack addr to 0x40804790 Debug: 4300 15030 esp_riscv_algorithm.c:84 esp_riscv_algo_init(): Set arg[0] = 5 (a0) Debug: 4301 15030 esp_riscv_algorithm.c:95 esp_riscv_algo_init(): Set arg[1] = -1 (a1) Debug: 4302 15030 esp_riscv_algorithm.c:95 esp_riscv_algo_init(): Set arg[2] = 0 (a2) [OpenOCD] Debug: 4303 15030 esp.c:240 esp_common_assist_debug_monitor_disable(): [esp32c6] addr 0x600c2000 Debug: 4304 15050 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 4305 15050 target.c:2598 target_read_u32(): address: 0x600c2000, value: 0x00000000 Debug: 4306 15050 esp.c:248 esp_common_assist_debug_monitor_disable(): Saved register value 0x00000000 Debug: 4307 15050 target.c:2686 target_write_u32(): address: 0x600c2000, value: 0x00000000 Debug: 4308 15058 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600c2000 Debug: 4309 15063 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 4310 15063 target.c:2070 target_alloc_working_area_try(): allocated new working area of 28 bytes at address 0x40804794 [OpenOCD] Debug: 4311 15092 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 4312 15092 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 4313 15092 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 4314 15092 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 4315 15092 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 4316 15092 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 4317 15092 target.c:1938 print_wa_layout(): b* 0x40804794-0x408047af (28 bytes) Debug: 4318 15092 target.c:1938 print_wa_layout(): 0x408047b0-0x40823fff (129104 bytes) Debug: 4319 15092 esp_algorithm.c:90 algorithm_run_image(): Algorithm start @ 0x40801454, stack 1300 bytes @ 0x40804794 Debug: 4320 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save ra Debug: 4321 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read ra: 0x40801456 (cached) Debug: 4322 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x40801456 from ra (valid=1). Debug: 4323 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save sp Debug: 4324 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read sp: 0x40804780 (cached) Debug: 4325 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x40804780 from sp (valid=1). Debug: 4326 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save gp Debug: 4327 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read gp: 0x0 (cached) Debug: 4328 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from gp (valid=1). Debug: 4329 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save tp Debug: 4330 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read tp: 0x0 (cached) Debug: 4331 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tp (valid=1). Debug: 4332 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save t0 Debug: 4333 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read t0: 0x40027bd4 (cached) Debug: 4334 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x40027bd4 from t0 (valid=1). Debug: 4335 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save t1 Debug: 4336 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read t1: 0xffffffe0 (cached) Debug: 4337 15092 riscv.c:5259 register_get(): [esp32c6] Read 0xffffffe0 from t1 (valid=1). Debug: 4338 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save t2 Debug: 4339 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read t2: 0x0 (cached) Debug: 4340 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t2 (valid=1). Debug: 4341 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save fp Debug: 4342 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read fp: 0x0 (cached) Debug: 4343 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from fp (valid=1). Debug: 4344 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s1 Debug: 4345 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s1: 0x0 (cached) Debug: 4346 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s1 (valid=1). Debug: 4347 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save a0 Debug: 4348 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read a0: 0x20000000 (cached) Debug: 4349 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x20000000 from a0 (valid=1). Debug: 4350 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save a1 Debug: 4351 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read a1: 0x60002000 (cached) Debug: 4352 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x60002000 from a1 (valid=1). Debug: 4353 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save a2 Debug: 4354 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read a2: 0x10 (cached) Debug: 4355 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000010 from a2 (valid=1). Debug: 4356 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save a3 Debug: 4357 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read a3: 0x10000 (cached) Debug: 4358 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00010000 from a3 (valid=1). Debug: 4359 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save a4 Debug: 4360 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read a4: 0x408021e0 (cached) Debug: 4361 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x408021e0 from a4 (valid=1). Debug: 4362 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save a5 Debug: 4363 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read a5: 0x4 (cached) Debug: 4364 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000004 from a5 (valid=1). Debug: 4365 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save a6 Debug: 4366 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read a6: 0x8 (cached) Debug: 4367 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000008 from a6 (valid=1). Debug: 4368 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save a7 Debug: 4369 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read a7: 0x80000000 (cached) Debug: 4370 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x80000000 from a7 (valid=1). Debug: 4371 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s2 Debug: 4372 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s2: 0x0 (cached) Debug: 4373 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s2 (valid=1). Debug: 4374 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s3 Debug: 4375 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s3: 0x0 (cached) Debug: 4376 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s3 (valid=1). Debug: 4377 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s4 Debug: 4378 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s4: 0x0 (cached) Debug: 4379 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s4 (valid=1). Debug: 4380 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s5 Debug: 4381 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s5: 0x0 (cached) Debug: 4382 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s5 (valid=1). Debug: 4383 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s6 Debug: 4384 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s6: 0x0 (cached) Debug: 4385 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s6 (valid=1). Debug: 4386 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s7 Debug: 4387 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s7: 0x0 (cached) Debug: 4388 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s7 (valid=1). Debug: 4389 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s8 Debug: 4390 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s8: 0x0 (cached) Debug: 4391 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s8 (valid=1). Debug: 4392 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s9 Debug: 4393 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s9: 0x0 (cached) Debug: 4394 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s9 (valid=1). Debug: 4395 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s10 Debug: 4396 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s10: 0x0 (cached) Debug: 4397 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s10 (valid=1). Debug: 4398 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save s11 Debug: 4399 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read s11: 0x0 (cached) Debug: 4400 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s11 (valid=1). Debug: 4401 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save t3 Debug: 4402 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read t3: 0x0 (cached) Debug: 4403 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t3 (valid=1). Debug: 4404 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save t4 Debug: 4405 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read t4: 0x0 (cached) Debug: 4406 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t4 (valid=1). Debug: 4407 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save t5 Debug: 4408 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read t5: 0x0 (cached) Debug: 4409 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t5 (valid=1). Debug: 4410 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save t6 Debug: 4411 15092 riscv.c:4819 riscv_get_register(): [esp32c6] Read t6: 0x0 (cached) Debug: 4412 15092 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t6 (valid=1). Debug: 4413 15092 esp_riscv.c:593 esp_riscv_start_algorithm(): save pc Debug: 4414 15092 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 4415 15092 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 4416 15092 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 4417 15092 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 4418 15098 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40000000 Debug: 4419 15098 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40000000 Debug: 4420 15098 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40000000 Debug: 4421 15098 riscv.c:5259 register_get(): [esp32c6] Read 0x40000000 from pc (valid=0). Debug: 4422 15098 esp_riscv.c:593 esp_riscv_start_algorithm(): save mstatus Debug: 4423 15098 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mstatus from target Debug: 4424 15098 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mstatus Debug: 4425 15098 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mstatus Debug: 4426 15098 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 4427 15104 riscv-013.c:1561 register_read_direct(): [esp32c6] mstatus = 0x201800 Debug: 4428 15104 riscv.c:4831 riscv_get_register(): [esp32c6] Read mstatus: 0x201800 Debug: 4429 15104 riscv.c:5259 register_get(): [esp32c6] Read 0x00201800 from mstatus (valid=1). Debug: 4430 15104 esp_riscv.c:593 esp_riscv_start_algorithm(): save misa Debug: 4431 15104 riscv.c:4823 riscv_get_register(): [esp32c6] Reading misa from target Debug: 4432 15104 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register misa Debug: 4433 15104 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading misa Debug: 4434 15104 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 4435 15112 riscv-013.c:1561 register_read_direct(): [esp32c6] misa = 0x40903105 Debug: 4436 15112 riscv.c:4831 riscv_get_register(): [esp32c6] Read misa: 0x40903105 Debug: 4437 15112 riscv.c:5259 register_get(): [esp32c6] Read 0x40903105 from misa (valid=1). Debug: 4438 15112 esp_riscv.c:593 esp_riscv_start_algorithm(): save mtvec Debug: 4439 15112 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mtvec from target Debug: 4440 15112 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr773 Debug: 4441 15112 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr773 Debug: 4442 15112 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305 Debug: 4443 15118 riscv-013.c:1561 register_read_direct(): [esp32c6] csr773 = 0x1 Debug: 4444 15118 riscv.c:4831 riscv_get_register(): [esp32c6] Read mtvec: 0x1 Debug: 4445 15118 riscv.c:5259 register_get(): [esp32c6] Read 0x00000001 from mtvec (valid=0). Debug: 4446 15118 esp_riscv.c:593 esp_riscv_start_algorithm(): save mscratch Debug: 4447 15118 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mscratch from target Debug: 4448 15118 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr832 Debug: 4449 15118 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr832 Debug: 4450 15118 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340 Debug: 4451 15125 riscv-013.c:1561 register_read_direct(): [esp32c6] csr832 = 0x0 Debug: 4452 15125 riscv.c:4831 riscv_get_register(): [esp32c6] Read mscratch: 0x0 Debug: 4453 15125 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mscratch (valid=0). Debug: 4454 15125 esp_riscv.c:593 esp_riscv_start_algorithm(): save mepc Debug: 4455 15125 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mepc from target Debug: 4456 15125 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mepc Debug: 4457 15125 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mepc Debug: 4458 15125 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 4459 15131 riscv-013.c:1561 register_read_direct(): [esp32c6] mepc = 0x0 Debug: 4460 15131 riscv.c:4831 riscv_get_register(): [esp32c6] Read mepc: 0x0 Debug: 4461 15131 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mepc (valid=1). Debug: 4462 15131 esp_riscv.c:593 esp_riscv_start_algorithm(): save mcause Debug: 4463 15131 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mcause from target Debug: 4464 15131 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mcause Debug: 4465 15131 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mcause Debug: 4466 15131 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 Debug: 4467 15138 riscv-013.c:1561 register_read_direct(): [esp32c6] mcause = 0x0 Debug: 4468 15138 riscv.c:4831 riscv_get_register(): [esp32c6] Read mcause: 0x0 Debug: 4469 15138 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mcause (valid=1). Debug: 4470 15138 esp_riscv.c:593 esp_riscv_start_algorithm(): save mtval Debug: 4471 15138 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mtval from target Debug: 4472 15138 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr835 Debug: 4473 15138 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr835 Debug: 4474 15138 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343 Debug: 4475 15143 riscv-013.c:1561 register_read_direct(): [esp32c6] csr835 = 0x0 Debug: 4476 15143 riscv.c:4831 riscv_get_register(): [esp32c6] Read mtval: 0x0 Debug: 4477 15143 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mtval (valid=0). Debug: 4478 15143 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg0 Debug: 4479 15143 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg0 from target Debug: 4480 15143 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr928 Debug: 4481 15143 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr928 Debug: 4482 15143 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0 Debug: 4483 15148 riscv-013.c:1561 register_read_direct(): [esp32c6] csr928 = 0x0 Debug: 4484 15148 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg0: 0x0 Debug: 4485 15148 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg0 (valid=0). Debug: 4486 15148 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg1 Debug: 4487 15148 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg1 from target Debug: 4488 15148 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr929 Debug: 4489 15148 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr929 Debug: 4490 15148 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1 [OpenOCD] Debug: 4491 15155 riscv-013.c:1561 register_read_direct(): [esp32c6] csr929 = 0x0 Debug: 4492 15155 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg1: 0x0 Debug: 4493 15155 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg1 (valid=0). Debug: 4494 15155 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg2 Debug: 4495 15155 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg2 from target Debug: 4496 15155 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr930 Debug: 4497 15155 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr930 Debug: 4498 15155 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2 Debug: 4499 15163 riscv-013.c:1561 register_read_direct(): [esp32c6] csr930 = 0x0 Debug: 4500 15163 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg2: 0x0 Debug: 4501 15163 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg2 (valid=0). Debug: 4502 15163 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg3 Debug: 4503 15163 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg3 from target Debug: 4504 15163 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr931 Debug: 4505 15163 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr931 Debug: 4506 15163 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3 Debug: 4507 15184 riscv-013.c:1561 register_read_direct(): [esp32c6] csr931 = 0x0 Debug: 4508 15184 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg3: 0x0 Debug: 4509 15184 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg3 (valid=0). Debug: 4510 15184 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr0 Debug: 4511 15184 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr0 from target Debug: 4512 15184 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr944 Debug: 4513 15184 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr944 Debug: 4514 15184 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0 Debug: 4515 15198 riscv-013.c:1561 register_read_direct(): [esp32c6] csr944 = 0x0 Debug: 4516 15198 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr0: 0x0 Debug: 4517 15198 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr0 (valid=0). Debug: 4518 15198 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr1 Debug: 4519 15198 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr1 from target Debug: 4520 15198 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr945 Debug: 4521 15198 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr945 Debug: 4522 15198 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1 Debug: 4523 15208 riscv-013.c:1561 register_read_direct(): [esp32c6] csr945 = 0x0 Debug: 4524 15208 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr1: 0x0 Debug: 4525 15208 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr1 (valid=0). Debug: 4526 15208 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr2 Debug: 4527 15208 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr2 from target Debug: 4528 15208 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr946 Debug: 4529 15208 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr946 Debug: 4530 15208 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2 [OpenOCD] Debug: 4531 15219 riscv-013.c:1561 register_read_direct(): [esp32c6] csr946 = 0x0 Debug: 4532 15219 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr2: 0x0 Debug: 4533 15219 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr2 (valid=0). Debug: 4534 15219 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr3 Debug: 4535 15219 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr3 from target Debug: 4536 15219 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr947 Debug: 4537 15219 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr947 Debug: 4538 15219 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3 Debug: 4539 15227 riscv-013.c:1561 register_read_direct(): [esp32c6] csr947 = 0x0 Debug: 4540 15227 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr3: 0x0 Debug: 4541 15227 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr3 (valid=0). Debug: 4542 15227 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr4 Debug: 4543 15227 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr4 from target Debug: 4544 15227 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr948 Debug: 4545 15227 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr948 Debug: 4546 15227 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4 Debug: 4547 15241 riscv-013.c:1561 register_read_direct(): [esp32c6] csr948 = 0x0 Debug: 4548 15241 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr4: 0x0 Debug: 4549 15241 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr4 (valid=0). Debug: 4550 15241 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr5 Debug: 4551 15241 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr5 from target Debug: 4552 15241 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr949 Debug: 4553 15241 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr949 Debug: 4554 15241 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5 Debug: 4555 15255 riscv-013.c:1561 register_read_direct(): [esp32c6] csr949 = 0x0 Debug: 4556 15255 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr5: 0x0 Debug: 4557 15255 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr5 (valid=0). Debug: 4558 15255 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr6 Debug: 4559 15255 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr6 from target Debug: 4560 15255 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr950 Debug: 4561 15255 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr950 Debug: 4562 15255 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6 Debug: 4563 15265 riscv-013.c:1561 register_read_direct(): [esp32c6] csr950 = 0x0 Debug: 4564 15265 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr6: 0x0 Debug: 4565 15265 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr6 (valid=0). Debug: 4566 15265 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr7 Debug: 4567 15265 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr7 from target Debug: 4568 15265 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr951 Debug: 4569 15265 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr951 Debug: 4570 15265 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7 Debug: 4571 15274 riscv-013.c:1561 register_read_direct(): [esp32c6] csr951 = 0x0 Debug: 4572 15274 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr7: 0x0 Debug: 4573 15274 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr7 (valid=0). Debug: 4574 15274 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr8 Debug: 4575 15274 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr8 from target Debug: 4576 15274 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr952 Debug: 4577 15274 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr952 Debug: 4578 15274 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8 [OpenOCD] Debug: 4579 15289 riscv-013.c:1561 register_read_direct(): [esp32c6] csr952 = 0x0 Debug: 4580 15289 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr8: 0x0 Debug: 4581 15289 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr8 (valid=0). Debug: 4582 15289 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr9 Debug: 4583 15289 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr9 from target Debug: 4584 15289 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr953 Debug: 4585 15289 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr953 Debug: 4586 15289 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9 Debug: 4587 15341 riscv-013.c:1561 register_read_direct(): [esp32c6] csr953 = 0x0 Debug: 4588 15341 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr9: 0x0 Debug: 4589 15341 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr9 (valid=0). Debug: 4590 15341 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr10 Debug: 4591 15341 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr10 from target Debug: 4592 15341 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr954 Debug: 4593 15341 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr954 Debug: 4594 15341 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba Debug: 4595 15352 riscv-013.c:1561 register_read_direct(): [esp32c6] csr954 = 0x0 Debug: 4596 15352 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr10: 0x0 Debug: 4597 15352 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr10 (valid=0). Debug: 4598 15352 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr11 Debug: 4599 15352 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr11 from target Debug: 4600 15352 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr955 Debug: 4601 15352 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr955 Debug: 4602 15352 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb Debug: 4603 15362 riscv-013.c:1561 register_read_direct(): [esp32c6] csr955 = 0x0 Debug: 4604 15362 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr11: 0x0 Debug: 4605 15362 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr11 (valid=0). Debug: 4606 15362 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr12 Debug: 4607 15362 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr12 from target Debug: 4608 15362 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr956 Debug: 4609 15362 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr956 Debug: 4610 15362 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc [OpenOCD] Debug: 4611 15371 riscv-013.c:1561 register_read_direct(): [esp32c6] csr956 = 0x0 Debug: 4612 15371 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr12: 0x0 Debug: 4613 15371 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr12 (valid=0). Debug: 4614 15371 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr13 Debug: 4615 15371 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr13 from target Debug: 4616 15371 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr957 Debug: 4617 15371 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr957 Debug: 4618 15371 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd Debug: 4619 15381 riscv-013.c:1561 register_read_direct(): [esp32c6] csr957 = 0x0 Debug: 4620 15381 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr13: 0x0 Debug: 4621 15381 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr13 (valid=0). Debug: 4622 15381 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr14 Debug: 4623 15381 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr14 from target Debug: 4624 15381 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr958 Debug: 4625 15381 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr958 Debug: 4626 15381 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be Debug: 4627 15394 riscv-013.c:1561 register_read_direct(): [esp32c6] csr958 = 0x0 Debug: 4628 15394 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr14: 0x0 Debug: 4629 15394 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr14 (valid=0). Debug: 4630 15394 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr15 Debug: 4631 15394 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr15 from target Debug: 4632 15394 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr959 Debug: 4633 15394 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr959 Debug: 4634 15394 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf Debug: 4635 15409 riscv-013.c:1561 register_read_direct(): [esp32c6] csr959 = 0x0 Debug: 4636 15409 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr15: 0x0 Debug: 4637 15409 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr15 (valid=0). Debug: 4638 15409 esp_riscv.c:593 esp_riscv_start_algorithm(): save tselect Debug: 4639 15409 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 4640 15409 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 4641 15409 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 4642 15409 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 4643 15420 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x0 Debug: 4644 15420 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x0 Debug: 4645 15420 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tselect (valid=0). Debug: 4646 15420 esp_riscv.c:593 esp_riscv_start_algorithm(): save tdata1 Debug: 4647 15420 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata1 from target Debug: 4648 15420 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata1 Debug: 4649 15420 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata1 Debug: 4650 15420 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 4651 15429 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata1 = 0x23e00000 Debug: 4652 15429 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata1: 0x23e00000 Debug: 4653 15429 riscv.c:5259 register_get(): [esp32c6] Read 0x23e00000 from tdata1 (valid=0). Debug: 4654 15429 esp_riscv.c:593 esp_riscv_start_algorithm(): save tdata2 Debug: 4655 15429 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata2 from target Debug: 4656 15429 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata2 Debug: 4657 15429 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata2 Debug: 4658 15429 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2 Debug: 4659 15436 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata2 = 0x0 Debug: 4660 15436 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata2: 0x0 Debug: 4661 15436 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tdata2 (valid=0). Debug: 4662 15436 esp_riscv.c:593 esp_riscv_start_algorithm(): save tcontrol Debug: 4663 15436 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tcontrol from target Debug: 4664 15436 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr1957 Debug: 4665 15436 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr1957 Debug: 4666 15436 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5 [OpenOCD] Debug: 4667 15442 riscv-013.c:1561 register_read_direct(): [esp32c6] csr1957 = 0x0 Debug: 4668 15442 riscv.c:4831 riscv_get_register(): [esp32c6] Read tcontrol: 0x0 Debug: 4669 15442 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tcontrol (valid=0). Debug: 4670 15442 esp_riscv.c:593 esp_riscv_start_algorithm(): save dcsr Debug: 4671 15442 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dcsr from target Debug: 4672 15442 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dcsr Debug: 4673 15442 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 4674 15442 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 4675 15453 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 4676 15453 riscv.c:4831 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 Debug: 4677 15453 riscv.c:5259 register_get(): [esp32c6] Read 0x400090c3 from dcsr (valid=1). Debug: 4678 15453 esp_riscv.c:593 esp_riscv_start_algorithm(): save dpc Debug: 4679 15453 riscv.c:4819 riscv_get_register(): [esp32c6] Read dpc: 0x40000000 (cached) Debug: 4680 15453 riscv.c:5259 register_get(): [esp32c6] Read 0x40000000 from dpc (valid=1). Debug: 4681 15453 esp_riscv.c:593 esp_riscv_start_algorithm(): save dscratch0 Debug: 4682 15453 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dscratch0 from target Debug: 4683 15453 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dscratch0 Debug: 4684 15453 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dscratch0 Debug: 4685 15453 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2 Debug: 4686 15461 riscv-013.c:1561 register_read_direct(): [esp32c6] dscratch0 = 0x0 Debug: 4687 15461 riscv.c:4831 riscv_get_register(): [esp32c6] Read dscratch0: 0x0 Debug: 4688 15461 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from dscratch0 (valid=1). Debug: 4689 15461 esp_riscv.c:593 esp_riscv_start_algorithm(): save dscratch1 Debug: 4690 15461 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dscratch1 from target Debug: 4691 15461 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr1971 Debug: 4692 15461 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr1971 Debug: 4693 15461 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3 Debug: 4694 15471 riscv-013.c:1561 register_read_direct(): [esp32c6] csr1971 = 0x20000000 Debug: 4695 15471 riscv.c:4831 riscv_get_register(): [esp32c6] Read dscratch1: 0x20000000 Debug: 4696 15471 riscv.c:5259 register_get(): [esp32c6] Read 0x20000000 from dscratch1 (valid=0). Debug: 4697 15471 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpcer Debug: 4698 15471 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpcer from target Debug: 4699 15471 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2016 Debug: 4700 15471 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2016 Debug: 4701 15471 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e0 Debug: 4702 15479 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2016 = 0x0 Debug: 4703 15479 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpcer: 0x0 Debug: 4704 15479 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_mpcer (valid=0). Debug: 4705 15479 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpcmr Debug: 4706 15479 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpcmr from target Debug: 4707 15479 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2017 Debug: 4708 15479 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2017 Debug: 4709 15479 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e1 Debug: 4710 15486 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2017 = 0x3 Debug: 4711 15486 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpcmr: 0x3 Debug: 4712 15486 riscv.c:5259 register_get(): [esp32c6] Read 0x00000003 from csr_mpcmr (valid=0). Debug: 4713 15486 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpccr Debug: 4714 15486 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpccr from target Debug: 4715 15486 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2018 Debug: 4716 15486 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2018 Debug: 4717 15486 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e2 Debug: 4718 15491 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2018 = 0x0 Debug: 4719 15491 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpccr: 0x0 Debug: 4720 15491 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_mpccr (valid=0). Debug: 4721 15491 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_oen Debug: 4722 15491 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_oen from target Debug: 4723 15491 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2051 Debug: 4724 15491 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2051 Debug: 4725 15491 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220803; access register, size=32, postexec=0, transfer=1, write=0, regno=0x803 [OpenOCD] Debug: 4726 15497 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2051 = 0x0 Debug: 4727 15497 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_oen: 0x0 Debug: 4728 15497 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_oen (valid=0). Debug: 4729 15497 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_in Debug: 4730 15497 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_in from target Debug: 4731 15497 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2052 Debug: 4732 15497 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2052 Debug: 4733 15497 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220804; access register, size=32, postexec=0, transfer=1, write=0, regno=0x804 Debug: 4734 15506 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2052 = 0x0 Debug: 4735 15506 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_in: 0x0 Debug: 4736 15506 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_in (valid=0). Debug: 4737 15506 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_out Debug: 4738 15506 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_out from target Debug: 4739 15506 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2053 Debug: 4740 15506 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2053 Debug: 4741 15506 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220805; access register, size=32, postexec=0, transfer=1, write=0, regno=0x805 Debug: 4742 15515 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2053 = 0x0 Debug: 4743 15515 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_out: 0x0 Debug: 4744 15515 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_out (valid=0). Debug: 4745 15515 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg0 Debug: 4746 15515 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg0 from target Debug: 4747 15515 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3008 Debug: 4748 15515 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3008 Debug: 4749 15515 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc0 Debug: 4750 15535 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3008 = 0x0 Debug: 4751 15535 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg0: 0x0 Debug: 4752 15535 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg0 (valid=0). Debug: 4753 15535 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg1 Debug: 4754 15535 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg1 from target Debug: 4755 15535 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3009 Debug: 4756 15535 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3009 Debug: 4757 15535 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc1; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc1 Debug: 4758 15547 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3009 = 0x0 Debug: 4759 15547 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg1: 0x0 Debug: 4760 15547 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg1 (valid=0). Debug: 4761 15547 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg2 Debug: 4762 15547 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg2 from target Debug: 4763 15547 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3010 Debug: 4764 15547 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3010 Debug: 4765 15547 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc2; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc2 Debug: 4766 15555 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3010 = 0x0 Debug: 4767 15555 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg2: 0x0 Debug: 4768 15555 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg2 (valid=0). Debug: 4769 15555 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg3 Debug: 4770 15555 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg3 from target Debug: 4771 15555 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3011 Debug: 4772 15555 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3011 Debug: 4773 15555 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc3; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc3 Debug: 4774 15562 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3011 = 0x0 Debug: 4775 15562 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg3: 0x0 Debug: 4776 15562 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg3 (valid=0). Debug: 4777 15562 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg4 Debug: 4778 15562 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg4 from target Debug: 4779 15562 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3012 Debug: 4780 15562 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3012 Debug: 4781 15562 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc4; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc4 Debug: 4782 15569 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3012 = 0x0 Debug: 4783 15569 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg4: 0x0 Debug: 4784 15569 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg4 (valid=0). Debug: 4785 15569 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg5 Debug: 4786 15569 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg5 from target Debug: 4787 15569 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3013 Debug: 4788 15569 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3013 Debug: 4789 15569 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc5; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc5 Debug: 4790 15580 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3013 = 0x0 Debug: 4791 15580 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg5: 0x0 Debug: 4792 15580 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg5 (valid=0). Debug: 4793 15580 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg6 Debug: 4794 15580 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg6 from target Debug: 4795 15580 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3014 Debug: 4796 15580 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3014 Debug: 4797 15580 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc6; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc6 [OpenOCD] Debug: 4798 15588 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3014 = 0x0 Debug: 4799 15588 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg6: 0x0 Debug: 4800 15588 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg6 (valid=0). Debug: 4801 15588 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg7 Debug: 4802 15588 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg7 from target Debug: 4803 15588 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3015 Debug: 4804 15588 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3015 Debug: 4805 15588 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc7; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc7 Debug: 4806 15600 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3015 = 0x0 Debug: 4807 15600 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg7: 0x0 Debug: 4808 15600 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg7 (valid=0). Debug: 4809 15600 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg8 Debug: 4810 15600 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg8 from target Debug: 4811 15600 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3016 Debug: 4812 15600 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3016 Debug: 4813 15600 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc8; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc8 Debug: 4814 15612 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3016 = 0x0 Debug: 4815 15612 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg8: 0x0 Debug: 4816 15612 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg8 (valid=0). Debug: 4817 15612 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg9 Debug: 4818 15612 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg9 from target Debug: 4819 15612 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3017 Debug: 4820 15612 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3017 Debug: 4821 15612 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc9; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc9 Debug: 4822 15622 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3017 = 0x0 Debug: 4823 15622 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg9: 0x0 Debug: 4824 15622 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg9 (valid=0). Debug: 4825 15622 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg10 Debug: 4826 15622 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg10 from target Debug: 4827 15622 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3018 Debug: 4828 15622 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3018 Debug: 4829 15622 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bca; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbca Debug: 4830 15631 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3018 = 0x0 Debug: 4831 15631 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg10: 0x0 Debug: 4832 15631 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg10 (valid=0). Debug: 4833 15631 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg11 Debug: 4834 15632 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg11 from target Debug: 4835 15632 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3019 Debug: 4836 15632 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3019 Debug: 4837 15632 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcb; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcb Debug: 4838 15639 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3019 = 0x0 Debug: 4839 15639 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg11: 0x0 Debug: 4840 15639 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg11 (valid=0). Debug: 4841 15639 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg12 Debug: 4842 15639 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg12 from target Debug: 4843 15639 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3020 Debug: 4844 15639 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3020 Debug: 4845 15639 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcc; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcc Debug: 4846 15645 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3020 = 0x0 Debug: 4847 15645 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg12: 0x0 Debug: 4848 15645 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg12 (valid=0). Debug: 4849 15645 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg13 Debug: 4850 15645 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg13 from target Debug: 4851 15645 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3021 Debug: 4852 15645 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3021 Debug: 4853 15646 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcd; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcd [OpenOCD] Debug: 4854 15661 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3021 = 0x0 Debug: 4855 15661 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg13: 0x0 Debug: 4856 15661 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg13 (valid=0). Debug: 4857 15661 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg14 Debug: 4858 15661 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg14 from target Debug: 4859 15661 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3022 Debug: 4860 15661 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3022 Debug: 4861 15661 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bce; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbce Debug: 4862 15699 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3022 = 0x0 Debug: 4863 15699 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg14: 0x0 Debug: 4864 15699 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg14 (valid=0). Debug: 4865 15699 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg15 Debug: 4866 15699 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg15 from target Debug: 4867 15699 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3023 Debug: 4868 15699 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3023 Debug: 4869 15699 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcf; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcf Debug: 4870 15726 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3023 = 0x0 Debug: 4871 15726 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg15: 0x0 Debug: 4872 15726 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg15 (valid=0). Debug: 4873 15726 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr0 Debug: 4874 15726 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr0 from target Debug: 4875 15726 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3024 Debug: 4876 15726 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3024 Debug: 4877 15726 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd0 Debug: 4878 15734 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3024 = 0x0 Debug: 4879 15734 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr0: 0x0 Debug: 4880 15734 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr0 (valid=0). Debug: 4881 15734 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr1 Debug: 4882 15734 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr1 from target Debug: 4883 15734 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3025 Debug: 4884 15734 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3025 Debug: 4885 15734 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd1; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd1 Debug: 4886 15748 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3025 = 0x0 Debug: 4887 15748 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr1: 0x0 Debug: 4888 15748 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr1 (valid=0). Debug: 4889 15748 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr2 Debug: 4890 15748 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr2 from target Debug: 4891 15748 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3026 Debug: 4892 15748 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3026 Debug: 4893 15748 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd2; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd2 Debug: 4894 15759 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3026 = 0x0 Debug: 4895 15759 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr2: 0x0 Debug: 4896 15759 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr2 (valid=0). Debug: 4897 15759 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr3 Debug: 4898 15759 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr3 from target Debug: 4899 15759 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3027 Debug: 4900 15759 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3027 Debug: 4901 15759 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd3; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd3 [OpenOCD] Debug: 4902 15770 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3027 = 0x0 Debug: 4903 15770 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr3: 0x0 Debug: 4904 15770 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr3 (valid=0). Debug: 4905 15770 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr4 Debug: 4906 15770 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr4 from target Debug: 4907 15770 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3028 Debug: 4908 15770 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3028 Debug: 4909 15770 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd4; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd4 Debug: 4910 15782 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3028 = 0x0 Debug: 4911 15782 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr4: 0x0 Debug: 4912 15782 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr4 (valid=0). Debug: 4913 15782 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr5 Debug: 4914 15782 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr5 from target Debug: 4915 15782 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3029 Debug: 4916 15782 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3029 Debug: 4917 15782 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd5; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd5 Debug: 4918 15791 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3029 = 0x0 Debug: 4919 15791 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr5: 0x0 Debug: 4920 15791 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr5 (valid=0). Debug: 4921 15791 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr6 Debug: 4922 15791 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr6 from target Debug: 4923 15791 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3030 Debug: 4924 15791 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3030 Debug: 4925 15791 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd6; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd6 Debug: 4926 15807 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3030 = 0x0 Debug: 4927 15807 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr6: 0x0 Debug: 4928 15807 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr6 (valid=0). Debug: 4929 15807 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr7 Debug: 4930 15807 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr7 from target Debug: 4931 15807 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3031 Debug: 4932 15807 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3031 Debug: 4933 15807 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd7; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd7 Debug: 4934 15813 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3031 = 0x0 Debug: 4935 15813 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr7: 0x0 Debug: 4936 15813 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr7 (valid=0). Debug: 4937 15813 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr8 Debug: 4938 15813 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr8 from target Debug: 4939 15813 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3032 Debug: 4940 15813 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3032 Debug: 4941 15813 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd8; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd8 [OpenOCD] Debug: 4942 15821 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3032 = 0x0 Debug: 4943 15821 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr8: 0x0 Debug: 4944 15821 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr8 (valid=0). Debug: 4945 15821 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr9 Debug: 4946 15821 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr9 from target Debug: 4947 15821 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3033 Debug: 4948 15821 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3033 Debug: 4949 15821 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd9; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd9 Debug: 4950 15828 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3033 = 0x0 Debug: 4951 15828 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr9: 0x0 Debug: 4952 15828 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr9 (valid=0). Debug: 4953 15828 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr10 Debug: 4954 15828 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr10 from target Debug: 4955 15828 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3034 Debug: 4956 15828 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3034 Debug: 4957 15828 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bda; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbda Debug: 4958 15840 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3034 = 0x0 Debug: 4959 15840 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr10: 0x0 Debug: 4960 15840 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr10 (valid=0). Debug: 4961 15840 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr11 Debug: 4962 15840 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr11 from target Debug: 4963 15840 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3035 Debug: 4964 15840 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3035 Debug: 4965 15840 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdb; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdb Debug: 4966 15849 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3035 = 0x0 Debug: 4967 15849 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr11: 0x0 Debug: 4968 15849 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr11 (valid=0). Debug: 4969 15849 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr12 Debug: 4970 15849 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr12 from target Debug: 4971 15849 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3036 Debug: 4972 15849 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3036 Debug: 4973 15849 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdc; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdc Debug: 4974 15858 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3036 = 0x0 Debug: 4975 15858 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr12: 0x0 Debug: 4976 15858 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr12 (valid=0). Debug: 4977 15858 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr13 Debug: 4978 15858 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr13 from target Debug: 4979 15858 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3037 Debug: 4980 15858 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3037 Debug: 4981 15858 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdd; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdd Debug: 4982 15867 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3037 = 0x0 Debug: 4983 15867 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr13: 0x0 Debug: 4984 15867 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr13 (valid=0). Debug: 4985 15867 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr14 Debug: 4986 15867 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr14 from target Debug: 4987 15867 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3038 Debug: 4988 15867 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3038 Debug: 4989 15867 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bde; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbde Debug: 4990 15874 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3038 = 0x0 Debug: 4991 15874 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr14: 0x0 Debug: 4992 15874 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr14 (valid=0). Debug: 4993 15874 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr15 Debug: 4994 15874 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr15 from target Debug: 4995 15874 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3039 Debug: 4996 15874 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3039 Debug: 4997 15874 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdf; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdf [OpenOCD] Debug: 4998 15881 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3039 = 0x0 Debug: 4999 15881 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr15: 0x0 Debug: 5000 15881 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr15 (valid=0). Debug: 5001 15881 esp_riscv.c:593 esp_riscv_start_algorithm(): save hpmcounter16 Debug: 5002 15881 riscv.c:4823 riscv_get_register(): [esp32c6] Reading hpmcounter16 from target Debug: 5003 15881 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3088 Debug: 5004 15881 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3088 Debug: 5005 15881 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10 Debug: 5006 15889 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3088 = 0x3 Debug: 5007 15889 riscv.c:4831 riscv_get_register(): [esp32c6] Read hpmcounter16: 0x3 Debug: 5008 15889 riscv.c:5259 register_get(): [esp32c6] Read 0x00000003 from hpmcounter16 (valid=0). Debug: 5009 15889 esp_riscv.c:593 esp_riscv_start_algorithm(): save priv Debug: 5010 15889 riscv.c:4823 riscv_get_register(): [esp32c6] Reading priv from target Debug: 5011 15889 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register priv Debug: 5012 15889 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 5013 15889 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 5014 15896 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 5015 15896 riscv.c:4831 riscv_get_register(): [esp32c6] Read priv: 0x3 Debug: 5016 15896 riscv.c:5259 register_get(): [esp32c6] Read 0x03 from priv (valid=0). Debug: 5017 15896 esp_riscv.c:622 esp_riscv_start_algorithm(): set sp Debug: 5018 15896 riscv.c:5274 register_set(): [esp32c6] Write 0x40804780 to sp (valid=1). Debug: 5019 15896 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804780 to sp (cacheable=true, valid=true, dirty=false) Debug: 5020 15896 esp_riscv.c:622 esp_riscv_start_algorithm(): set a7 Debug: 5021 15896 riscv.c:5274 register_set(): [esp32c6] Write 0x4080110c to a7 (valid=1). Debug: 5022 15896 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4080110c to a7 (cacheable=true, valid=true, dirty=true) Debug: 5023 15896 esp_riscv.c:622 esp_riscv_start_algorithm(): set a0 Debug: 5024 15896 riscv.c:5274 register_set(): [esp32c6] Write 0x00000005 to a0 (valid=1). Debug: 5025 15896 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x5 to a0 (cacheable=true, valid=true, dirty=true) Debug: 5026 15896 esp_riscv.c:622 esp_riscv_start_algorithm(): set a1 Debug: 5027 15896 riscv.c:5274 register_set(): [esp32c6] Write 0xffffffff to a1 (valid=1). Debug: 5028 15896 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0xffffffff to a1 (cacheable=true, valid=true, dirty=true) Debug: 5029 15896 esp_riscv.c:622 esp_riscv_start_algorithm(): set a2 Debug: 5030 15896 riscv.c:5274 register_set(): [esp32c6] Write 0x40804794 to a2 (valid=1). Debug: 5031 15896 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804794 to a2 (cacheable=true, valid=true, dirty=true) Debug: 5032 15896 riscv.c:4550 riscv_interrupts_disable(): [esp32c6] Disabling interrupts. Debug: 5033 15896 riscv.c:4819 riscv_get_register(): [esp32c6] Read mstatus: 0x201800 (cached) Debug: 5034 15896 riscv.c:5259 register_get(): [esp32c6] Read 0x00201800 from mstatus (valid=1). Debug: 5035 15896 riscv.c:5274 register_set(): [esp32c6] Write 0x00201800 to mstatus (valid=1). Debug: 5036 15896 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x201800 to mstatus (cacheable=true, valid=true, dirty=false) Debug: 5037 15896 esp_riscv.c:659 esp_riscv_start_algorithm(): resume at 0x40801454 Debug: 5038 15896 riscv.c:1932 riscv_resume(): [esp32c6] current=false, address=0x40801454, handle_breakpoints=false, debug_exec=true Debug: 5039 15896 riscv.c:1937 riscv_resume(): [esp32c6] target->state=halted Debug: 5040 15896 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pc <- 0x40801454 (cacheable=false, valid=false, dirty=false) Debug: 5041 15896 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40801454 to register pc Debug: 5042 15896 riscv-013.c:4562 riscv013_set_register(): [esp32c6] writing PC to DPC: 0x40801454 Debug: 5043 15896 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40801454 to dpc Debug: 5044 15900 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 5045 15945 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40801454 Debug: 5046 15945 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40801454 to pc (cacheable=false, valid=false, dirty=false) Debug: 5047 15945 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[00] = DASM(0x0000100f) Debug: 5048 15945 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x100f @0 Debug: 5049 15945 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[01] = DASM(0x0330000f) Debug: 5050 15945 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x330000f @1 Debug: 5051 15945 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[02] = DASM(0x00100073) Debug: 5052 15945 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x100073 @2 Debug: 5053 15945 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 5054 15965 riscv-013.c:1591 set_dcsr_ebreak(): [esp32c6] Set dcsr.ebreak* Debug: 5055 15965 riscv.c:4819 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 (cached) Debug: 5056 15965 riscv.c:1575 riscv_flush_registers(): [esp32c6] a7 is dirty; write back 0x4080110c Debug: 5057 15965 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4080110c to register a7 Debug: 5058 15965 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4080110c to a7 Debug: 5059 15971 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 [OpenOCD] Debug: 5060 15978 riscv-013.c:1532 register_write_direct(): [esp32c6] a7 <- 0x4080110c Debug: 5061 15978 riscv.c:1575 riscv_flush_registers(): [esp32c6] a2 is dirty; write back 0x40804794 Debug: 5062 15978 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40804794 to register a2 Debug: 5063 15978 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40804794 to a2 Debug: 5064 16016 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 5065 16023 riscv-013.c:1532 register_write_direct(): [esp32c6] a2 <- 0x40804794 Debug: 5066 16023 riscv.c:1575 riscv_flush_registers(): [esp32c6] a1 is dirty; write back 0xffffffff Debug: 5067 16023 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0xffffffff to register a1 Debug: 5068 16023 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0xffffffff to a1 Debug: 5069 16031 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 5070 16040 riscv-013.c:1532 register_write_direct(): [esp32c6] a1 <- 0xffffffff Debug: 5071 16040 riscv.c:1575 riscv_flush_registers(): [esp32c6] a0 is dirty; write back 0x5 Debug: 5072 16040 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x5 to register a0 Debug: 5073 16040 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x5 to a0 Debug: 5074 16044 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 5075 16049 riscv-013.c:1532 register_write_direct(): [esp32c6] a0 <- 0x5 Debug: 5076 16049 riscv.c:1858 resume_prep(): [esp32c6] Mark as prepped. Debug: 5077 16049 riscv.c:4536 riscv_resume_go_all_harts(): [esp32c6] Resuming hart, state=2. Debug: 5078 16049 riscv-013.c:4625 select_prepped_harts(): [esp32c6] index=0, coreid=0, prepped=1 Debug: 5079 16049 riscv-013.c:4922 riscv013_step_or_resume_current_hart(): [esp32c6] resuming (for step?=0) Debug: 5080 16062 riscv.c:4640 riscv_invalidate_register_cache(): [esp32c6] Invalidating register cache. Debug: 5081 16062 target.c:1812 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c6 Debug: 5082 16062 esp_algorithm.c:111 algorithm_run_image(): Wait algorithm completion Debug: 5083 16065 riscv.c:2779 riscv_poll_hart(): [esp32c6] triggered a halt; previous_target_state=4 Debug: 5084 16065 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 5085 16065 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 5086 16073 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x40009043 Debug: 5087 16073 riscv-013.c:4791 riscv013_halt_reason(): [esp32c6] dcsr.cause: 0x1 Debug: 5088 16073 riscv.c:1621 set_debug_reason(): [esp32c6] debug_reason=1 Debug: 5089 16073 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 5090 16073 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 5091 16073 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 5092 16073 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 [OpenOCD] Debug: 5093 16080 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40801456 Debug: 5094 16080 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40801456 Debug: 5095 16080 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40801456 Debug: 5096 16080 esp_riscv.c:799 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40801452 Debug: 5097 16108 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 5098 16108 riscv_semihosting.c:94 riscv_semihosting(): [esp32c6] compare 0x98820613 from 0x40801452 against 0x01f01013 Debug: 5099 16108 riscv_semihosting.c:96 riscv_semihosting(): [esp32c6] -> NONE (no magic) Debug: 5100 16108 target.c:1812 target_call_event_callbacks(): target event 17 (debug-halted) for core esp32c6 Debug: 5101 16108 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 5102 16108 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 5103 16108 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 5104 16108 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 5105 16117 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40801456 Debug: 5106 16117 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40801456 Debug: 5107 16117 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40801456 Debug: 5108 16117 riscv.c:5259 register_get(): [esp32c6] Read 0x40801456 from pc (valid=0). Debug: 5109 16117 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a0 from target Debug: 5110 16117 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a0 Debug: 5111 16117 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a0 Debug: 5112 16117 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 5113 16146 riscv-013.c:1561 register_read_direct(): [esp32c6] a0 = 0x0 Debug: 5114 16146 riscv.c:4831 riscv_get_register(): [esp32c6] Read a0: 0x0 Debug: 5115 16146 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from a0 (valid=1). Debug: 5116 16146 esp_riscv.c:733 esp_riscv_wait_algorithm(): Read mem params Debug: 5117 16146 esp_riscv.c:735 esp_riscv_wait_algorithm(): Check mem param @ 0x40804794 Debug: 5118 16146 esp_riscv.c:737 esp_riscv_wait_algorithm(): Read mem param @ 0x40804794 Debug: 5119 16146 target.c:2444 target_read_buffer(): reading buffer of 28 byte at 0x40804794 [OpenOCD] Debug: 5120 16228 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 5121 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore ra Debug: 5122 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x40801456 to ra (valid=0). Debug: 5123 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40801456 to ra (cacheable=true, valid=true, dirty=true) Debug: 5124 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore sp Debug: 5125 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x40804780 to sp (valid=0). Debug: 5126 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804780 to sp (cacheable=true, valid=true, dirty=true) Debug: 5127 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore gp Debug: 5128 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to gp (valid=0). Debug: 5129 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to gp (cacheable=true, valid=true, dirty=true) Debug: 5130 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tp Debug: 5131 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tp (valid=0). Debug: 5132 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tp (cacheable=true, valid=true, dirty=true) Debug: 5133 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t0 Debug: 5134 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x40027bd4 to t0 (valid=0). Debug: 5135 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40027bd4 to t0 (cacheable=true, valid=true, dirty=true) Debug: 5136 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t1 Debug: 5137 16228 riscv.c:5274 register_set(): [esp32c6] Write 0xffffffe0 to t1 (valid=0). Debug: 5138 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0xffffffe0 to t1 (cacheable=true, valid=true, dirty=true) Debug: 5139 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t2 Debug: 5140 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t2 (valid=0). Debug: 5141 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t2 (cacheable=true, valid=true, dirty=true) Debug: 5142 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore fp Debug: 5143 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to fp (valid=0). Debug: 5144 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to fp (cacheable=true, valid=true, dirty=true) Debug: 5145 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s1 Debug: 5146 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s1 (valid=0). Debug: 5147 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s1 (cacheable=true, valid=true, dirty=true) Debug: 5148 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a0 Debug: 5149 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x20000000 to a0 (valid=1). Debug: 5150 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x20000000 to a0 (cacheable=true, valid=true, dirty=true) Debug: 5151 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a1 Debug: 5152 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x60002000 to a1 (valid=0). Debug: 5153 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x60002000 to a1 (cacheable=true, valid=true, dirty=true) Debug: 5154 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a2 Debug: 5155 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000010 to a2 (valid=0). Debug: 5156 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x10 to a2 (cacheable=true, valid=true, dirty=true) Debug: 5157 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a3 Debug: 5158 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00010000 to a3 (valid=0). Debug: 5159 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x10000 to a3 (cacheable=true, valid=true, dirty=true) Debug: 5160 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a4 Debug: 5161 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x408021e0 to a4 (valid=0). Debug: 5162 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x408021e0 to a4 (cacheable=true, valid=true, dirty=true) Debug: 5163 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a5 Debug: 5164 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000004 to a5 (valid=0). Debug: 5165 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4 to a5 (cacheable=true, valid=true, dirty=true) Debug: 5166 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a6 Debug: 5167 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000008 to a6 (valid=0). Debug: 5168 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x8 to a6 (cacheable=true, valid=true, dirty=true) Debug: 5169 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a7 Debug: 5170 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x80000000 to a7 (valid=0). Debug: 5171 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x80000000 to a7 (cacheable=true, valid=true, dirty=true) Debug: 5172 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s2 Debug: 5173 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s2 (valid=0). Debug: 5174 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s2 (cacheable=true, valid=true, dirty=true) Debug: 5175 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s3 Debug: 5176 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s3 (valid=0). Debug: 5177 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s3 (cacheable=true, valid=true, dirty=true) Debug: 5178 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s4 Debug: 5179 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s4 (valid=0). Debug: 5180 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s4 (cacheable=true, valid=true, dirty=true) Debug: 5181 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s5 Debug: 5182 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s5 (valid=0). Debug: 5183 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s5 (cacheable=true, valid=true, dirty=true) Debug: 5184 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s6 Debug: 5185 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s6 (valid=0). Debug: 5186 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s6 (cacheable=true, valid=true, dirty=true) Debug: 5187 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s7 Debug: 5188 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s7 (valid=0). Debug: 5189 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s7 (cacheable=true, valid=true, dirty=true) Debug: 5190 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s8 Debug: 5191 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s8 (valid=0). Debug: 5192 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s8 (cacheable=true, valid=true, dirty=true) Debug: 5193 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s9 Debug: 5194 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s9 (valid=0). Debug: 5195 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s9 (cacheable=true, valid=true, dirty=true) Debug: 5196 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s10 Debug: 5197 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s10 (valid=0). Debug: 5198 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s10 (cacheable=true, valid=true, dirty=true) Debug: 5199 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s11 Debug: 5200 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s11 (valid=0). Debug: 5201 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s11 (cacheable=true, valid=true, dirty=true) Debug: 5202 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t3 Debug: 5203 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t3 (valid=0). Debug: 5204 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t3 (cacheable=true, valid=true, dirty=true) Debug: 5205 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t4 Debug: 5206 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t4 (valid=0). Debug: 5207 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t4 (cacheable=true, valid=true, dirty=true) Debug: 5208 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t5 Debug: 5209 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t5 (valid=0). Debug: 5210 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t5 (cacheable=true, valid=true, dirty=true) Debug: 5211 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t6 Debug: 5212 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t6 (valid=0). Debug: 5213 16228 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t6 (cacheable=true, valid=true, dirty=true) Debug: 5214 16228 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pc Debug: 5215 16228 riscv.c:5274 register_set(): [esp32c6] Write 0x40000000 to pc (valid=0). Debug: 5216 16228 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pc <- 0x40000000 (cacheable=false, valid=false, dirty=false) Debug: 5217 16228 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40000000 to register pc Debug: 5218 16228 riscv-013.c:4562 riscv013_set_register(): [esp32c6] writing PC to DPC: 0x40000000 Debug: 5219 16228 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40000000 to dpc Debug: 5220 16233 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 5221 16238 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40000000 Debug: 5222 16238 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40000000 to pc (cacheable=false, valid=false, dirty=false) Debug: 5223 16238 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mstatus Debug: 5224 16238 riscv.c:5274 register_set(): [esp32c6] Write 0x00201800 to mstatus (valid=0). Debug: 5225 16238 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mstatus <- 0x201800 (cacheable=false, valid=false, dirty=false) Debug: 5226 16238 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x201800 to register mstatus Debug: 5227 16238 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x201800 to mstatus Debug: 5228 16242 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 5229 16250 riscv-013.c:1532 register_write_direct(): [esp32c6] mstatus <- 0x201800 Debug: 5230 16250 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x201800 to mstatus (cacheable=false, valid=false, dirty=false) Debug: 5231 16250 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore misa Debug: 5232 16250 riscv.c:5274 register_set(): [esp32c6] Write 0x40903105 to misa (valid=0). Debug: 5233 16250 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: misa <- 0x40903105 (cacheable=false, valid=false, dirty=false) Debug: 5234 16250 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40903105 to register misa Debug: 5235 16250 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40903105 to misa [OpenOCD] Debug: 5236 16254 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301 Debug: 5237 16259 riscv-013.c:1532 register_write_direct(): [esp32c6] misa <- 0x40903105 Debug: 5238 16259 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40903105 to misa (cacheable=false, valid=false, dirty=false) Debug: 5239 16259 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mtvec Debug: 5240 16259 riscv.c:5274 register_set(): [esp32c6] Write 0x00000001 to mtvec (valid=0). Debug: 5241 16259 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mtvec <- 0x1 (cacheable=false, valid=false, dirty=false) Debug: 5242 16259 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x1 to register csr773 Debug: 5243 16259 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x1 to csr773 Debug: 5244 16263 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305 Debug: 5245 16270 riscv-013.c:1532 register_write_direct(): [esp32c6] csr773 <- 0x1 Debug: 5246 16270 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x1 to mtvec (cacheable=false, valid=false, dirty=false) Debug: 5247 16270 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mscratch Debug: 5248 16270 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mscratch (valid=0). Debug: 5249 16270 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mscratch <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5250 16270 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr832 Debug: 5251 16270 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr832 Debug: 5252 16275 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340 Debug: 5253 16283 riscv-013.c:1532 register_write_direct(): [esp32c6] csr832 <- 0x0 Debug: 5254 16283 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mscratch (cacheable=false, valid=false, dirty=false) Debug: 5255 16283 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mepc Debug: 5256 16283 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mepc (valid=0). Debug: 5257 16283 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mepc <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5258 16283 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register mepc Debug: 5259 16283 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to mepc Debug: 5260 16286 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341 Debug: 5261 16292 riscv-013.c:1532 register_write_direct(): [esp32c6] mepc <- 0x0 Debug: 5262 16292 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mepc (cacheable=false, valid=false, dirty=false) Debug: 5263 16292 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mcause Debug: 5264 16292 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mcause (valid=0). Debug: 5265 16292 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mcause <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5266 16292 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register mcause Debug: 5267 16292 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to mcause Debug: 5268 16295 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342 Debug: 5269 16302 riscv-013.c:1532 register_write_direct(): [esp32c6] mcause <- 0x0 Debug: 5270 16302 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mcause (cacheable=false, valid=false, dirty=false) Debug: 5271 16302 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mtval Debug: 5272 16302 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mtval (valid=0). Debug: 5273 16302 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mtval <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5274 16302 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr835 Debug: 5275 16302 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr835 Debug: 5276 16305 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343 Debug: 5277 16309 riscv-013.c:1532 register_write_direct(): [esp32c6] csr835 <- 0x0 Debug: 5278 16309 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mtval (cacheable=false, valid=false, dirty=false) Debug: 5279 16309 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg0 Debug: 5280 16309 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg0 (valid=0). Debug: 5281 16309 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5282 16309 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr928 Debug: 5283 16309 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr928 [OpenOCD] Debug: 5284 16313 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0 Debug: 5285 16317 riscv-013.c:1532 register_write_direct(): [esp32c6] csr928 <- 0x0 Debug: 5286 16317 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg0 (cacheable=false, valid=false, dirty=false) Debug: 5287 16317 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg1 Debug: 5288 16317 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg1 (valid=0). Debug: 5289 16317 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5290 16317 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr929 Debug: 5291 16317 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr929 Debug: 5292 16321 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1 Debug: 5293 16326 riscv-013.c:1532 register_write_direct(): [esp32c6] csr929 <- 0x0 Debug: 5294 16326 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg1 (cacheable=false, valid=false, dirty=false) Debug: 5295 16326 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg2 Debug: 5296 16326 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg2 (valid=0). Debug: 5297 16326 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5298 16326 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr930 Debug: 5299 16326 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr930 Debug: 5300 16328 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2 Debug: 5301 16334 riscv-013.c:1532 register_write_direct(): [esp32c6] csr930 <- 0x0 Debug: 5302 16334 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg2 (cacheable=false, valid=false, dirty=false) Debug: 5303 16334 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg3 Debug: 5304 16334 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg3 (valid=0). Debug: 5305 16334 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5306 16334 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr931 Debug: 5307 16334 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr931 Debug: 5308 16338 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3 Debug: 5309 16344 riscv-013.c:1532 register_write_direct(): [esp32c6] csr931 <- 0x0 Debug: 5310 16344 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg3 (cacheable=false, valid=false, dirty=false) Debug: 5311 16344 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr0 Debug: 5312 16344 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr0 (valid=0). Debug: 5313 16344 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5314 16344 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr944 Debug: 5315 16344 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr944 Debug: 5316 16348 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0 Debug: 5317 16355 riscv-013.c:1532 register_write_direct(): [esp32c6] csr944 <- 0x0 Debug: 5318 16355 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr0 (cacheable=false, valid=false, dirty=false) Debug: 5319 16355 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr1 Debug: 5320 16355 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr1 (valid=0). Debug: 5321 16355 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5322 16355 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr945 Debug: 5323 16355 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr945 Debug: 5324 16366 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1 Debug: 5325 16374 riscv-013.c:1532 register_write_direct(): [esp32c6] csr945 <- 0x0 Debug: 5326 16374 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr1 (cacheable=false, valid=false, dirty=false) Debug: 5327 16374 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr2 Debug: 5328 16374 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr2 (valid=0). Debug: 5329 16374 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5330 16374 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr946 Debug: 5331 16374 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr946 Debug: 5332 16377 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2 Debug: 5333 16386 riscv-013.c:1532 register_write_direct(): [esp32c6] csr946 <- 0x0 Debug: 5334 16386 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr2 (cacheable=false, valid=false, dirty=false) Debug: 5335 16386 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr3 Debug: 5336 16386 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr3 (valid=0). Debug: 5337 16386 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5338 16386 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr947 Debug: 5339 16386 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr947 [OpenOCD] Debug: 5340 16390 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3 Debug: 5341 16396 riscv-013.c:1532 register_write_direct(): [esp32c6] csr947 <- 0x0 Debug: 5342 16396 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr3 (cacheable=false, valid=false, dirty=false) Debug: 5343 16396 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr4 Debug: 5344 16396 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr4 (valid=0). Debug: 5345 16396 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5346 16396 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr948 Debug: 5347 16396 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr948 Debug: 5348 16402 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4 Debug: 5349 16411 riscv-013.c:1532 register_write_direct(): [esp32c6] csr948 <- 0x0 Debug: 5350 16411 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr4 (cacheable=false, valid=false, dirty=false) Debug: 5351 16411 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr5 Debug: 5352 16411 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr5 (valid=0). Debug: 5353 16411 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5354 16411 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr949 Debug: 5355 16411 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr949 Debug: 5356 16417 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5 Debug: 5357 16424 riscv-013.c:1532 register_write_direct(): [esp32c6] csr949 <- 0x0 Debug: 5358 16424 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr5 (cacheable=false, valid=false, dirty=false) Debug: 5359 16424 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr6 Debug: 5360 16424 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr6 (valid=0). Debug: 5361 16424 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5362 16424 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr950 Debug: 5363 16424 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr950 Debug: 5364 16429 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6 Debug: 5365 16440 riscv-013.c:1532 register_write_direct(): [esp32c6] csr950 <- 0x0 Debug: 5366 16440 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr6 (cacheable=false, valid=false, dirty=false) Debug: 5367 16440 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr7 Debug: 5368 16440 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr7 (valid=0). Debug: 5369 16440 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5370 16440 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr951 Debug: 5371 16440 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr951 Debug: 5372 16443 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7 Debug: 5373 16447 riscv-013.c:1532 register_write_direct(): [esp32c6] csr951 <- 0x0 Debug: 5374 16447 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr7 (cacheable=false, valid=false, dirty=false) Debug: 5375 16447 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr8 Debug: 5376 16447 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr8 (valid=0). Debug: 5377 16447 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5378 16447 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr952 Debug: 5379 16447 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr952 Debug: 5380 16450 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8 Debug: 5381 16454 riscv-013.c:1532 register_write_direct(): [esp32c6] csr952 <- 0x0 Debug: 5382 16454 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr8 (cacheable=false, valid=false, dirty=false) Debug: 5383 16454 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr9 Debug: 5384 16454 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr9 (valid=0). Debug: 5385 16454 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5386 16454 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr953 Debug: 5387 16454 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr953 Debug: 5388 16457 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9 Debug: 5389 16461 riscv-013.c:1532 register_write_direct(): [esp32c6] csr953 <- 0x0 Debug: 5390 16461 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr9 (cacheable=false, valid=false, dirty=false) Debug: 5391 16461 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr10 Debug: 5392 16461 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr10 (valid=0). Debug: 5393 16461 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5394 16461 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr954 Debug: 5395 16461 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr954 [OpenOCD] Debug: 5396 16464 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba Debug: 5397 16471 riscv-013.c:1532 register_write_direct(): [esp32c6] csr954 <- 0x0 Debug: 5398 16471 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr10 (cacheable=false, valid=false, dirty=false) Debug: 5399 16471 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr11 Debug: 5400 16471 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr11 (valid=0). Debug: 5401 16471 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5402 16471 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr955 Debug: 5403 16471 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr955 Debug: 5404 16476 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb Debug: 5405 16495 riscv-013.c:1532 register_write_direct(): [esp32c6] csr955 <- 0x0 Debug: 5406 16495 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr11 (cacheable=false, valid=false, dirty=false) Debug: 5407 16495 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr12 Debug: 5408 16495 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr12 (valid=0). Debug: 5409 16495 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5410 16495 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr956 Debug: 5411 16495 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr956 Debug: 5412 16504 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc Debug: 5413 16508 riscv-013.c:1532 register_write_direct(): [esp32c6] csr956 <- 0x0 Debug: 5414 16508 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr12 (cacheable=false, valid=false, dirty=false) Debug: 5415 16508 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr13 Debug: 5416 16508 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr13 (valid=0). Debug: 5417 16508 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5418 16508 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr957 Debug: 5419 16508 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr957 Debug: 5420 16518 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd [OpenOCD] Debug: 5421 16544 riscv-013.c:1532 register_write_direct(): [esp32c6] csr957 <- 0x0 Debug: 5422 16544 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr13 (cacheable=false, valid=false, dirty=false) Debug: 5423 16544 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr14 Debug: 5424 16544 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr14 (valid=0). Debug: 5425 16544 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5426 16544 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr958 Debug: 5427 16544 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr958 Debug: 5428 16568 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be Debug: 5429 16575 riscv-013.c:1532 register_write_direct(): [esp32c6] csr958 <- 0x0 Debug: 5430 16575 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr14 (cacheable=false, valid=false, dirty=false) Debug: 5431 16575 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr15 Debug: 5432 16575 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr15 (valid=0). Debug: 5433 16575 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5434 16575 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr959 Debug: 5435 16575 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr959 Debug: 5436 16581 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf Debug: 5437 16588 riscv-013.c:1532 register_write_direct(): [esp32c6] csr959 <- 0x0 Debug: 5438 16588 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr15 (cacheable=false, valid=false, dirty=false) Debug: 5439 16588 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tselect Debug: 5440 16588 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tselect (valid=0). Debug: 5441 16588 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5442 16588 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tselect Debug: 5443 16588 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tselect Debug: 5444 16592 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 5445 16596 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x0 Debug: 5446 16596 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tselect (cacheable=false, valid=false, dirty=false) Debug: 5447 16596 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tdata1 Debug: 5448 16596 riscv.c:5274 register_set(): [esp32c6] Write 0x23e00000 to tdata1 (valid=0). Debug: 5449 16596 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tdata1 <- 0x23e00000 (cacheable=false, valid=false, dirty=false) Debug: 5450 16596 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x23e00000 to register tdata1 Debug: 5451 16596 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x23e00000 to tdata1 Debug: 5452 16599 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1 Debug: 5453 16603 riscv-013.c:1532 register_write_direct(): [esp32c6] tdata1 <- 0x23e00000 Debug: 5454 16603 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x23e00000 to tdata1 (cacheable=false, valid=false, dirty=false) Debug: 5455 16603 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tdata2 Debug: 5456 16603 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tdata2 (valid=0). Debug: 5457 16603 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tdata2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5458 16603 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tdata2 Debug: 5459 16603 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tdata2 [OpenOCD] Debug: 5460 16606 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2 Debug: 5461 16611 riscv-013.c:1532 register_write_direct(): [esp32c6] tdata2 <- 0x0 Debug: 5462 16611 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tdata2 (cacheable=false, valid=false, dirty=false) Debug: 5463 16611 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tcontrol Debug: 5464 16611 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tcontrol (valid=0). Debug: 5465 16611 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tcontrol <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5466 16611 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr1957 Debug: 5467 16611 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr1957 Debug: 5468 16619 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5 Debug: 5469 16630 riscv-013.c:1532 register_write_direct(): [esp32c6] csr1957 <- 0x0 Debug: 5470 16630 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tcontrol (cacheable=false, valid=false, dirty=false) Debug: 5471 16630 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dcsr Debug: 5472 16630 riscv.c:5274 register_set(): [esp32c6] Write 0x400090c3 to dcsr (valid=0). Debug: 5473 16630 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dcsr <- 0x400090c3 (cacheable=false, valid=false, dirty=false) Debug: 5474 16630 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x400090c3 to register dcsr Debug: 5475 16630 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x400090c3 to dcsr Debug: 5476 16634 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 5477 16638 riscv-013.c:1532 register_write_direct(): [esp32c6] dcsr <- 0x400090c3 Debug: 5478 16638 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x400090c3 to dcsr (cacheable=false, valid=false, dirty=false) Debug: 5479 16638 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dpc Debug: 5480 16638 riscv.c:5274 register_set(): [esp32c6] Write 0x40000000 to dpc (valid=0). Debug: 5481 16638 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40000000 to dpc (cacheable=true, valid=true, dirty=true) Debug: 5482 16638 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dscratch0 Debug: 5483 16638 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to dscratch0 (valid=0). Debug: 5484 16638 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dscratch0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5485 16638 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register dscratch0 Debug: 5486 16638 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to dscratch0 Debug: 5487 16641 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2 Debug: 5488 16649 riscv-013.c:1532 register_write_direct(): [esp32c6] dscratch0 <- 0x0 Debug: 5489 16649 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to dscratch0 (cacheable=false, valid=false, dirty=false) Debug: 5490 16649 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dscratch1 Debug: 5491 16649 riscv.c:5274 register_set(): [esp32c6] Write 0x20000000 to dscratch1 (valid=0). Debug: 5492 16649 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dscratch1 <- 0x20000000 (cacheable=false, valid=false, dirty=false) Debug: 5493 16649 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x20000000 to register csr1971 Debug: 5494 16649 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x20000000 to csr1971 Debug: 5495 16656 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3 Debug: 5496 16662 riscv-013.c:1532 register_write_direct(): [esp32c6] csr1971 <- 0x20000000 Debug: 5497 16662 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x20000000 to dscratch1 (cacheable=false, valid=false, dirty=false) Debug: 5498 16662 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpcer Debug: 5499 16662 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_mpcer (valid=0). Debug: 5500 16662 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpcer <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5501 16662 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2016 Debug: 5502 16662 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2016 Debug: 5503 16665 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e0 Debug: 5504 16670 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2016 <- 0x0 Debug: 5505 16670 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_mpcer (cacheable=false, valid=false, dirty=false) Debug: 5506 16670 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpcmr Debug: 5507 16670 riscv.c:5274 register_set(): [esp32c6] Write 0x00000003 to csr_mpcmr (valid=0). Debug: 5508 16670 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpcmr <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 5509 16670 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register csr2017 Debug: 5510 16670 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to csr2017 Debug: 5511 16673 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e1 Debug: 5512 16677 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2017 <- 0x3 Debug: 5513 16677 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to csr_mpcmr (cacheable=false, valid=false, dirty=false) Debug: 5514 16677 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpccr Debug: 5515 16677 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_mpccr (valid=0). Debug: 5516 16677 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpccr <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5517 16677 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2018 Debug: 5518 16677 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2018 [OpenOCD] Debug: 5519 16680 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e2 Debug: 5520 16683 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2018 <- 0x0 Debug: 5521 16684 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_mpccr (cacheable=false, valid=false, dirty=false) Debug: 5522 16684 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_oen Debug: 5523 16684 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_oen (valid=0). Debug: 5524 16684 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_oen <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5525 16684 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2051 Debug: 5526 16684 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2051 Debug: 5527 16688 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230803; access register, size=32, postexec=0, transfer=1, write=1, regno=0x803 Debug: 5528 16695 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2051 <- 0x0 Debug: 5529 16695 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_oen (cacheable=false, valid=false, dirty=false) Debug: 5530 16695 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_in Debug: 5531 16695 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_in (valid=0). Debug: 5532 16695 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_in <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5533 16695 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2052 Debug: 5534 16695 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2052 Debug: 5535 16698 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230804; access register, size=32, postexec=0, transfer=1, write=1, regno=0x804 Debug: 5536 16704 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2052 <- 0x0 Debug: 5537 16704 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_in (cacheable=false, valid=false, dirty=false) Debug: 5538 16704 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_out Debug: 5539 16704 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_out (valid=0). Debug: 5540 16704 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_out <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5541 16704 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2053 Debug: 5542 16704 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2053 Debug: 5543 16707 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230805; access register, size=32, postexec=0, transfer=1, write=1, regno=0x805 Debug: 5544 16757 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2053 <- 0x0 Debug: 5545 16757 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_out (cacheable=false, valid=false, dirty=false) Debug: 5546 16757 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg0 Debug: 5547 16757 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg0 (valid=0). Debug: 5548 16757 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5549 16757 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3008 Debug: 5550 16757 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3008 [OpenOCD] Debug: 5551 16766 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc0; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc0 Debug: 5552 16772 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3008 <- 0x0 Debug: 5553 16772 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg0 (cacheable=false, valid=false, dirty=false) Debug: 5554 16772 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg1 Debug: 5555 16772 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg1 (valid=0). Debug: 5556 16772 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5557 16772 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3009 Debug: 5558 16772 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3009 Debug: 5559 16777 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc1; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc1 Debug: 5560 16796 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3009 <- 0x0 Debug: 5561 16796 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg1 (cacheable=false, valid=false, dirty=false) Debug: 5562 16796 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg2 Debug: 5563 16796 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg2 (valid=0). Debug: 5564 16796 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5565 16796 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3010 Debug: 5566 16796 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3010 Debug: 5567 16802 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc2; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc2 Debug: 5568 16812 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3010 <- 0x0 Debug: 5569 16812 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg2 (cacheable=false, valid=false, dirty=false) Debug: 5570 16812 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg3 Debug: 5571 16812 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg3 (valid=0). Debug: 5572 16812 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5573 16812 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3011 Debug: 5574 16812 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3011 Debug: 5575 16817 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc3; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc3 Debug: 5576 16824 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3011 <- 0x0 Debug: 5577 16824 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg3 (cacheable=false, valid=false, dirty=false) Debug: 5578 16824 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg4 Debug: 5579 16824 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg4 (valid=0). Debug: 5580 16824 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5581 16824 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3012 Debug: 5582 16824 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3012 Debug: 5583 16826 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc4; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc4 Debug: 5584 16831 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3012 <- 0x0 Debug: 5585 16831 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg4 (cacheable=false, valid=false, dirty=false) Debug: 5586 16831 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg5 Debug: 5587 16831 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg5 (valid=0). Debug: 5588 16831 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5589 16831 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3013 Debug: 5590 16831 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3013 Debug: 5591 16834 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc5; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc5 Debug: 5592 16839 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3013 <- 0x0 Debug: 5593 16839 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg5 (cacheable=false, valid=false, dirty=false) Debug: 5594 16839 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg6 Debug: 5595 16839 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg6 (valid=0). Debug: 5596 16839 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5597 16839 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3014 Debug: 5598 16839 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3014 [OpenOCD] Debug: 5599 16843 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc6; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc6 Debug: 5600 16847 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3014 <- 0x0 Debug: 5601 16847 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg6 (cacheable=false, valid=false, dirty=false) Debug: 5602 16847 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg7 Debug: 5603 16847 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg7 (valid=0). Debug: 5604 16847 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5605 16847 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3015 Debug: 5606 16847 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3015 Debug: 5607 16851 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc7; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc7 Debug: 5608 16865 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3015 <- 0x0 Debug: 5609 16865 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg7 (cacheable=false, valid=false, dirty=false) Debug: 5610 16865 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg8 Debug: 5611 16865 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg8 (valid=0). Debug: 5612 16865 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5613 16865 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3016 Debug: 5614 16865 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3016 Debug: 5615 16869 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc8; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc8 Debug: 5616 16875 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3016 <- 0x0 Debug: 5617 16875 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg8 (cacheable=false, valid=false, dirty=false) Debug: 5618 16875 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg9 Debug: 5619 16875 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg9 (valid=0). Debug: 5620 16875 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5621 16875 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3017 Debug: 5622 16875 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3017 Debug: 5623 16879 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc9; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc9 Debug: 5624 16887 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3017 <- 0x0 Debug: 5625 16887 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg9 (cacheable=false, valid=false, dirty=false) Debug: 5626 16887 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg10 Debug: 5627 16887 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg10 (valid=0). Debug: 5628 16887 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5629 16887 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3018 Debug: 5630 16887 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3018 Debug: 5631 16892 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bca; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbca Debug: 5632 16897 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3018 <- 0x0 Debug: 5633 16897 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg10 (cacheable=false, valid=false, dirty=false) Debug: 5634 16897 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg11 Debug: 5635 16897 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg11 (valid=0). Debug: 5636 16897 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5637 16897 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3019 Debug: 5638 16897 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3019 Debug: 5639 16899 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcb; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcb [OpenOCD] Debug: 5640 16905 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3019 <- 0x0 Debug: 5641 16905 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg11 (cacheable=false, valid=false, dirty=false) Debug: 5642 16905 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg12 Debug: 5643 16905 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg12 (valid=0). Debug: 5644 16905 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5645 16905 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3020 Debug: 5646 16905 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3020 Debug: 5647 16908 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcc; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcc Debug: 5648 16912 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3020 <- 0x0 Debug: 5649 16912 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg12 (cacheable=false, valid=false, dirty=false) Debug: 5650 16912 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg13 Debug: 5651 16912 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg13 (valid=0). Debug: 5652 16912 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5653 16912 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3021 Debug: 5654 16912 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3021 Debug: 5655 16915 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcd; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcd Debug: 5656 16921 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3021 <- 0x0 Debug: 5657 16922 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg13 (cacheable=false, valid=false, dirty=false) Debug: 5658 16922 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg14 Debug: 5659 16922 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg14 (valid=0). Debug: 5660 16922 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5661 16922 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3022 Debug: 5662 16922 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3022 Debug: 5663 16926 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bce; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbce Debug: 5664 16931 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3022 <- 0x0 Debug: 5665 16931 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg14 (cacheable=false, valid=false, dirty=false) Debug: 5666 16931 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg15 Debug: 5667 16931 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg15 (valid=0). Debug: 5668 16931 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5669 16931 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3023 Debug: 5670 16931 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3023 Debug: 5671 16941 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcf; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcf Debug: 5672 16950 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3023 <- 0x0 Debug: 5673 16950 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg15 (cacheable=false, valid=false, dirty=false) Debug: 5674 16950 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr0 Debug: 5675 16950 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr0 (valid=0). Debug: 5676 16950 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5677 16950 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3024 Debug: 5678 16950 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3024 Debug: 5679 16954 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd0; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd0 Debug: 5680 16958 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3024 <- 0x0 Debug: 5681 16958 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr0 (cacheable=false, valid=false, dirty=false) Debug: 5682 16958 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr1 Debug: 5683 16958 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr1 (valid=0). Debug: 5684 16958 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5685 16958 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3025 Debug: 5686 16958 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3025 Debug: 5687 16960 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd1; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd1 Debug: 5688 16964 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3025 <- 0x0 Debug: 5689 16964 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr1 (cacheable=false, valid=false, dirty=false) Debug: 5690 16964 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr2 Debug: 5691 16964 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr2 (valid=0). Debug: 5692 16964 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5693 16964 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3026 Debug: 5694 16964 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3026 Debug: 5695 16967 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd2; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd2 Debug: 5696 16974 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3026 <- 0x0 Debug: 5697 16974 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr2 (cacheable=false, valid=false, dirty=false) Debug: 5698 16974 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr3 Debug: 5699 16974 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr3 (valid=0). Debug: 5700 16974 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5701 16974 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3027 Debug: 5702 16974 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3027 Debug: 5703 16979 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd3; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd3 [OpenOCD] Debug: 5704 16986 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3027 <- 0x0 Debug: 5705 16986 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr3 (cacheable=false, valid=false, dirty=false) Debug: 5706 16986 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr4 Debug: 5707 16986 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr4 (valid=0). Debug: 5708 16986 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5709 16986 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3028 Debug: 5710 16986 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3028 Debug: 5711 16991 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd4; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd4 Debug: 5712 17011 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3028 <- 0x0 Debug: 5713 17011 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr4 (cacheable=false, valid=false, dirty=false) Debug: 5714 17011 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr5 Debug: 5715 17011 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr5 (valid=0). Debug: 5716 17011 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5717 17011 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3029 Debug: 5718 17011 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3029 Debug: 5719 17016 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd5; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd5 Debug: 5720 17022 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3029 <- 0x0 Debug: 5721 17022 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr5 (cacheable=false, valid=false, dirty=false) Debug: 5722 17022 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr6 Debug: 5723 17022 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr6 (valid=0). Debug: 5724 17022 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5725 17022 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3030 Debug: 5726 17022 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3030 Debug: 5727 17037 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd6; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd6 Debug: 5728 17043 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3030 <- 0x0 Debug: 5729 17043 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr6 (cacheable=false, valid=false, dirty=false) Debug: 5730 17043 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr7 Debug: 5731 17043 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr7 (valid=0). Debug: 5732 17043 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5733 17043 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3031 Debug: 5734 17043 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3031 Debug: 5735 17050 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd7; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd7 [OpenOCD] Debug: 5736 17078 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3031 <- 0x0 Debug: 5737 17078 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr7 (cacheable=false, valid=false, dirty=false) Debug: 5738 17078 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr8 Debug: 5739 17078 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr8 (valid=0). Debug: 5740 17078 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5741 17078 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3032 Debug: 5742 17078 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3032 Debug: 5743 17082 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd8; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd8 Debug: 5744 17090 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3032 <- 0x0 Debug: 5745 17090 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr8 (cacheable=false, valid=false, dirty=false) Debug: 5746 17090 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr9 Debug: 5747 17090 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr9 (valid=0). Debug: 5748 17090 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5749 17090 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3033 Debug: 5750 17090 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3033 Debug: 5751 17095 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd9; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd9 Debug: 5752 17109 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3033 <- 0x0 Debug: 5753 17109 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr9 (cacheable=false, valid=false, dirty=false) Debug: 5754 17109 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr10 Debug: 5755 17109 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr10 (valid=0). Debug: 5756 17109 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5757 17109 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3034 Debug: 5758 17109 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3034 Debug: 5759 17114 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bda; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbda Debug: 5760 17121 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3034 <- 0x0 Debug: 5761 17121 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr10 (cacheable=false, valid=false, dirty=false) Debug: 5762 17121 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr11 Debug: 5763 17121 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr11 (valid=0). Debug: 5764 17121 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5765 17121 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3035 Debug: 5766 17121 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3035 Debug: 5767 17124 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdb; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdb Debug: 5768 17129 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3035 <- 0x0 Debug: 5769 17129 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr11 (cacheable=false, valid=false, dirty=false) Debug: 5770 17129 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr12 Debug: 5771 17129 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr12 (valid=0). Debug: 5772 17129 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5773 17129 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3036 Debug: 5774 17129 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3036 Debug: 5775 17131 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdc; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdc [OpenOCD] Debug: 5776 17138 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3036 <- 0x0 Debug: 5777 17138 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr12 (cacheable=false, valid=false, dirty=false) Debug: 5778 17138 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr13 Debug: 5779 17138 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr13 (valid=0). Debug: 5780 17138 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5781 17138 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3037 Debug: 5782 17138 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3037 Debug: 5783 17140 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdd; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdd Debug: 5784 17146 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3037 <- 0x0 Debug: 5785 17146 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr13 (cacheable=false, valid=false, dirty=false) Debug: 5786 17146 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr14 Debug: 5787 17146 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr14 (valid=0). Debug: 5788 17146 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5789 17146 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3038 Debug: 5790 17146 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3038 Debug: 5791 17149 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bde; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbde Debug: 5792 17157 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3038 <- 0x0 Debug: 5793 17157 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr14 (cacheable=false, valid=false, dirty=false) Debug: 5794 17157 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr15 Debug: 5795 17157 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr15 (valid=0). Debug: 5796 17157 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 5797 17157 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3039 Debug: 5798 17157 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3039 Debug: 5799 17161 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdf; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdf Debug: 5800 17165 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3039 <- 0x0 Debug: 5801 17165 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr15 (cacheable=false, valid=false, dirty=false) Debug: 5802 17165 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore hpmcounter16 Debug: 5803 17165 riscv.c:5274 register_set(): [esp32c6] Write 0x00000003 to hpmcounter16 (valid=0). Debug: 5804 17165 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: hpmcounter16 <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 5805 17165 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register csr3088 Debug: 5806 17165 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to csr3088 Debug: 5807 17170 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10 Debug: 5808 17174 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3088 <- 0x3 Debug: 5809 17174 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to hpmcounter16 (cacheable=false, valid=false, dirty=false) Debug: 5810 17174 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore priv Debug: 5811 17174 riscv.c:5274 register_set(): [esp32c6] Write 0x03 to priv (valid=0). Debug: 5812 17174 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: priv <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 5813 17174 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register priv Debug: 5814 17174 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 5815 17174 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 5816 17181 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 5817 17181 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x400090c3 to dcsr Debug: 5818 17185 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 5819 17189 riscv-013.c:1532 register_write_direct(): [esp32c6] dcsr <- 0x400090c3 Debug: 5820 17189 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to priv (cacheable=false, valid=false, dirty=false) Debug: 5821 17189 riscv.c:1575 riscv_flush_registers(): [esp32c6] dpc is dirty; write back 0x40000000 Debug: 5822 17189 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40000000 to register dpc Debug: 5823 17189 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40000000 to dpc [OpenOCD] Debug: 5824 17199 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 5825 17208 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40000000 Debug: 5826 17208 riscv.c:1575 riscv_flush_registers(): [esp32c6] t6 is dirty; write back 0x0 Debug: 5827 17208 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t6 Debug: 5828 17208 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t6 Debug: 5829 17215 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f Debug: 5830 17222 riscv-013.c:1532 register_write_direct(): [esp32c6] t6 <- 0x0 Debug: 5831 17222 riscv.c:1575 riscv_flush_registers(): [esp32c6] t5 is dirty; write back 0x0 Debug: 5832 17223 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t5 Debug: 5833 17223 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t5 Debug: 5834 17226 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e Debug: 5835 17234 riscv-013.c:1532 register_write_direct(): [esp32c6] t5 <- 0x0 Debug: 5836 17234 riscv.c:1575 riscv_flush_registers(): [esp32c6] t4 is dirty; write back 0x0 Debug: 5837 17234 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t4 Debug: 5838 17234 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t4 Debug: 5839 17239 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d Debug: 5840 17246 riscv-013.c:1532 register_write_direct(): [esp32c6] t4 <- 0x0 Debug: 5841 17246 riscv.c:1575 riscv_flush_registers(): [esp32c6] t3 is dirty; write back 0x0 Debug: 5842 17246 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t3 Debug: 5843 17246 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t3 Debug: 5844 17250 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c Debug: 5845 17254 riscv-013.c:1532 register_write_direct(): [esp32c6] t3 <- 0x0 Debug: 5846 17254 riscv.c:1575 riscv_flush_registers(): [esp32c6] s11 is dirty; write back 0x0 Debug: 5847 17254 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s11 Debug: 5848 17254 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s11 Debug: 5849 17257 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b Debug: 5850 17265 riscv-013.c:1532 register_write_direct(): [esp32c6] s11 <- 0x0 Debug: 5851 17265 riscv.c:1575 riscv_flush_registers(): [esp32c6] s10 is dirty; write back 0x0 Debug: 5852 17265 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s10 Debug: 5853 17265 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s10 [OpenOCD] Debug: 5854 17270 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a Debug: 5855 17274 riscv-013.c:1532 register_write_direct(): [esp32c6] s10 <- 0x0 Debug: 5856 17274 riscv.c:1575 riscv_flush_registers(): [esp32c6] s9 is dirty; write back 0x0 Debug: 5857 17274 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s9 Debug: 5858 17274 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s9 Debug: 5859 17278 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019 Debug: 5860 17283 riscv-013.c:1532 register_write_direct(): [esp32c6] s9 <- 0x0 Debug: 5861 17283 riscv.c:1575 riscv_flush_registers(): [esp32c6] s8 is dirty; write back 0x0 Debug: 5862 17283 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s8 Debug: 5863 17283 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s8 Debug: 5864 17287 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018 Debug: 5865 17291 riscv-013.c:1532 register_write_direct(): [esp32c6] s8 <- 0x0 Debug: 5866 17291 riscv.c:1575 riscv_flush_registers(): [esp32c6] s7 is dirty; write back 0x0 Debug: 5867 17291 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s7 Debug: 5868 17291 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s7 Debug: 5869 17294 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017 Debug: 5870 17330 riscv-013.c:1532 register_write_direct(): [esp32c6] s7 <- 0x0 Debug: 5871 17330 riscv.c:1575 riscv_flush_registers(): [esp32c6] s6 is dirty; write back 0x0 Debug: 5872 17330 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s6 Debug: 5873 17330 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s6 Debug: 5874 17338 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016 [OpenOCD] Debug: 5875 17347 riscv-013.c:1532 register_write_direct(): [esp32c6] s6 <- 0x0 Debug: 5876 17347 riscv.c:1575 riscv_flush_registers(): [esp32c6] s5 is dirty; write back 0x0 Debug: 5877 17347 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s5 Debug: 5878 17347 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s5 Debug: 5879 17350 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015 Debug: 5880 17355 riscv-013.c:1532 register_write_direct(): [esp32c6] s5 <- 0x0 Debug: 5881 17355 riscv.c:1575 riscv_flush_registers(): [esp32c6] s4 is dirty; write back 0x0 Debug: 5882 17355 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s4 Debug: 5883 17355 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s4 Debug: 5884 17370 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014 Debug: 5885 17376 riscv-013.c:1532 register_write_direct(): [esp32c6] s4 <- 0x0 Debug: 5886 17376 riscv.c:1575 riscv_flush_registers(): [esp32c6] s3 is dirty; write back 0x0 Debug: 5887 17376 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s3 Debug: 5888 17376 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s3 Debug: 5889 17380 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013 Debug: 5890 17386 riscv-013.c:1532 register_write_direct(): [esp32c6] s3 <- 0x0 Debug: 5891 17386 riscv.c:1575 riscv_flush_registers(): [esp32c6] s2 is dirty; write back 0x0 Debug: 5892 17386 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s2 Debug: 5893 17386 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s2 Debug: 5894 17390 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012 Debug: 5895 17394 riscv-013.c:1532 register_write_direct(): [esp32c6] s2 <- 0x0 Debug: 5896 17394 riscv.c:1575 riscv_flush_registers(): [esp32c6] a7 is dirty; write back 0x80000000 Debug: 5897 17394 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x80000000 to register a7 Debug: 5898 17394 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x80000000 to a7 Debug: 5899 17397 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 5900 17400 riscv-013.c:1532 register_write_direct(): [esp32c6] a7 <- 0x80000000 Debug: 5901 17400 riscv.c:1575 riscv_flush_registers(): [esp32c6] a6 is dirty; write back 0x8 Debug: 5902 17400 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x8 to register a6 Debug: 5903 17400 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x8 to a6 Debug: 5904 17403 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010 [OpenOCD] Debug: 5905 17413 riscv-013.c:1532 register_write_direct(): [esp32c6] a6 <- 0x8 Debug: 5906 17413 riscv.c:1575 riscv_flush_registers(): [esp32c6] a5 is dirty; write back 0x4 Debug: 5907 17413 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4 to register a5 Debug: 5908 17413 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4 to a5 Debug: 5909 17424 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f Debug: 5910 17431 riscv-013.c:1532 register_write_direct(): [esp32c6] a5 <- 0x4 Debug: 5911 17431 riscv.c:1575 riscv_flush_registers(): [esp32c6] a4 is dirty; write back 0x408021e0 Debug: 5912 17431 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x408021e0 to register a4 Debug: 5913 17431 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x408021e0 to a4 Debug: 5914 17436 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e Debug: 5915 17444 riscv-013.c:1532 register_write_direct(): [esp32c6] a4 <- 0x408021e0 Debug: 5916 17444 riscv.c:1575 riscv_flush_registers(): [esp32c6] a3 is dirty; write back 0x10000 Debug: 5917 17444 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x10000 to register a3 Debug: 5918 17444 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x10000 to a3 Debug: 5919 17452 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d Debug: 5920 17464 riscv-013.c:1532 register_write_direct(): [esp32c6] a3 <- 0x10000 Debug: 5921 17464 riscv.c:1575 riscv_flush_registers(): [esp32c6] a2 is dirty; write back 0x10 Debug: 5922 17464 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x10 to register a2 Debug: 5923 17464 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x10 to a2 Debug: 5924 17468 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 5925 17472 riscv-013.c:1532 register_write_direct(): [esp32c6] a2 <- 0x10 Debug: 5926 17472 riscv.c:1575 riscv_flush_registers(): [esp32c6] a1 is dirty; write back 0x60002000 Debug: 5927 17472 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x60002000 to register a1 Debug: 5928 17472 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x60002000 to a1 Debug: 5929 17475 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 5930 17481 riscv-013.c:1532 register_write_direct(): [esp32c6] a1 <- 0x60002000 Debug: 5931 17481 riscv.c:1575 riscv_flush_registers(): [esp32c6] a0 is dirty; write back 0x20000000 Debug: 5932 17481 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x20000000 to register a0 Debug: 5933 17481 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x20000000 to a0 Debug: 5934 17486 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a [OpenOCD] Debug: 5935 17490 riscv-013.c:1532 register_write_direct(): [esp32c6] a0 <- 0x20000000 Debug: 5936 17490 riscv.c:1575 riscv_flush_registers(): [esp32c6] s1 is dirty; write back 0x0 Debug: 5937 17490 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s1 Debug: 5938 17490 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s1 Debug: 5939 17494 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 5940 17500 riscv-013.c:1532 register_write_direct(): [esp32c6] s1 <- 0x0 Debug: 5941 17500 riscv.c:1575 riscv_flush_registers(): [esp32c6] fp is dirty; write back 0x0 Debug: 5942 17500 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s0 Debug: 5943 17500 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s0 Debug: 5944 17506 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 5945 17511 riscv-013.c:1532 register_write_direct(): [esp32c6] s0 <- 0x0 Debug: 5946 17511 riscv.c:1575 riscv_flush_registers(): [esp32c6] t2 is dirty; write back 0x0 Debug: 5947 17511 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t2 Debug: 5948 17511 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t2 Debug: 5949 17515 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007 Debug: 5950 17521 riscv-013.c:1532 register_write_direct(): [esp32c6] t2 <- 0x0 Debug: 5951 17521 riscv.c:1575 riscv_flush_registers(): [esp32c6] t1 is dirty; write back 0xffffffe0 Debug: 5952 17521 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0xffffffe0 to register t1 Debug: 5953 17521 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0xffffffe0 to t1 Debug: 5954 17524 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006 Debug: 5955 17535 riscv-013.c:1532 register_write_direct(): [esp32c6] t1 <- 0xffffffe0 Debug: 5956 17535 riscv.c:1575 riscv_flush_registers(): [esp32c6] t0 is dirty; write back 0x40027bd4 Debug: 5957 17535 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40027bd4 to register t0 Debug: 5958 17535 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40027bd4 to t0 Debug: 5959 17539 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005 Debug: 5960 17544 riscv-013.c:1532 register_write_direct(): [esp32c6] t0 <- 0x40027bd4 Debug: 5961 17544 riscv.c:1575 riscv_flush_registers(): [esp32c6] tp is dirty; write back 0x0 Debug: 5962 17544 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tp Debug: 5963 17544 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tp [OpenOCD] Debug: 5964 17561 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004 Debug: 5965 17580 riscv-013.c:1532 register_write_direct(): [esp32c6] tp <- 0x0 Debug: 5966 17580 riscv.c:1575 riscv_flush_registers(): [esp32c6] gp is dirty; write back 0x0 Debug: 5967 17580 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register gp Debug: 5968 17580 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to gp Debug: 5969 17584 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003 Debug: 5970 17593 riscv-013.c:1532 register_write_direct(): [esp32c6] gp <- 0x0 Debug: 5971 17593 riscv.c:1575 riscv_flush_registers(): [esp32c6] sp is dirty; write back 0x40804780 Debug: 5972 17593 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40804780 to register sp Debug: 5973 17593 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40804780 to sp Debug: 5974 17597 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 5975 17603 riscv-013.c:1532 register_write_direct(): [esp32c6] sp <- 0x40804780 Debug: 5976 17603 riscv.c:1575 riscv_flush_registers(): [esp32c6] ra is dirty; write back 0x40801456 Debug: 5977 17603 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40801456 to register ra Debug: 5978 17603 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40801456 to ra Debug: 5979 17606 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001 Debug: 5980 17616 riscv-013.c:1532 register_write_direct(): [esp32c6] ra <- 0x40801456 Debug: 5981 17617 esp_algorithm.c:130 algorithm_run_image(): Got algorithm RC 0x0 Debug: 5982 17632 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804794 Debug: 5983 17639 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 5984 17639 target.c:2138 target_free_working_area_restore(): freed 28 bytes of working area at address 0x40804794 Debug: 5985 17639 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 5986 17639 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 5987 17639 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 5988 17639 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 5989 17639 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 5990 17639 target.c:1938 print_wa_layout(): 0x40804794-0x40823fff (129132 bytes) Debug: 5991 17639 esp.c:259 esp_common_assist_debug_monitor_restore(): [esp32c6] value 0x00000000 addr 0x600c2000 Debug: 5992 17639 target.c:2686 target_write_u32(): address: 0x600c2000, value: 0x00000000 Debug: 5993 17645 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600c2000 Debug: 5994 17651 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 5995 17651 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 5996 17660 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800000 [OpenOCD] Debug: 5997 17671 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800200 Debug: 5998 17681 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800400 Debug: 5999 17696 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800600 Debug: 6000 17706 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800800 Debug: 6001 17717 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800a00 Debug: 6002 17726 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800c00 Debug: 6003 17735 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800e00 [OpenOCD] Debug: 6004 17744 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801000 Debug: 6005 17755 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801200 Debug: 6006 17765 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801400 Debug: 6007 17827 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. [OpenOCD] Debug: 6008 17840 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801454 Debug: 6009 17847 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6010 17869 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804000 Debug: 6011 17879 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804200 Debug: 6012 17890 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6013 17897 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804280 Debug: 6014 17906 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804480 [OpenOCD] Debug: 6015 17915 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804680 Debug: 6016 17925 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6017 17925 target.c:1938 print_wa_layout(): 0x40800000-0x40823fff (147456 bytes) Info : 6018 17925 esp_flash.c:412 esp_algo_flash_get_mappings(): Flash mapping 0: 0x20020 -> 0x42020020, 55 KB Info : 6019 17925 esp_flash.c:412 esp_algo_flash_get_mappings(): Flash mapping 1: 0x30020 -> 0x42000020, 109 KB Info : 6020 17925 esp_flash.c:1013 esp_algo_flash_probe(): Using flash bank 'esp32c6.irom' size 112 KB Debug: 6021 17925 esp_flash.c:1030 esp_algo_flash_probe(): allocated 28 sectors Debug: 6022 17925 esp_flash.c:961 esp_algo_flash_probe(): Flash size = 0 KB @ 0x00000000 'esp32c6' - 'halted' Debug: 6023 17925 esp_flash.c:245 esp_algo_flasher_algorithm_init(): base=00000000 set=0 Debug: 6024 17925 esp_algorithm.c:290 algorithm_load_func_image(): stub: base 0x0, start 0x4080110c, 2 sections Debug: 6025 17925 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 5202, flags 1 Debug: 6026 17925 target.c:2017 target_alloc_working_area_try(): MMU disabled, using physical address for working memory 0x40800000 Debug: 6027 17925 target.c:2070 target_alloc_working_area_try(): allocated new working area of 5204 bytes at address 0x40800000 [OpenOCD] Debug: 6028 19584 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6029 19584 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 6030 19584 target.c:1938 print_wa_layout(): 0x40801454-0x40823fff (142252 bytes) Debug: 6031 19584 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800000 [OpenOCD] Debug: 6032 19589 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800000 Debug: 6033 19596 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800200 Debug: 6034 19605 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6035 19605 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800400 Debug: 6036 19610 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800400 Debug: 6037 19618 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800600 Debug: 6038 19626 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6039 19626 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800800 Debug: 6040 19632 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800800 Debug: 6041 19641 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800a00 [OpenOCD] Debug: 6042 19648 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6043 19648 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40800c00 Debug: 6044 19654 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800c00 Debug: 6045 19662 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800e00 Debug: 6046 19672 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6047 19672 target.c:2379 target_write_buffer(): writing buffer of 1024 byte at 0x40801000 Debug: 6048 19677 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801000 Debug: 6049 19686 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801200 [OpenOCD] Debug: 6050 19694 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6051 19694 target.c:2379 target_write_buffer(): writing buffer of 82 byte at 0x40801400 Debug: 6052 19700 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801400 Debug: 6053 19705 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6054 19705 esp_riscv.c:826 esp_riscv_write_memory(): Use 32-bit access: size: 2 count:1 start address: 0x40801450 Debug: 6055 19716 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6056 19723 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801450 Debug: 6057 19728 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6058 19728 target.c:2070 target_alloc_working_area_try(): allocated new working area of 4 bytes at address 0x40801454 Debug: 6059 19739 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6060 19739 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 6061 19739 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 6062 19739 target.c:1938 print_wa_layout(): 0x40801458-0x40823fff (142248 bytes) Debug: 6063 19739 esp_algorithm.c:377 algorithm_load_func_image(): Write tramp to addr 0x40801454, sz 4 Debug: 6064 19739 target.c:2379 target_write_buffer(): writing buffer of 4 byte at 0x40801454 [OpenOCD] Debug: 6065 19746 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801454 Debug: 6066 19756 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6067 19756 esp_algorithm.c:388 algorithm_load_func_image(): Tramp mapped to addr 0x40801454 Debug: 6068 19756 target.c:2070 target_alloc_working_area_try(): allocated new working area of 11176 bytes at address 0x40801458 Debug: 6069 19756 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 6070 19756 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 6071 19756 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 6072 19756 target.c:1938 print_wa_layout(): 0x40804000-0x40823fff (131072 bytes) Debug: 6073 19756 esp_algorithm.c:413 algorithm_load_func_image(): addr 0x00000000, sz 321, flags 0 Debug: 6074 19756 esp_algorithm.c:417 algorithm_load_func_image(): DATA sec size 321 -> 324 Debug: 6075 19756 esp_algorithm.c:419 algorithm_load_func_image(): BSS sec size 316 -> 316 Debug: 6076 19756 target.c:2070 target_alloc_working_area_try(): allocated new working area of 640 bytes at address 0x40804000 [OpenOCD] Debug: 6077 20089 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6078 20089 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 6079 20089 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 6080 20089 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 6081 20089 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 6082 20089 target.c:1938 print_wa_layout(): 0x40804280-0x40823fff (130432 bytes) Debug: 6083 20089 target.c:2379 target_write_buffer(): writing buffer of 321 byte at 0x40804000 [OpenOCD] Debug: 6084 20096 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804000 Debug: 6085 20102 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6086 20102 esp_riscv.c:826 esp_riscv_write_memory(): Use 32-bit access: size: 1 count:1 start address: 0x40804140 Debug: 6087 20112 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6088 20117 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804140 Debug: 6089 20121 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6090 20121 target.c:2070 target_alloc_working_area_try(): allocated new working area of 1300 bytes at address 0x40804280 [OpenOCD] Debug: 6091 20531 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6092 20531 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 6093 20531 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 6094 20531 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 6095 20531 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 6096 20531 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 6097 20531 target.c:1938 print_wa_layout(): 0x40804794-0x40823fff (129132 bytes) Debug: 6098 20531 esp_algorithm.c:460 algorithm_load_func_image(): Stub loaded in 2606.17 ms Debug: 6099 20531 esp_riscv_algorithm.c:43 esp_riscv_algo_regs_init_start(): Check stack addr 0x40804794 Debug: 6100 20531 esp_riscv_algorithm.c:46 esp_riscv_algo_regs_init_start(): Adjust stack addr to 0x40804790 [OpenOCD] Debug: 6101 20531 esp_riscv_algorithm.c:84 esp_riscv_algo_init(): Set arg[0] = 5 (a0) Debug: 6102 20531 esp_riscv_algorithm.c:95 esp_riscv_algo_init(): Set arg[1] = -1 (a1) Debug: 6103 20531 esp_riscv_algorithm.c:95 esp_riscv_algo_init(): Set arg[2] = 0 (a2) Debug: 6104 20531 esp.c:240 esp_common_assist_debug_monitor_disable(): [esp32c6] addr 0x600c2000 Debug: 6105 20541 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6106 20541 target.c:2598 target_read_u32(): address: 0x600c2000, value: 0x00000000 Debug: 6107 20541 esp.c:248 esp_common_assist_debug_monitor_disable(): Saved register value 0x00000000 Debug: 6108 20541 target.c:2686 target_write_u32(): address: 0x600c2000, value: 0x00000000 Debug: 6109 20546 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600c2000 Debug: 6110 20550 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 6111 20550 target.c:2070 target_alloc_working_area_try(): allocated new working area of 28 bytes at address 0x40804794 Debug: 6112 20577 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6113 20577 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 6114 20577 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 6115 20577 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 6116 20577 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 6117 20577 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 6118 20577 target.c:1938 print_wa_layout(): b* 0x40804794-0x408047af (28 bytes) Debug: 6119 20577 target.c:1938 print_wa_layout(): 0x408047b0-0x40823fff (129104 bytes) Debug: 6120 20577 esp_algorithm.c:90 algorithm_run_image(): Algorithm start @ 0x40801454, stack 1300 bytes @ 0x40804794 Debug: 6121 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save ra Debug: 6122 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read ra: 0x40801456 (cached) Debug: 6123 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x40801456 from ra (valid=1). Debug: 6124 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save sp Debug: 6125 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read sp: 0x40804780 (cached) Debug: 6126 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x40804780 from sp (valid=1). Debug: 6127 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save gp Debug: 6128 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read gp: 0x0 (cached) Debug: 6129 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from gp (valid=1). Debug: 6130 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save tp Debug: 6131 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read tp: 0x0 (cached) Debug: 6132 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tp (valid=1). Debug: 6133 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save t0 Debug: 6134 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read t0: 0x40027bd4 (cached) Debug: 6135 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x40027bd4 from t0 (valid=1). Debug: 6136 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save t1 Debug: 6137 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read t1: 0xffffffe0 (cached) Debug: 6138 20577 riscv.c:5259 register_get(): [esp32c6] Read 0xffffffe0 from t1 (valid=1). Debug: 6139 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save t2 Debug: 6140 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read t2: 0x0 (cached) Debug: 6141 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t2 (valid=1). Debug: 6142 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save fp Debug: 6143 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read fp: 0x0 (cached) Debug: 6144 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from fp (valid=1). Debug: 6145 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s1 Debug: 6146 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s1: 0x0 (cached) Debug: 6147 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s1 (valid=1). Debug: 6148 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save a0 Debug: 6149 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read a0: 0x20000000 (cached) Debug: 6150 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x20000000 from a0 (valid=1). Debug: 6151 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save a1 Debug: 6152 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read a1: 0x60002000 (cached) Debug: 6153 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x60002000 from a1 (valid=1). Debug: 6154 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save a2 Debug: 6155 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read a2: 0x10 (cached) Debug: 6156 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000010 from a2 (valid=1). Debug: 6157 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save a3 Debug: 6158 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read a3: 0x10000 (cached) Debug: 6159 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00010000 from a3 (valid=1). Debug: 6160 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save a4 Debug: 6161 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read a4: 0x408021e0 (cached) Debug: 6162 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x408021e0 from a4 (valid=1). Debug: 6163 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save a5 Debug: 6164 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read a5: 0x4 (cached) Debug: 6165 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000004 from a5 (valid=1). Debug: 6166 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save a6 Debug: 6167 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read a6: 0x8 (cached) Debug: 6168 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000008 from a6 (valid=1). Debug: 6169 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save a7 Debug: 6170 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read a7: 0x80000000 (cached) Debug: 6171 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x80000000 from a7 (valid=1). Debug: 6172 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s2 Debug: 6173 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s2: 0x0 (cached) Debug: 6174 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s2 (valid=1). Debug: 6175 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s3 Debug: 6176 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s3: 0x0 (cached) Debug: 6177 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s3 (valid=1). Debug: 6178 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s4 Debug: 6179 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s4: 0x0 (cached) Debug: 6180 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s4 (valid=1). Debug: 6181 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s5 Debug: 6182 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s5: 0x0 (cached) Debug: 6183 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s5 (valid=1). Debug: 6184 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s6 Debug: 6185 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s6: 0x0 (cached) Debug: 6186 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s6 (valid=1). Debug: 6187 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s7 Debug: 6188 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s7: 0x0 (cached) Debug: 6189 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s7 (valid=1). Debug: 6190 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s8 Debug: 6191 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s8: 0x0 (cached) Debug: 6192 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s8 (valid=1). Debug: 6193 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s9 Debug: 6194 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s9: 0x0 (cached) Debug: 6195 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s9 (valid=1). Debug: 6196 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s10 Debug: 6197 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s10: 0x0 (cached) Debug: 6198 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s10 (valid=1). Debug: 6199 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save s11 Debug: 6200 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read s11: 0x0 (cached) Debug: 6201 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from s11 (valid=1). Debug: 6202 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save t3 Debug: 6203 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read t3: 0x0 (cached) Debug: 6204 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t3 (valid=1). Debug: 6205 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save t4 Debug: 6206 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read t4: 0x0 (cached) Debug: 6207 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t4 (valid=1). Debug: 6208 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save t5 Debug: 6209 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read t5: 0x0 (cached) Debug: 6210 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t5 (valid=1). Debug: 6211 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save t6 Debug: 6212 20577 riscv.c:4819 riscv_get_register(): [esp32c6] Read t6: 0x0 (cached) Debug: 6213 20577 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from t6 (valid=1). Debug: 6214 20577 esp_riscv.c:593 esp_riscv_start_algorithm(): save pc Debug: 6215 20577 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 6216 20577 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 6217 20577 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 6218 20577 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 [OpenOCD] Debug: 6219 20583 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40000000 Debug: 6220 20583 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40000000 Debug: 6221 20583 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40000000 Debug: 6222 20583 riscv.c:5259 register_get(): [esp32c6] Read 0x40000000 from pc (valid=0). Debug: 6223 20583 esp_riscv.c:593 esp_riscv_start_algorithm(): save mstatus Debug: 6224 20583 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mstatus from target Debug: 6225 20583 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mstatus Debug: 6226 20583 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mstatus Debug: 6227 20583 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 6228 20590 riscv-013.c:1561 register_read_direct(): [esp32c6] mstatus = 0x201800 Debug: 6229 20590 riscv.c:4831 riscv_get_register(): [esp32c6] Read mstatus: 0x201800 Debug: 6230 20590 riscv.c:5259 register_get(): [esp32c6] Read 0x00201800 from mstatus (valid=1). Debug: 6231 20590 esp_riscv.c:593 esp_riscv_start_algorithm(): save misa Debug: 6232 20590 riscv.c:4823 riscv_get_register(): [esp32c6] Reading misa from target Debug: 6233 20590 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register misa Debug: 6234 20590 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading misa Debug: 6235 20590 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 6236 20597 riscv-013.c:1561 register_read_direct(): [esp32c6] misa = 0x40903105 Debug: 6237 20597 riscv.c:4831 riscv_get_register(): [esp32c6] Read misa: 0x40903105 Debug: 6238 20597 riscv.c:5259 register_get(): [esp32c6] Read 0x40903105 from misa (valid=1). Debug: 6239 20597 esp_riscv.c:593 esp_riscv_start_algorithm(): save mtvec Debug: 6240 20597 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mtvec from target Debug: 6241 20597 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr773 Debug: 6242 20597 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr773 Debug: 6243 20597 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305 Debug: 6244 20608 riscv-013.c:1561 register_read_direct(): [esp32c6] csr773 = 0x1 Debug: 6245 20608 riscv.c:4831 riscv_get_register(): [esp32c6] Read mtvec: 0x1 Debug: 6246 20608 riscv.c:5259 register_get(): [esp32c6] Read 0x00000001 from mtvec (valid=0). Debug: 6247 20608 esp_riscv.c:593 esp_riscv_start_algorithm(): save mscratch Debug: 6248 20608 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mscratch from target Debug: 6249 20608 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr832 Debug: 6250 20608 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr832 Debug: 6251 20608 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340 Debug: 6252 20620 riscv-013.c:1561 register_read_direct(): [esp32c6] csr832 = 0x0 Debug: 6253 20620 riscv.c:4831 riscv_get_register(): [esp32c6] Read mscratch: 0x0 Debug: 6254 20620 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mscratch (valid=0). Debug: 6255 20620 esp_riscv.c:593 esp_riscv_start_algorithm(): save mepc Debug: 6256 20620 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mepc from target Debug: 6257 20620 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mepc Debug: 6258 20620 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mepc Debug: 6259 20620 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 6260 20631 riscv-013.c:1561 register_read_direct(): [esp32c6] mepc = 0x0 Debug: 6261 20631 riscv.c:4831 riscv_get_register(): [esp32c6] Read mepc: 0x0 Debug: 6262 20631 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mepc (valid=1). Debug: 6263 20631 esp_riscv.c:593 esp_riscv_start_algorithm(): save mcause Debug: 6264 20631 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mcause from target Debug: 6265 20631 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register mcause Debug: 6266 20631 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading mcause Debug: 6267 20631 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 [OpenOCD] Debug: 6268 20641 riscv-013.c:1561 register_read_direct(): [esp32c6] mcause = 0x0 Debug: 6269 20641 riscv.c:4831 riscv_get_register(): [esp32c6] Read mcause: 0x0 Debug: 6270 20641 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mcause (valid=1). Debug: 6271 20641 esp_riscv.c:593 esp_riscv_start_algorithm(): save mtval Debug: 6272 20641 riscv.c:4823 riscv_get_register(): [esp32c6] Reading mtval from target Debug: 6273 20641 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr835 Debug: 6274 20641 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr835 Debug: 6275 20641 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343 Debug: 6276 20659 riscv-013.c:1561 register_read_direct(): [esp32c6] csr835 = 0x0 Debug: 6277 20659 riscv.c:4831 riscv_get_register(): [esp32c6] Read mtval: 0x0 Debug: 6278 20659 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from mtval (valid=0). Debug: 6279 20659 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg0 Debug: 6280 20659 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg0 from target Debug: 6281 20659 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr928 Debug: 6282 20659 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr928 Debug: 6283 20659 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0 Debug: 6284 20678 riscv-013.c:1561 register_read_direct(): [esp32c6] csr928 = 0x0 Debug: 6285 20678 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg0: 0x0 Debug: 6286 20678 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg0 (valid=0). Debug: 6287 20678 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg1 Debug: 6288 20678 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg1 from target Debug: 6289 20678 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr929 Debug: 6290 20678 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr929 Debug: 6291 20678 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1 Debug: 6292 20689 riscv-013.c:1561 register_read_direct(): [esp32c6] csr929 = 0x0 Debug: 6293 20689 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg1: 0x0 Debug: 6294 20689 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg1 (valid=0). Debug: 6295 20689 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg2 Debug: 6296 20689 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg2 from target Debug: 6297 20689 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr930 Debug: 6298 20689 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr930 Debug: 6299 20689 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2 Debug: 6300 20695 riscv-013.c:1561 register_read_direct(): [esp32c6] csr930 = 0x0 Debug: 6301 20695 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg2: 0x0 Debug: 6302 20695 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg2 (valid=0). Debug: 6303 20695 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpcfg3 Debug: 6304 20695 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpcfg3 from target Debug: 6305 20695 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr931 Debug: 6306 20695 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr931 Debug: 6307 20695 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3 [OpenOCD] Debug: 6308 20704 riscv-013.c:1561 register_read_direct(): [esp32c6] csr931 = 0x0 Debug: 6309 20704 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpcfg3: 0x0 Debug: 6310 20704 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpcfg3 (valid=0). Debug: 6311 20704 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr0 Debug: 6312 20704 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr0 from target Debug: 6313 20704 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr944 Debug: 6314 20704 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr944 Debug: 6315 20704 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0 Debug: 6316 20710 riscv-013.c:1561 register_read_direct(): [esp32c6] csr944 = 0x0 Debug: 6317 20710 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr0: 0x0 Debug: 6318 20710 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr0 (valid=0). Debug: 6319 20710 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr1 Debug: 6320 20710 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr1 from target Debug: 6321 20710 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr945 Debug: 6322 20710 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr945 Debug: 6323 20710 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1 Debug: 6324 20720 riscv-013.c:1561 register_read_direct(): [esp32c6] csr945 = 0x0 Debug: 6325 20720 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr1: 0x0 Debug: 6326 20720 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr1 (valid=0). Debug: 6327 20720 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr2 Debug: 6328 20720 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr2 from target Debug: 6329 20720 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr946 Debug: 6330 20720 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr946 Debug: 6331 20720 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2 Debug: 6332 20727 riscv-013.c:1561 register_read_direct(): [esp32c6] csr946 = 0x0 Debug: 6333 20727 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr2: 0x0 Debug: 6334 20727 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr2 (valid=0). Debug: 6335 20727 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr3 Debug: 6336 20727 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr3 from target Debug: 6337 20727 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr947 Debug: 6338 20727 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr947 Debug: 6339 20727 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3 Debug: 6340 20736 riscv-013.c:1561 register_read_direct(): [esp32c6] csr947 = 0x0 Debug: 6341 20736 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr3: 0x0 Debug: 6342 20736 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr3 (valid=0). Debug: 6343 20736 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr4 Debug: 6344 20736 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr4 from target Debug: 6345 20736 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr948 Debug: 6346 20736 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr948 Debug: 6347 20736 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4 Debug: 6348 20743 riscv-013.c:1561 register_read_direct(): [esp32c6] csr948 = 0x0 Debug: 6349 20743 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr4: 0x0 Debug: 6350 20743 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr4 (valid=0). Debug: 6351 20743 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr5 Debug: 6352 20743 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr5 from target Debug: 6353 20743 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr949 Debug: 6354 20743 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr949 Debug: 6355 20743 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5 Debug: 6356 20748 riscv-013.c:1561 register_read_direct(): [esp32c6] csr949 = 0x0 Debug: 6357 20748 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr5: 0x0 Debug: 6358 20748 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr5 (valid=0). Debug: 6359 20748 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr6 Debug: 6360 20748 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr6 from target Debug: 6361 20748 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr950 Debug: 6362 20748 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr950 Debug: 6363 20748 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6 Debug: 6364 20761 riscv-013.c:1561 register_read_direct(): [esp32c6] csr950 = 0x0 Debug: 6365 20761 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr6: 0x0 Debug: 6366 20761 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr6 (valid=0). Debug: 6367 20761 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr7 Debug: 6368 20761 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr7 from target Debug: 6369 20761 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr951 Debug: 6370 20761 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr951 Debug: 6371 20761 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7 [OpenOCD] Debug: 6372 20813 riscv-013.c:1561 register_read_direct(): [esp32c6] csr951 = 0x0 Debug: 6373 20813 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr7: 0x0 Debug: 6374 20813 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr7 (valid=0). Debug: 6375 20813 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr8 Debug: 6376 20813 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr8 from target Debug: 6377 20813 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr952 Debug: 6378 20813 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr952 Debug: 6379 20813 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8 Debug: 6380 20826 riscv-013.c:1561 register_read_direct(): [esp32c6] csr952 = 0x0 Debug: 6381 20826 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr8: 0x0 Debug: 6382 20826 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr8 (valid=0). Debug: 6383 20826 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr9 Debug: 6384 20826 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr9 from target Debug: 6385 20826 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr953 Debug: 6386 20826 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr953 Debug: 6387 20826 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9 Debug: 6388 20837 riscv-013.c:1561 register_read_direct(): [esp32c6] csr953 = 0x0 Debug: 6389 20837 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr9: 0x0 Debug: 6390 20837 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr9 (valid=0). Debug: 6391 20837 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr10 Debug: 6392 20837 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr10 from target Debug: 6393 20837 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr954 Debug: 6394 20837 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr954 Debug: 6395 20837 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba Debug: 6396 20847 riscv-013.c:1561 register_read_direct(): [esp32c6] csr954 = 0x0 Debug: 6397 20847 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr10: 0x0 Debug: 6398 20847 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr10 (valid=0). Debug: 6399 20847 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr11 Debug: 6400 20847 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr11 from target Debug: 6401 20847 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr955 Debug: 6402 20847 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr955 Debug: 6403 20847 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb Debug: 6404 20862 riscv-013.c:1561 register_read_direct(): [esp32c6] csr955 = 0x0 Debug: 6405 20863 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr11: 0x0 Debug: 6406 20863 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr11 (valid=0). Debug: 6407 20863 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr12 Debug: 6408 20863 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr12 from target Debug: 6409 20863 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr956 Debug: 6410 20863 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr956 Debug: 6411 20863 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc [OpenOCD] Debug: 6412 20871 riscv-013.c:1561 register_read_direct(): [esp32c6] csr956 = 0x0 Debug: 6413 20871 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr12: 0x0 Debug: 6414 20871 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr12 (valid=0). Debug: 6415 20871 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr13 Debug: 6416 20871 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr13 from target Debug: 6417 20871 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr957 Debug: 6418 20871 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr957 Debug: 6419 20871 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd Debug: 6420 20883 riscv-013.c:1561 register_read_direct(): [esp32c6] csr957 = 0x0 Debug: 6421 20883 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr13: 0x0 Debug: 6422 20883 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr13 (valid=0). Debug: 6423 20883 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr14 Debug: 6424 20883 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr14 from target Debug: 6425 20883 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr958 Debug: 6426 20883 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr958 Debug: 6427 20883 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be Debug: 6428 20896 riscv-013.c:1561 register_read_direct(): [esp32c6] csr958 = 0x0 Debug: 6429 20896 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr14: 0x0 Debug: 6430 20896 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr14 (valid=0). Debug: 6431 20896 esp_riscv.c:593 esp_riscv_start_algorithm(): save pmpaddr15 Debug: 6432 20896 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pmpaddr15 from target Debug: 6433 20896 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr959 Debug: 6434 20896 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr959 Debug: 6435 20896 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf Debug: 6436 20910 riscv-013.c:1561 register_read_direct(): [esp32c6] csr959 = 0x0 Debug: 6437 20910 riscv.c:4831 riscv_get_register(): [esp32c6] Read pmpaddr15: 0x0 Debug: 6438 20910 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from pmpaddr15 (valid=0). Debug: 6439 20910 esp_riscv.c:593 esp_riscv_start_algorithm(): save tselect Debug: 6440 20910 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tselect from target Debug: 6441 20910 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tselect Debug: 6442 20910 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tselect Debug: 6443 20910 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 6444 20922 riscv-013.c:1561 register_read_direct(): [esp32c6] tselect = 0x0 Debug: 6445 20922 riscv.c:4831 riscv_get_register(): [esp32c6] Read tselect: 0x0 Debug: 6446 20922 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tselect (valid=0). Debug: 6447 20922 esp_riscv.c:593 esp_riscv_start_algorithm(): save tdata1 Debug: 6448 20922 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata1 from target Debug: 6449 20922 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata1 Debug: 6450 20922 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata1 Debug: 6451 20922 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 6452 20928 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata1 = 0x23e00000 Debug: 6453 20928 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata1: 0x23e00000 Debug: 6454 20928 riscv.c:5259 register_get(): [esp32c6] Read 0x23e00000 from tdata1 (valid=0). Debug: 6455 20928 esp_riscv.c:593 esp_riscv_start_algorithm(): save tdata2 Debug: 6456 20928 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tdata2 from target Debug: 6457 20928 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register tdata2 Debug: 6458 20928 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading tdata2 Debug: 6459 20928 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2 [OpenOCD] Debug: 6460 20935 riscv-013.c:1561 register_read_direct(): [esp32c6] tdata2 = 0x0 Debug: 6461 20935 riscv.c:4831 riscv_get_register(): [esp32c6] Read tdata2: 0x0 Debug: 6462 20935 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tdata2 (valid=0). Debug: 6463 20935 esp_riscv.c:593 esp_riscv_start_algorithm(): save tcontrol Debug: 6464 20935 riscv.c:4823 riscv_get_register(): [esp32c6] Reading tcontrol from target Debug: 6465 20935 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr1957 Debug: 6466 20935 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr1957 Debug: 6467 20935 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5 Debug: 6468 20943 riscv-013.c:1561 register_read_direct(): [esp32c6] csr1957 = 0x0 Debug: 6469 20943 riscv.c:4831 riscv_get_register(): [esp32c6] Read tcontrol: 0x0 Debug: 6470 20943 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from tcontrol (valid=0). Debug: 6471 20943 esp_riscv.c:593 esp_riscv_start_algorithm(): save dcsr Debug: 6472 20943 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dcsr from target Debug: 6473 20943 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dcsr Debug: 6474 20943 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 6475 20943 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 6476 20953 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 6477 20953 riscv.c:4831 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 Debug: 6478 20953 riscv.c:5259 register_get(): [esp32c6] Read 0x400090c3 from dcsr (valid=1). Debug: 6479 20953 esp_riscv.c:593 esp_riscv_start_algorithm(): save dpc Debug: 6480 20953 riscv.c:4819 riscv_get_register(): [esp32c6] Read dpc: 0x40000000 (cached) Debug: 6481 20953 riscv.c:5259 register_get(): [esp32c6] Read 0x40000000 from dpc (valid=1). Debug: 6482 20953 esp_riscv.c:593 esp_riscv_start_algorithm(): save dscratch0 Debug: 6483 20953 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dscratch0 from target Debug: 6484 20953 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register dscratch0 Debug: 6485 20953 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dscratch0 Debug: 6486 20953 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2 Debug: 6487 20965 riscv-013.c:1561 register_read_direct(): [esp32c6] dscratch0 = 0x0 Debug: 6488 20965 riscv.c:4831 riscv_get_register(): [esp32c6] Read dscratch0: 0x0 Debug: 6489 20965 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from dscratch0 (valid=1). Debug: 6490 20965 esp_riscv.c:593 esp_riscv_start_algorithm(): save dscratch1 Debug: 6491 20965 riscv.c:4823 riscv_get_register(): [esp32c6] Reading dscratch1 from target Debug: 6492 20965 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr1971 Debug: 6493 20965 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr1971 Debug: 6494 20965 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3 Debug: 6495 20976 riscv-013.c:1561 register_read_direct(): [esp32c6] csr1971 = 0x20000000 Debug: 6496 20976 riscv.c:4831 riscv_get_register(): [esp32c6] Read dscratch1: 0x20000000 Debug: 6497 20976 riscv.c:5259 register_get(): [esp32c6] Read 0x20000000 from dscratch1 (valid=0). Debug: 6498 20976 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpcer Debug: 6499 20976 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpcer from target Debug: 6500 20976 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2016 Debug: 6501 20976 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2016 Debug: 6502 20976 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e0 Debug: 6503 20985 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2016 = 0x0 Debug: 6504 20985 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpcer: 0x0 Debug: 6505 20985 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_mpcer (valid=0). Debug: 6506 20985 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpcmr Debug: 6507 20985 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpcmr from target Debug: 6508 20985 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2017 Debug: 6509 20985 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2017 Debug: 6510 20985 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e1 [OpenOCD] Debug: 6511 21006 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2017 = 0x3 Debug: 6512 21006 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpcmr: 0x3 Debug: 6513 21006 riscv.c:5259 register_get(): [esp32c6] Read 0x00000003 from csr_mpcmr (valid=0). Debug: 6514 21006 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_mpccr Debug: 6515 21006 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_mpccr from target Debug: 6516 21006 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2018 Debug: 6517 21006 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2018 Debug: 6518 21006 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207e2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7e2 Debug: 6519 21034 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2018 = 0x0 Debug: 6520 21034 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_mpccr: 0x0 Debug: 6521 21034 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_mpccr (valid=0). Debug: 6522 21034 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_oen Debug: 6523 21034 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_oen from target Debug: 6524 21034 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2051 Debug: 6525 21034 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2051 Debug: 6526 21034 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220803; access register, size=32, postexec=0, transfer=1, write=0, regno=0x803 Debug: 6527 21052 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2051 = 0x0 Debug: 6528 21052 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_oen: 0x0 Debug: 6529 21052 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_oen (valid=0). Debug: 6530 21052 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_in Debug: 6531 21052 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_in from target Debug: 6532 21052 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2052 Debug: 6533 21052 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2052 Debug: 6534 21052 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220804; access register, size=32, postexec=0, transfer=1, write=0, regno=0x804 Debug: 6535 21070 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2052 = 0x0 Debug: 6536 21070 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_in: 0x0 Debug: 6537 21070 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_in (valid=0). Debug: 6538 21070 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_cpu_gpio_out Debug: 6539 21070 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_cpu_gpio_out from target Debug: 6540 21070 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr2053 Debug: 6541 21070 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr2053 Debug: 6542 21070 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220805; access register, size=32, postexec=0, transfer=1, write=0, regno=0x805 Debug: 6543 21081 riscv-013.c:1561 register_read_direct(): [esp32c6] csr2053 = 0x0 Debug: 6544 21081 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_cpu_gpio_out: 0x0 Debug: 6545 21081 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_cpu_gpio_out (valid=0). Debug: 6546 21081 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg0 Debug: 6547 21081 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg0 from target Debug: 6548 21081 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3008 Debug: 6549 21081 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3008 Debug: 6550 21081 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc0 Debug: 6551 21089 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3008 = 0x0 Debug: 6552 21089 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg0: 0x0 Debug: 6553 21089 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg0 (valid=0). Debug: 6554 21089 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg1 Debug: 6555 21089 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg1 from target Debug: 6556 21089 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3009 Debug: 6557 21089 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3009 Debug: 6558 21089 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc1; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc1 [OpenOCD] Debug: 6559 21152 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3009 = 0x0 Debug: 6560 21152 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg1: 0x0 Debug: 6561 21152 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg1 (valid=0). Debug: 6562 21152 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg2 Debug: 6563 21152 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg2 from target Debug: 6564 21152 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3010 Debug: 6565 21152 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3010 Debug: 6566 21152 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc2; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc2 Debug: 6567 21161 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3010 = 0x0 Debug: 6568 21161 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg2: 0x0 Debug: 6569 21161 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg2 (valid=0). Debug: 6570 21161 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg3 Debug: 6571 21161 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg3 from target Debug: 6572 21161 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3011 Debug: 6573 21161 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3011 Debug: 6574 21161 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc3; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc3 Debug: 6575 21169 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3011 = 0x0 Debug: 6576 21169 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg3: 0x0 Debug: 6577 21169 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg3 (valid=0). Debug: 6578 21169 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg4 Debug: 6579 21169 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg4 from target Debug: 6580 21169 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3012 Debug: 6581 21169 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3012 Debug: 6582 21169 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc4; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc4 [OpenOCD] Debug: 6583 21181 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3012 = 0x0 Debug: 6584 21181 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg4: 0x0 Debug: 6585 21181 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg4 (valid=0). Debug: 6586 21181 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg5 Debug: 6587 21181 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg5 from target Debug: 6588 21181 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3013 Debug: 6589 21181 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3013 Debug: 6590 21181 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc5; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc5 Debug: 6591 21190 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3013 = 0x0 Debug: 6592 21190 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg5: 0x0 Debug: 6593 21190 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg5 (valid=0). Debug: 6594 21190 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg6 Debug: 6595 21190 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg6 from target Debug: 6596 21190 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3014 Debug: 6597 21190 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3014 Debug: 6598 21190 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc6; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc6 Debug: 6599 21201 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3014 = 0x0 Debug: 6600 21201 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg6: 0x0 Debug: 6601 21201 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg6 (valid=0). Debug: 6602 21201 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg7 Debug: 6603 21201 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg7 from target Debug: 6604 21201 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3015 Debug: 6605 21201 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3015 Debug: 6606 21201 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc7; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc7 Debug: 6607 21210 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3015 = 0x0 Debug: 6608 21210 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg7: 0x0 Debug: 6609 21210 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg7 (valid=0). Debug: 6610 21210 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg8 Debug: 6611 21210 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg8 from target Debug: 6612 21210 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3016 Debug: 6613 21210 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3016 Debug: 6614 21210 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc8; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc8 Debug: 6615 21219 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3016 = 0x0 Debug: 6616 21219 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg8: 0x0 Debug: 6617 21219 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg8 (valid=0). Debug: 6618 21219 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg9 Debug: 6619 21219 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg9 from target Debug: 6620 21219 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3017 Debug: 6621 21219 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3017 Debug: 6622 21219 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bc9; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbc9 Debug: 6623 21227 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3017 = 0x0 Debug: 6624 21227 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg9: 0x0 Debug: 6625 21227 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg9 (valid=0). Debug: 6626 21227 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg10 Debug: 6627 21227 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg10 from target Debug: 6628 21227 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3018 Debug: 6629 21227 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3018 Debug: 6630 21227 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bca; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbca Debug: 6631 21233 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3018 = 0x0 Debug: 6632 21233 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg10: 0x0 Debug: 6633 21233 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg10 (valid=0). Debug: 6634 21233 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg11 Debug: 6635 21233 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg11 from target Debug: 6636 21233 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3019 Debug: 6637 21233 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3019 Debug: 6638 21233 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcb; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcb Debug: 6639 21239 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3019 = 0x0 Debug: 6640 21239 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg11: 0x0 Debug: 6641 21239 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg11 (valid=0). Debug: 6642 21239 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg12 Debug: 6643 21239 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg12 from target Debug: 6644 21239 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3020 Debug: 6645 21240 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3020 Debug: 6646 21240 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcc; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcc [OpenOCD] Debug: 6647 21256 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3020 = 0x0 Debug: 6648 21256 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg12: 0x0 Debug: 6649 21256 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg12 (valid=0). Debug: 6650 21256 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg13 Debug: 6651 21256 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg13 from target Debug: 6652 21256 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3021 Debug: 6653 21256 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3021 Debug: 6654 21256 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcd; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcd Debug: 6655 21269 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3021 = 0x0 Debug: 6656 21269 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg13: 0x0 Debug: 6657 21269 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg13 (valid=0). Debug: 6658 21269 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg14 Debug: 6659 21269 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg14 from target Debug: 6660 21269 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3022 Debug: 6661 21269 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3022 Debug: 6662 21269 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bce; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbce Debug: 6663 21281 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3022 = 0x0 Debug: 6664 21281 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg14: 0x0 Debug: 6665 21281 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg14 (valid=0). Debug: 6666 21281 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_cfg15 Debug: 6667 21281 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_cfg15 from target Debug: 6668 21281 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3023 Debug: 6669 21281 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3023 Debug: 6670 21281 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bcf; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbcf Debug: 6671 21294 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3023 = 0x0 Debug: 6672 21294 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_cfg15: 0x0 Debug: 6673 21294 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_cfg15 (valid=0). Debug: 6674 21294 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr0 Debug: 6675 21294 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr0 from target Debug: 6676 21294 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3024 Debug: 6677 21294 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3024 Debug: 6678 21294 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd0; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd0 Debug: 6679 21304 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3024 = 0x0 Debug: 6680 21304 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr0: 0x0 Debug: 6681 21304 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr0 (valid=0). Debug: 6682 21304 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr1 Debug: 6683 21304 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr1 from target Debug: 6684 21304 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3025 Debug: 6685 21304 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3025 Debug: 6686 21304 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd1; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd1 Debug: 6687 21313 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3025 = 0x0 Debug: 6688 21313 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr1: 0x0 Debug: 6689 21313 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr1 (valid=0). Debug: 6690 21313 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr2 Debug: 6691 21313 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr2 from target Debug: 6692 21313 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3026 Debug: 6693 21313 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3026 Debug: 6694 21313 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd2; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd2 Debug: 6695 21320 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3026 = 0x0 Debug: 6696 21320 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr2: 0x0 Debug: 6697 21320 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr2 (valid=0). Debug: 6698 21320 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr3 Debug: 6699 21320 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr3 from target Debug: 6700 21320 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3027 Debug: 6701 21320 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3027 Debug: 6702 21320 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd3; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd3 [OpenOCD] Debug: 6703 21328 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3027 = 0x0 Debug: 6704 21328 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr3: 0x0 Debug: 6705 21328 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr3 (valid=0). Debug: 6706 21328 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr4 Debug: 6707 21328 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr4 from target Debug: 6708 21328 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3028 Debug: 6709 21328 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3028 Debug: 6710 21328 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd4; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd4 Debug: 6711 21338 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3028 = 0x0 Debug: 6712 21338 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr4: 0x0 Debug: 6713 21338 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr4 (valid=0). Debug: 6714 21338 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr5 Debug: 6715 21338 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr5 from target Debug: 6716 21338 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3029 Debug: 6717 21338 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3029 Debug: 6718 21338 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd5; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd5 Debug: 6719 21348 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3029 = 0x0 Debug: 6720 21348 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr5: 0x0 Debug: 6721 21348 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr5 (valid=0). Debug: 6722 21348 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr6 Debug: 6723 21348 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr6 from target Debug: 6724 21348 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3030 Debug: 6725 21348 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3030 Debug: 6726 21348 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd6; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd6 Debug: 6727 21358 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3030 = 0x0 Debug: 6728 21358 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr6: 0x0 Debug: 6729 21358 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr6 (valid=0). Debug: 6730 21358 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr7 Debug: 6731 21358 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr7 from target Debug: 6732 21358 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3031 Debug: 6733 21358 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3031 Debug: 6734 21358 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd7; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd7 Debug: 6735 21370 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3031 = 0x0 Debug: 6736 21370 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr7: 0x0 Debug: 6737 21370 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr7 (valid=0). Debug: 6738 21370 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr8 Debug: 6739 21370 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr8 from target Debug: 6740 21370 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3032 Debug: 6741 21370 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3032 Debug: 6742 21370 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd8; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd8 Debug: 6743 21376 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3032 = 0x0 Debug: 6744 21376 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr8: 0x0 Debug: 6745 21376 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr8 (valid=0). Debug: 6746 21376 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr9 Debug: 6747 21376 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr9 from target Debug: 6748 21376 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3033 Debug: 6749 21376 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3033 Debug: 6750 21376 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bd9; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbd9 [OpenOCD] Debug: 6751 21387 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3033 = 0x0 Debug: 6752 21387 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr9: 0x0 Debug: 6753 21387 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr9 (valid=0). Debug: 6754 21387 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr10 Debug: 6755 21387 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr10 from target Debug: 6756 21387 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3034 Debug: 6757 21387 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3034 Debug: 6758 21387 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bda; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbda Debug: 6759 21430 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3034 = 0x0 Debug: 6760 21430 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr10: 0x0 Debug: 6761 21430 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr10 (valid=0). Debug: 6762 21430 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr11 Debug: 6763 21430 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr11 from target Debug: 6764 21430 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3035 Debug: 6765 21430 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3035 Debug: 6766 21430 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdb; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdb Debug: 6767 21450 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3035 = 0x0 Debug: 6768 21450 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr11: 0x0 Debug: 6769 21450 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr11 (valid=0). Debug: 6770 21450 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr12 Debug: 6771 21450 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr12 from target Debug: 6772 21450 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3036 Debug: 6773 21450 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3036 Debug: 6774 21450 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdc; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdc Debug: 6775 21461 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3036 = 0x0 Debug: 6776 21461 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr12: 0x0 Debug: 6777 21461 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr12 (valid=0). Debug: 6778 21461 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr13 Debug: 6779 21461 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr13 from target Debug: 6780 21461 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3037 Debug: 6781 21461 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3037 Debug: 6782 21461 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdd; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdd Debug: 6783 21468 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3037 = 0x0 Debug: 6784 21469 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr13: 0x0 Debug: 6785 21469 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr13 (valid=0). Debug: 6786 21469 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr14 Debug: 6787 21469 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr14 from target Debug: 6788 21469 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3038 Debug: 6789 21469 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3038 Debug: 6790 21469 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bde; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbde [OpenOCD] Debug: 6791 21486 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3038 = 0x0 Debug: 6792 21486 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr14: 0x0 Debug: 6793 21486 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr14 (valid=0). Debug: 6794 21486 esp_riscv.c:593 esp_riscv_start_algorithm(): save csr_pma_addr15 Debug: 6795 21486 riscv.c:4823 riscv_get_register(): [esp32c6] Reading csr_pma_addr15 from target Debug: 6796 21486 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3039 Debug: 6797 21486 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3039 Debug: 6798 21486 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220bdf; access register, size=32, postexec=0, transfer=1, write=0, regno=0xbdf Debug: 6799 21494 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3039 = 0x0 Debug: 6800 21494 riscv.c:4831 riscv_get_register(): [esp32c6] Read csr_pma_addr15: 0x0 Debug: 6801 21494 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from csr_pma_addr15 (valid=0). Debug: 6802 21494 esp_riscv.c:593 esp_riscv_start_algorithm(): save hpmcounter16 Debug: 6803 21494 riscv.c:4823 riscv_get_register(): [esp32c6] Reading hpmcounter16 from target Debug: 6804 21494 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register csr3088 Debug: 6805 21494 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading csr3088 Debug: 6806 21494 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10 Debug: 6807 21511 riscv-013.c:1561 register_read_direct(): [esp32c6] csr3088 = 0x3 Debug: 6808 21511 riscv.c:4831 riscv_get_register(): [esp32c6] Read hpmcounter16: 0x3 Debug: 6809 21511 riscv.c:5259 register_get(): [esp32c6] Read 0x00000003 from hpmcounter16 (valid=0). Debug: 6810 21511 esp_riscv.c:593 esp_riscv_start_algorithm(): save priv Debug: 6811 21511 riscv.c:4823 riscv_get_register(): [esp32c6] Reading priv from target Debug: 6812 21511 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register priv Debug: 6813 21511 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 6814 21511 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 6815 21521 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 6816 21521 riscv.c:4831 riscv_get_register(): [esp32c6] Read priv: 0x3 Debug: 6817 21521 riscv.c:5259 register_get(): [esp32c6] Read 0x03 from priv (valid=0). Debug: 6818 21521 esp_riscv.c:622 esp_riscv_start_algorithm(): set sp Debug: 6819 21521 riscv.c:5274 register_set(): [esp32c6] Write 0x40804780 to sp (valid=1). Debug: 6820 21521 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804780 to sp (cacheable=true, valid=true, dirty=false) Debug: 6821 21521 esp_riscv.c:622 esp_riscv_start_algorithm(): set a7 Debug: 6822 21521 riscv.c:5274 register_set(): [esp32c6] Write 0x4080110c to a7 (valid=1). Debug: 6823 21521 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4080110c to a7 (cacheable=true, valid=true, dirty=true) Debug: 6824 21521 esp_riscv.c:622 esp_riscv_start_algorithm(): set a0 Debug: 6825 21521 riscv.c:5274 register_set(): [esp32c6] Write 0x00000005 to a0 (valid=1). Debug: 6826 21521 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x5 to a0 (cacheable=true, valid=true, dirty=true) Debug: 6827 21521 esp_riscv.c:622 esp_riscv_start_algorithm(): set a1 Debug: 6828 21521 riscv.c:5274 register_set(): [esp32c6] Write 0xffffffff to a1 (valid=1). Debug: 6829 21521 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0xffffffff to a1 (cacheable=true, valid=true, dirty=true) Debug: 6830 21521 esp_riscv.c:622 esp_riscv_start_algorithm(): set a2 Debug: 6831 21521 riscv.c:5274 register_set(): [esp32c6] Write 0x40804794 to a2 (valid=1). Debug: 6832 21521 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804794 to a2 (cacheable=true, valid=true, dirty=true) Debug: 6833 21521 riscv.c:4550 riscv_interrupts_disable(): [esp32c6] Disabling interrupts. Debug: 6834 21521 riscv.c:4819 riscv_get_register(): [esp32c6] Read mstatus: 0x201800 (cached) Debug: 6835 21521 riscv.c:5259 register_get(): [esp32c6] Read 0x00201800 from mstatus (valid=1). Debug: 6836 21521 riscv.c:5274 register_set(): [esp32c6] Write 0x00201800 to mstatus (valid=1). Debug: 6837 21521 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x201800 to mstatus (cacheable=true, valid=true, dirty=false) Debug: 6838 21521 esp_riscv.c:659 esp_riscv_start_algorithm(): resume at 0x40801454 Debug: 6839 21521 riscv.c:1932 riscv_resume(): [esp32c6] current=false, address=0x40801454, handle_breakpoints=false, debug_exec=true Debug: 6840 21521 riscv.c:1937 riscv_resume(): [esp32c6] target->state=halted Debug: 6841 21521 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pc <- 0x40801454 (cacheable=false, valid=false, dirty=false) Debug: 6842 21521 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40801454 to register pc Debug: 6843 21521 riscv-013.c:4562 riscv013_set_register(): [esp32c6] writing PC to DPC: 0x40801454 Debug: 6844 21521 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40801454 to dpc Debug: 6845 21524 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 6846 21528 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40801454 Debug: 6847 21528 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40801454 to pc (cacheable=false, valid=false, dirty=false) Debug: 6848 21528 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[00] = DASM(0x0000100f) Debug: 6849 21528 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x100f @0 Debug: 6850 21528 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[01] = DASM(0x0330000f) Debug: 6851 21528 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x330000f @1 Debug: 6852 21528 program.c:36 riscv_program_write(): [esp32c6] debug_buffer[02] = DASM(0x00100073) Debug: 6853 21528 riscv-013.c:4827 riscv013_write_debug_buffer(): [esp32c6] Cache hit for 0x100073 @2 Debug: 6854 21528 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 6855 21532 riscv-013.c:1591 set_dcsr_ebreak(): [esp32c6] Set dcsr.ebreak* Debug: 6856 21532 riscv.c:4819 riscv_get_register(): [esp32c6] Read dcsr: 0x400090c3 (cached) Debug: 6857 21532 riscv.c:1575 riscv_flush_registers(): [esp32c6] a7 is dirty; write back 0x4080110c Debug: 6858 21532 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4080110c to register a7 Debug: 6859 21532 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4080110c to a7 Debug: 6860 21535 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 6861 21539 riscv-013.c:1532 register_write_direct(): [esp32c6] a7 <- 0x4080110c Debug: 6862 21539 riscv.c:1575 riscv_flush_registers(): [esp32c6] a2 is dirty; write back 0x40804794 Debug: 6863 21539 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40804794 to register a2 Debug: 6864 21539 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40804794 to a2 Debug: 6865 21541 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 6866 21544 riscv-013.c:1532 register_write_direct(): [esp32c6] a2 <- 0x40804794 Debug: 6867 21545 riscv.c:1575 riscv_flush_registers(): [esp32c6] a1 is dirty; write back 0xffffffff Debug: 6868 21545 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0xffffffff to register a1 Debug: 6869 21545 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0xffffffff to a1 Debug: 6870 21547 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 6871 21550 riscv-013.c:1532 register_write_direct(): [esp32c6] a1 <- 0xffffffff Debug: 6872 21550 riscv.c:1575 riscv_flush_registers(): [esp32c6] a0 is dirty; write back 0x5 Debug: 6873 21550 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x5 to register a0 Debug: 6874 21550 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x5 to a0 Debug: 6875 21554 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 6876 21558 riscv-013.c:1532 register_write_direct(): [esp32c6] a0 <- 0x5 Debug: 6877 21558 riscv.c:1858 resume_prep(): [esp32c6] Mark as prepped. Debug: 6878 21558 riscv.c:4536 riscv_resume_go_all_harts(): [esp32c6] Resuming hart, state=2. Debug: 6879 21558 riscv-013.c:4625 select_prepped_harts(): [esp32c6] index=0, coreid=0, prepped=1 Debug: 6880 21558 riscv-013.c:4922 riscv013_step_or_resume_current_hart(): [esp32c6] resuming (for step?=0) Debug: 6881 21565 riscv.c:4640 riscv_invalidate_register_cache(): [esp32c6] Invalidating register cache. Debug: 6882 21565 target.c:1812 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c6 Debug: 6883 21565 esp_algorithm.c:111 algorithm_run_image(): Wait algorithm completion Debug: 6884 21568 riscv.c:2779 riscv_poll_hart(): [esp32c6] triggered a halt; previous_target_state=4 Debug: 6885 21568 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 6886 21568 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 6887 21574 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x40009043 Debug: 6888 21574 riscv-013.c:4791 riscv013_halt_reason(): [esp32c6] dcsr.cause: 0x1 Debug: 6889 21574 riscv.c:1621 set_debug_reason(): [esp32c6] debug_reason=1 Debug: 6890 21574 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 6891 21574 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 6892 21574 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 6893 21574 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 6894 21580 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40801456 Debug: 6895 21580 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40801456 Debug: 6896 21580 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40801456 Debug: 6897 21580 esp_riscv.c:799 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40801452 Debug: 6898 21603 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6899 21604 riscv_semihosting.c:94 riscv_semihosting(): [esp32c6] compare 0x98820613 from 0x40801452 against 0x01f01013 Debug: 6900 21604 riscv_semihosting.c:96 riscv_semihosting(): [esp32c6] -> NONE (no magic) Debug: 6901 21604 target.c:1812 target_call_event_callbacks(): target event 17 (debug-halted) for core esp32c6 Debug: 6902 21604 riscv.c:4823 riscv_get_register(): [esp32c6] Reading pc from target Debug: 6903 21604 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register pc Debug: 6904 21604 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dpc Debug: 6905 21604 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 [OpenOCD] Debug: 6906 21614 riscv-013.c:1561 register_read_direct(): [esp32c6] dpc = 0x40801456 Debug: 6907 21614 riscv-013.c:4533 riscv013_get_register(): [esp32c6] read PC from DPC: 0x40801456 Debug: 6908 21614 riscv.c:4831 riscv_get_register(): [esp32c6] Read pc: 0x40801456 Debug: 6909 21614 riscv.c:5259 register_get(): [esp32c6] Read 0x40801456 from pc (valid=0). Debug: 6910 21614 riscv.c:4823 riscv_get_register(): [esp32c6] Reading a0 from target Debug: 6911 21614 riscv-013.c:4524 riscv013_get_register(): [esp32c6] reading register a0 Debug: 6912 21614 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading a0 Debug: 6913 21614 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 6914 21629 riscv-013.c:1561 register_read_direct(): [esp32c6] a0 = 0x0 Debug: 6915 21629 riscv.c:4831 riscv_get_register(): [esp32c6] Read a0: 0x0 Debug: 6916 21629 riscv.c:5259 register_get(): [esp32c6] Read 0x00000000 from a0 (valid=1). Debug: 6917 21629 esp_riscv.c:733 esp_riscv_wait_algorithm(): Read mem params Debug: 6918 21629 esp_riscv.c:735 esp_riscv_wait_algorithm(): Check mem param @ 0x40804794 Debug: 6919 21629 esp_riscv.c:737 esp_riscv_wait_algorithm(): Read mem param @ 0x40804794 Debug: 6920 21629 target.c:2444 target_read_buffer(): reading buffer of 28 byte at 0x40804794 Debug: 6921 21675 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to read memory via system bus. Debug: 6922 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore ra [OpenOCD] Debug: 6923 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x40801456 to ra (valid=0). Debug: 6924 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40801456 to ra (cacheable=true, valid=true, dirty=true) Debug: 6925 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore sp Debug: 6926 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x40804780 to sp (valid=0). Debug: 6927 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40804780 to sp (cacheable=true, valid=true, dirty=true) Debug: 6928 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore gp Debug: 6929 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to gp (valid=0). Debug: 6930 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to gp (cacheable=true, valid=true, dirty=true) Debug: 6931 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tp Debug: 6932 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tp (valid=0). Debug: 6933 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tp (cacheable=true, valid=true, dirty=true) Debug: 6934 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t0 Debug: 6935 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x40027bd4 to t0 (valid=0). Debug: 6936 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40027bd4 to t0 (cacheable=true, valid=true, dirty=true) Debug: 6937 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t1 Debug: 6938 21675 riscv.c:5274 register_set(): [esp32c6] Write 0xffffffe0 to t1 (valid=0). Debug: 6939 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0xffffffe0 to t1 (cacheable=true, valid=true, dirty=true) Debug: 6940 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t2 Debug: 6941 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t2 (valid=0). Debug: 6942 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t2 (cacheable=true, valid=true, dirty=true) Debug: 6943 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore fp Debug: 6944 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to fp (valid=0). Debug: 6945 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to fp (cacheable=true, valid=true, dirty=true) Debug: 6946 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s1 Debug: 6947 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s1 (valid=0). Debug: 6948 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s1 (cacheable=true, valid=true, dirty=true) Debug: 6949 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a0 Debug: 6950 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x20000000 to a0 (valid=1). Debug: 6951 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x20000000 to a0 (cacheable=true, valid=true, dirty=true) Debug: 6952 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a1 Debug: 6953 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x60002000 to a1 (valid=0). Debug: 6954 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x60002000 to a1 (cacheable=true, valid=true, dirty=true) Debug: 6955 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a2 Debug: 6956 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000010 to a2 (valid=0). Debug: 6957 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x10 to a2 (cacheable=true, valid=true, dirty=true) Debug: 6958 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a3 Debug: 6959 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00010000 to a3 (valid=0). Debug: 6960 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x10000 to a3 (cacheable=true, valid=true, dirty=true) Debug: 6961 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a4 Debug: 6962 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x408021e0 to a4 (valid=0). Debug: 6963 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x408021e0 to a4 (cacheable=true, valid=true, dirty=true) Debug: 6964 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a5 Debug: 6965 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000004 to a5 (valid=0). Debug: 6966 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x4 to a5 (cacheable=true, valid=true, dirty=true) Debug: 6967 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a6 Debug: 6968 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000008 to a6 (valid=0). Debug: 6969 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x8 to a6 (cacheable=true, valid=true, dirty=true) Debug: 6970 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore a7 Debug: 6971 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x80000000 to a7 (valid=0). Debug: 6972 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x80000000 to a7 (cacheable=true, valid=true, dirty=true) Debug: 6973 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s2 Debug: 6974 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s2 (valid=0). Debug: 6975 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s2 (cacheable=true, valid=true, dirty=true) Debug: 6976 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s3 Debug: 6977 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s3 (valid=0). Debug: 6978 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s3 (cacheable=true, valid=true, dirty=true) Debug: 6979 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s4 Debug: 6980 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s4 (valid=0). Debug: 6981 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s4 (cacheable=true, valid=true, dirty=true) Debug: 6982 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s5 Debug: 6983 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s5 (valid=0). Debug: 6984 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s5 (cacheable=true, valid=true, dirty=true) Debug: 6985 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s6 Debug: 6986 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s6 (valid=0). Debug: 6987 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s6 (cacheable=true, valid=true, dirty=true) Debug: 6988 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s7 Debug: 6989 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s7 (valid=0). Debug: 6990 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s7 (cacheable=true, valid=true, dirty=true) Debug: 6991 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s8 Debug: 6992 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s8 (valid=0). Debug: 6993 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s8 (cacheable=true, valid=true, dirty=true) Debug: 6994 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s9 Debug: 6995 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s9 (valid=0). Debug: 6996 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s9 (cacheable=true, valid=true, dirty=true) Debug: 6997 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s10 Debug: 6998 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s10 (valid=0). Debug: 6999 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s10 (cacheable=true, valid=true, dirty=true) Debug: 7000 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore s11 Debug: 7001 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to s11 (valid=0). Debug: 7002 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to s11 (cacheable=true, valid=true, dirty=true) Debug: 7003 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t3 Debug: 7004 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t3 (valid=0). Debug: 7005 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t3 (cacheable=true, valid=true, dirty=true) Debug: 7006 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t4 Debug: 7007 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t4 (valid=0). Debug: 7008 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t4 (cacheable=true, valid=true, dirty=true) Debug: 7009 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t5 Debug: 7010 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t5 (valid=0). Debug: 7011 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t5 (cacheable=true, valid=true, dirty=true) Debug: 7012 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore t6 Debug: 7013 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to t6 (valid=0). Debug: 7014 21675 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to t6 (cacheable=true, valid=true, dirty=true) Debug: 7015 21675 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pc Debug: 7016 21675 riscv.c:5274 register_set(): [esp32c6] Write 0x40000000 to pc (valid=0). Debug: 7017 21675 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pc <- 0x40000000 (cacheable=false, valid=false, dirty=false) Debug: 7018 21675 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40000000 to register pc Debug: 7019 21675 riscv-013.c:4562 riscv013_set_register(): [esp32c6] writing PC to DPC: 0x40000000 Debug: 7020 21675 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40000000 to dpc Debug: 7021 21679 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 7022 21685 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40000000 Debug: 7023 21685 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40000000 to pc (cacheable=false, valid=false, dirty=false) Debug: 7024 21685 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mstatus Debug: 7025 21685 riscv.c:5274 register_set(): [esp32c6] Write 0x00201800 to mstatus (valid=0). Debug: 7026 21685 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mstatus <- 0x201800 (cacheable=false, valid=false, dirty=false) Debug: 7027 21685 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x201800 to register mstatus Debug: 7028 21685 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x201800 to mstatus Debug: 7029 21689 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 7030 21694 riscv-013.c:1532 register_write_direct(): [esp32c6] mstatus <- 0x201800 Debug: 7031 21694 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x201800 to mstatus (cacheable=false, valid=false, dirty=false) Debug: 7032 21694 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore misa Debug: 7033 21694 riscv.c:5274 register_set(): [esp32c6] Write 0x40903105 to misa (valid=0). Debug: 7034 21694 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: misa <- 0x40903105 (cacheable=false, valid=false, dirty=false) Debug: 7035 21694 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40903105 to register misa Debug: 7036 21694 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40903105 to misa Debug: 7037 21697 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301 Debug: 7038 21704 riscv-013.c:1532 register_write_direct(): [esp32c6] misa <- 0x40903105 Debug: 7039 21704 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40903105 to misa (cacheable=false, valid=false, dirty=false) Debug: 7040 21704 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mtvec Debug: 7041 21704 riscv.c:5274 register_set(): [esp32c6] Write 0x00000001 to mtvec (valid=0). Debug: 7042 21704 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mtvec <- 0x1 (cacheable=false, valid=false, dirty=false) Debug: 7043 21704 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x1 to register csr773 Debug: 7044 21704 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x1 to csr773 Debug: 7045 21707 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305 Debug: 7046 21714 riscv-013.c:1532 register_write_direct(): [esp32c6] csr773 <- 0x1 Debug: 7047 21714 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x1 to mtvec (cacheable=false, valid=false, dirty=false) Debug: 7048 21714 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mscratch Debug: 7049 21714 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mscratch (valid=0). Debug: 7050 21714 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mscratch <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7051 21714 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr832 Debug: 7052 21714 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr832 Debug: 7053 21723 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340 Debug: 7054 21726 riscv-013.c:1532 register_write_direct(): [esp32c6] csr832 <- 0x0 Debug: 7055 21726 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mscratch (cacheable=false, valid=false, dirty=false) Debug: 7056 21726 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mepc Debug: 7057 21726 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mepc (valid=0). Debug: 7058 21726 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mepc <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7059 21726 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register mepc Debug: 7060 21726 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to mepc Debug: 7061 21729 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341 [OpenOCD] Debug: 7062 21733 riscv-013.c:1532 register_write_direct(): [esp32c6] mepc <- 0x0 Debug: 7063 21733 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mepc (cacheable=false, valid=false, dirty=false) Debug: 7064 21734 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mcause Debug: 7065 21734 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mcause (valid=0). Debug: 7066 21734 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mcause <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7067 21734 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register mcause Debug: 7068 21734 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to mcause Debug: 7069 21737 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342 Debug: 7070 21741 riscv-013.c:1532 register_write_direct(): [esp32c6] mcause <- 0x0 Debug: 7071 21741 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mcause (cacheable=false, valid=false, dirty=false) Debug: 7072 21741 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore mtval Debug: 7073 21741 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to mtval (valid=0). Debug: 7074 21741 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: mtval <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7075 21741 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr835 Debug: 7076 21741 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr835 Debug: 7077 21745 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343 Debug: 7078 21750 riscv-013.c:1532 register_write_direct(): [esp32c6] csr835 <- 0x0 Debug: 7079 21750 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to mtval (cacheable=false, valid=false, dirty=false) Debug: 7080 21750 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg0 Debug: 7081 21750 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg0 (valid=0). Debug: 7082 21750 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7083 21750 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr928 Debug: 7084 21750 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr928 Debug: 7085 21754 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0 Debug: 7086 21759 riscv-013.c:1532 register_write_direct(): [esp32c6] csr928 <- 0x0 Debug: 7087 21759 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg0 (cacheable=false, valid=false, dirty=false) Debug: 7088 21759 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg1 Debug: 7089 21759 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg1 (valid=0). Debug: 7090 21759 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7091 21759 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr929 Debug: 7092 21759 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr929 Debug: 7093 21771 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1 Debug: 7094 21790 riscv-013.c:1532 register_write_direct(): [esp32c6] csr929 <- 0x0 Debug: 7095 21790 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg1 (cacheable=false, valid=false, dirty=false) Debug: 7096 21790 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg2 Debug: 7097 21790 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg2 (valid=0). Debug: 7098 21790 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7099 21790 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr930 Debug: 7100 21790 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr930 Debug: 7101 21796 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2 [OpenOCD] Debug: 7102 21819 riscv-013.c:1532 register_write_direct(): [esp32c6] csr930 <- 0x0 Debug: 7103 21819 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg2 (cacheable=false, valid=false, dirty=false) Debug: 7104 21819 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpcfg3 Debug: 7105 21819 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpcfg3 (valid=0). Debug: 7106 21819 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpcfg3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7107 21819 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr931 Debug: 7108 21819 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr931 Debug: 7109 21827 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3 Debug: 7110 21841 riscv-013.c:1532 register_write_direct(): [esp32c6] csr931 <- 0x0 Debug: 7111 21841 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpcfg3 (cacheable=false, valid=false, dirty=false) Debug: 7112 21841 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr0 Debug: 7113 21841 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr0 (valid=0). Debug: 7114 21841 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7115 21841 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr944 Debug: 7116 21841 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr944 Debug: 7117 21855 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0 Debug: 7118 21866 riscv-013.c:1532 register_write_direct(): [esp32c6] csr944 <- 0x0 Debug: 7119 21866 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr0 (cacheable=false, valid=false, dirty=false) Debug: 7120 21866 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr1 Debug: 7121 21866 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr1 (valid=0). Debug: 7122 21866 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7123 21866 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr945 Debug: 7124 21866 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr945 Debug: 7125 21870 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1 Debug: 7126 21874 riscv-013.c:1532 register_write_direct(): [esp32c6] csr945 <- 0x0 Debug: 7127 21874 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr1 (cacheable=false, valid=false, dirty=false) Debug: 7128 21874 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr2 Debug: 7129 21874 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr2 (valid=0). Debug: 7130 21874 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7131 21874 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr946 Debug: 7132 21874 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr946 Debug: 7133 21877 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2 Debug: 7134 21882 riscv-013.c:1532 register_write_direct(): [esp32c6] csr946 <- 0x0 Debug: 7135 21882 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr2 (cacheable=false, valid=false, dirty=false) Debug: 7136 21882 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr3 Debug: 7137 21882 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr3 (valid=0). Debug: 7138 21882 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7139 21882 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr947 Debug: 7140 21882 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr947 Debug: 7141 21886 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3 [OpenOCD] Debug: 7142 21892 riscv-013.c:1532 register_write_direct(): [esp32c6] csr947 <- 0x0 Debug: 7143 21892 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr3 (cacheable=false, valid=false, dirty=false) Debug: 7144 21892 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr4 Debug: 7145 21892 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr4 (valid=0). Debug: 7146 21892 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7147 21892 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr948 Debug: 7148 21892 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr948 Debug: 7149 21896 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4 Debug: 7150 21902 riscv-013.c:1532 register_write_direct(): [esp32c6] csr948 <- 0x0 Debug: 7151 21902 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr4 (cacheable=false, valid=false, dirty=false) Debug: 7152 21902 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr5 Debug: 7153 21902 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr5 (valid=0). Debug: 7154 21902 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7155 21902 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr949 Debug: 7156 21902 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr949 Debug: 7157 21907 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5 Debug: 7158 21913 riscv-013.c:1532 register_write_direct(): [esp32c6] csr949 <- 0x0 Debug: 7159 21913 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr5 (cacheable=false, valid=false, dirty=false) Debug: 7160 21913 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr6 Debug: 7161 21913 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr6 (valid=0). Debug: 7162 21913 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7163 21913 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr950 Debug: 7164 21913 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr950 Debug: 7165 21917 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6 Debug: 7166 21924 riscv-013.c:1532 register_write_direct(): [esp32c6] csr950 <- 0x0 Debug: 7167 21924 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr6 (cacheable=false, valid=false, dirty=false) Debug: 7168 21924 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr7 Debug: 7169 21924 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr7 (valid=0). Debug: 7170 21924 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7171 21924 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr951 Debug: 7172 21924 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr951 Debug: 7173 21930 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7 Debug: 7174 21934 riscv-013.c:1532 register_write_direct(): [esp32c6] csr951 <- 0x0 Debug: 7175 21934 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr7 (cacheable=false, valid=false, dirty=false) Debug: 7176 21934 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr8 Debug: 7177 21934 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr8 (valid=0). Debug: 7178 21934 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7179 21934 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr952 Debug: 7180 21934 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr952 Debug: 7181 21937 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8 Debug: 7182 21941 riscv-013.c:1532 register_write_direct(): [esp32c6] csr952 <- 0x0 Debug: 7183 21941 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr8 (cacheable=false, valid=false, dirty=false) Debug: 7184 21941 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr9 Debug: 7185 21941 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr9 (valid=0). Debug: 7186 21941 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7187 21941 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr953 Debug: 7188 21941 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr953 Debug: 7189 21943 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9 Debug: 7190 21947 riscv-013.c:1532 register_write_direct(): [esp32c6] csr953 <- 0x0 Debug: 7191 21947 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr9 (cacheable=false, valid=false, dirty=false) Debug: 7192 21947 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr10 Debug: 7193 21947 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr10 (valid=0). Debug: 7194 21947 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7195 21947 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr954 Debug: 7196 21947 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr954 [OpenOCD] Debug: 7197 21950 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba Debug: 7198 21955 riscv-013.c:1532 register_write_direct(): [esp32c6] csr954 <- 0x0 Debug: 7199 21955 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr10 (cacheable=false, valid=false, dirty=false) Debug: 7200 21955 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr11 Debug: 7201 21955 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr11 (valid=0). Debug: 7202 21955 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7203 21955 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr955 Debug: 7204 21955 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr955 Debug: 7205 21958 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb Debug: 7206 21963 riscv-013.c:1532 register_write_direct(): [esp32c6] csr955 <- 0x0 Debug: 7207 21963 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr11 (cacheable=false, valid=false, dirty=false) Debug: 7208 21963 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr12 Debug: 7209 21963 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr12 (valid=0). Debug: 7210 21963 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7211 21963 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr956 Debug: 7212 21963 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr956 Debug: 7213 21966 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc Debug: 7214 21971 riscv-013.c:1532 register_write_direct(): [esp32c6] csr956 <- 0x0 Debug: 7215 21971 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr12 (cacheable=false, valid=false, dirty=false) Debug: 7216 21971 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr13 Debug: 7217 21971 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr13 (valid=0). Debug: 7218 21971 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7219 21971 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr957 Debug: 7220 21971 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr957 Debug: 7221 21974 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd Debug: 7222 21979 riscv-013.c:1532 register_write_direct(): [esp32c6] csr957 <- 0x0 Debug: 7223 21979 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr13 (cacheable=false, valid=false, dirty=false) Debug: 7224 21979 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr14 Debug: 7225 21979 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr14 (valid=0). Debug: 7226 21979 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7227 21979 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr958 Debug: 7228 21979 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr958 Debug: 7229 21988 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be Debug: 7230 22024 riscv-013.c:1532 register_write_direct(): [esp32c6] csr958 <- 0x0 Debug: 7231 22024 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr14 (cacheable=false, valid=false, dirty=false) Debug: 7232 22024 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore pmpaddr15 Debug: 7233 22024 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to pmpaddr15 (valid=0). Debug: 7234 22024 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: pmpaddr15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7235 22024 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr959 Debug: 7236 22024 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr959 Debug: 7237 22040 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf [OpenOCD] Debug: 7238 22046 riscv-013.c:1532 register_write_direct(): [esp32c6] csr959 <- 0x0 Debug: 7239 22046 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to pmpaddr15 (cacheable=false, valid=false, dirty=false) Debug: 7240 22046 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tselect Debug: 7241 22046 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tselect (valid=0). Debug: 7242 22046 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tselect <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7243 22046 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tselect Debug: 7244 22046 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tselect Debug: 7245 22053 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 7246 22062 riscv-013.c:1532 register_write_direct(): [esp32c6] tselect <- 0x0 Debug: 7247 22062 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tselect (cacheable=false, valid=false, dirty=false) Debug: 7248 22062 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tdata1 Debug: 7249 22062 riscv.c:5274 register_set(): [esp32c6] Write 0x23e00000 to tdata1 (valid=0). Debug: 7250 22062 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tdata1 <- 0x23e00000 (cacheable=false, valid=false, dirty=false) Debug: 7251 22062 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x23e00000 to register tdata1 Debug: 7252 22062 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x23e00000 to tdata1 Debug: 7253 22068 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1 Debug: 7254 22089 riscv-013.c:1532 register_write_direct(): [esp32c6] tdata1 <- 0x23e00000 Debug: 7255 22089 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x23e00000 to tdata1 (cacheable=false, valid=false, dirty=false) Debug: 7256 22089 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tdata2 Debug: 7257 22089 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tdata2 (valid=0). Debug: 7258 22089 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tdata2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7259 22089 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tdata2 Debug: 7260 22089 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tdata2 Debug: 7261 22095 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2 Debug: 7262 22103 riscv-013.c:1532 register_write_direct(): [esp32c6] tdata2 <- 0x0 Debug: 7263 22103 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tdata2 (cacheable=false, valid=false, dirty=false) Debug: 7264 22103 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore tcontrol Debug: 7265 22103 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to tcontrol (valid=0). Debug: 7266 22103 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: tcontrol <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7267 22103 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr1957 Debug: 7268 22103 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr1957 Debug: 7269 22106 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5 Debug: 7270 22109 riscv-013.c:1532 register_write_direct(): [esp32c6] csr1957 <- 0x0 Debug: 7271 22109 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to tcontrol (cacheable=false, valid=false, dirty=false) Debug: 7272 22109 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dcsr Debug: 7273 22109 riscv.c:5274 register_set(): [esp32c6] Write 0x400090c3 to dcsr (valid=0). Debug: 7274 22109 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dcsr <- 0x400090c3 (cacheable=false, valid=false, dirty=false) Debug: 7275 22109 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x400090c3 to register dcsr Debug: 7276 22109 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x400090c3 to dcsr Debug: 7277 22114 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 7278 22120 riscv-013.c:1532 register_write_direct(): [esp32c6] dcsr <- 0x400090c3 Debug: 7279 22120 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x400090c3 to dcsr (cacheable=false, valid=false, dirty=false) Debug: 7280 22120 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dpc Debug: 7281 22120 riscv.c:5274 register_set(): [esp32c6] Write 0x40000000 to dpc (valid=0). Debug: 7282 22120 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x40000000 to dpc (cacheable=true, valid=true, dirty=true) Debug: 7283 22120 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dscratch0 Debug: 7284 22120 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to dscratch0 (valid=0). Debug: 7285 22120 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dscratch0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7286 22120 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register dscratch0 Debug: 7287 22120 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to dscratch0 [OpenOCD] Debug: 7288 22123 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2 Debug: 7289 22128 riscv-013.c:1532 register_write_direct(): [esp32c6] dscratch0 <- 0x0 Debug: 7290 22128 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to dscratch0 (cacheable=false, valid=false, dirty=false) Debug: 7291 22128 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore dscratch1 Debug: 7292 22128 riscv.c:5274 register_set(): [esp32c6] Write 0x20000000 to dscratch1 (valid=0). Debug: 7293 22128 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: dscratch1 <- 0x20000000 (cacheable=false, valid=false, dirty=false) Debug: 7294 22128 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x20000000 to register csr1971 Debug: 7295 22128 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x20000000 to csr1971 Debug: 7296 22131 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3 Debug: 7297 22137 riscv-013.c:1532 register_write_direct(): [esp32c6] csr1971 <- 0x20000000 Debug: 7298 22137 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x20000000 to dscratch1 (cacheable=false, valid=false, dirty=false) Debug: 7299 22137 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpcer Debug: 7300 22137 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_mpcer (valid=0). Debug: 7301 22137 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpcer <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7302 22137 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2016 Debug: 7303 22137 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2016 Debug: 7304 22140 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e0 Debug: 7305 22145 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2016 <- 0x0 Debug: 7306 22145 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_mpcer (cacheable=false, valid=false, dirty=false) Debug: 7307 22145 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpcmr Debug: 7308 22145 riscv.c:5274 register_set(): [esp32c6] Write 0x00000003 to csr_mpcmr (valid=0). Debug: 7309 22145 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpcmr <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 7310 22145 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register csr2017 Debug: 7311 22145 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to csr2017 Debug: 7312 22149 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e1 Debug: 7313 22157 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2017 <- 0x3 Debug: 7314 22157 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to csr_mpcmr (cacheable=false, valid=false, dirty=false) Debug: 7315 22157 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_mpccr Debug: 7316 22157 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_mpccr (valid=0). Debug: 7317 22157 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_mpccr <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7318 22157 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2018 Debug: 7319 22157 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2018 Debug: 7320 22161 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307e2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7e2 Debug: 7321 22169 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2018 <- 0x0 Debug: 7322 22169 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_mpccr (cacheable=false, valid=false, dirty=false) Debug: 7323 22169 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_oen Debug: 7324 22169 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_oen (valid=0). Debug: 7325 22169 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_oen <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7326 22169 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2051 Debug: 7327 22169 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2051 Debug: 7328 22173 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230803; access register, size=32, postexec=0, transfer=1, write=1, regno=0x803 Debug: 7329 22178 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2051 <- 0x0 Debug: 7330 22178 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_oen (cacheable=false, valid=false, dirty=false) Debug: 7331 22178 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_in Debug: 7332 22178 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_in (valid=0). Debug: 7333 22178 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_in <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7334 22178 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2052 Debug: 7335 22178 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2052 Debug: 7336 22180 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230804; access register, size=32, postexec=0, transfer=1, write=1, regno=0x804 Debug: 7337 22185 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2052 <- 0x0 Debug: 7338 22185 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_in (cacheable=false, valid=false, dirty=false) Debug: 7339 22185 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_cpu_gpio_out Debug: 7340 22185 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_cpu_gpio_out (valid=0). Debug: 7341 22185 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_cpu_gpio_out <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7342 22185 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr2053 Debug: 7343 22185 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr2053 [OpenOCD] Debug: 7344 22189 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230805; access register, size=32, postexec=0, transfer=1, write=1, regno=0x805 Debug: 7345 22193 riscv-013.c:1532 register_write_direct(): [esp32c6] csr2053 <- 0x0 Debug: 7346 22193 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_cpu_gpio_out (cacheable=false, valid=false, dirty=false) Debug: 7347 22193 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg0 Debug: 7348 22193 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg0 (valid=0). Debug: 7349 22193 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7350 22193 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3008 Debug: 7351 22193 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3008 Debug: 7352 22196 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc0; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc0 Debug: 7353 22201 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3008 <- 0x0 Debug: 7354 22201 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg0 (cacheable=false, valid=false, dirty=false) Debug: 7355 22201 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg1 Debug: 7356 22201 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg1 (valid=0). Debug: 7357 22201 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7358 22201 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3009 Debug: 7359 22201 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3009 Debug: 7360 22205 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc1; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc1 Debug: 7361 22212 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3009 <- 0x0 Debug: 7362 22212 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg1 (cacheable=false, valid=false, dirty=false) Debug: 7363 22212 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg2 Debug: 7364 22212 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg2 (valid=0). Debug: 7365 22212 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7366 22212 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3010 Debug: 7367 22212 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3010 Debug: 7368 22249 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc2; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc2 Debug: 7369 22257 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3010 <- 0x0 Debug: 7370 22257 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg2 (cacheable=false, valid=false, dirty=false) Debug: 7371 22257 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg3 Debug: 7372 22257 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg3 (valid=0). Debug: 7373 22257 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7374 22257 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3011 Debug: 7375 22257 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3011 Debug: 7376 22264 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc3; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc3 Debug: 7377 22272 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3011 <- 0x0 Debug: 7378 22272 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg3 (cacheable=false, valid=false, dirty=false) Debug: 7379 22272 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg4 Debug: 7380 22272 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg4 (valid=0). Debug: 7381 22272 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7382 22272 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3012 Debug: 7383 22272 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3012 Debug: 7384 22279 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc4; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc4 [OpenOCD] Debug: 7385 22292 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3012 <- 0x0 Debug: 7386 22292 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg4 (cacheable=false, valid=false, dirty=false) Debug: 7387 22292 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg5 Debug: 7388 22292 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg5 (valid=0). Debug: 7389 22292 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7390 22292 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3013 Debug: 7391 22292 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3013 Debug: 7392 22302 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc5; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc5 Debug: 7393 22314 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3013 <- 0x0 Debug: 7394 22314 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg5 (cacheable=false, valid=false, dirty=false) Debug: 7395 22314 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg6 Debug: 7396 22314 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg6 (valid=0). Debug: 7397 22314 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7398 22314 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3014 Debug: 7399 22314 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3014 Debug: 7400 22322 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc6; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc6 Debug: 7401 22329 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3014 <- 0x0 Debug: 7402 22329 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg6 (cacheable=false, valid=false, dirty=false) Debug: 7403 22329 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg7 Debug: 7404 22329 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg7 (valid=0). Debug: 7405 22329 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7406 22329 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3015 Debug: 7407 22329 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3015 Debug: 7408 22336 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc7; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc7 Debug: 7409 22342 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3015 <- 0x0 Debug: 7410 22342 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg7 (cacheable=false, valid=false, dirty=false) Debug: 7411 22342 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg8 Debug: 7412 22342 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg8 (valid=0). Debug: 7413 22342 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7414 22342 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3016 Debug: 7415 22342 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3016 Debug: 7416 22347 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc8; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc8 Debug: 7417 22351 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3016 <- 0x0 Debug: 7418 22351 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg8 (cacheable=false, valid=false, dirty=false) Debug: 7419 22351 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg9 Debug: 7420 22351 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg9 (valid=0). Debug: 7421 22351 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7422 22351 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3017 Debug: 7423 22351 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3017 Debug: 7424 22354 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bc9; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbc9 Debug: 7425 22358 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3017 <- 0x0 Debug: 7426 22358 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg9 (cacheable=false, valid=false, dirty=false) Debug: 7427 22358 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg10 Debug: 7428 22358 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg10 (valid=0). Debug: 7429 22358 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7430 22358 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3018 Debug: 7431 22358 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3018 Debug: 7432 22362 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bca; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbca [OpenOCD] Debug: 7433 22366 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3018 <- 0x0 Debug: 7434 22366 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg10 (cacheable=false, valid=false, dirty=false) Debug: 7435 22366 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg11 Debug: 7436 22366 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg11 (valid=0). Debug: 7437 22366 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7438 22366 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3019 Debug: 7439 22366 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3019 Debug: 7440 22369 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcb; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcb Debug: 7441 22376 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3019 <- 0x0 Debug: 7442 22376 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg11 (cacheable=false, valid=false, dirty=false) Debug: 7443 22376 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg12 Debug: 7444 22376 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg12 (valid=0). Debug: 7445 22376 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7446 22376 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3020 Debug: 7447 22376 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3020 Debug: 7448 22379 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcc; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcc Debug: 7449 22386 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3020 <- 0x0 Debug: 7450 22386 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg12 (cacheable=false, valid=false, dirty=false) Debug: 7451 22386 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg13 Debug: 7452 22386 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg13 (valid=0). Debug: 7453 22386 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7454 22386 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3021 Debug: 7455 22386 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3021 Debug: 7456 22389 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcd; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcd Debug: 7457 22395 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3021 <- 0x0 Debug: 7458 22395 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg13 (cacheable=false, valid=false, dirty=false) Debug: 7459 22395 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg14 Debug: 7460 22395 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg14 (valid=0). Debug: 7461 22395 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7462 22395 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3022 Debug: 7463 22395 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3022 Debug: 7464 22398 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bce; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbce Debug: 7465 22413 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3022 <- 0x0 Debug: 7466 22413 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg14 (cacheable=false, valid=false, dirty=false) Debug: 7467 22413 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_cfg15 Debug: 7468 22413 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_cfg15 (valid=0). Debug: 7469 22413 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_cfg15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7470 22413 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3023 Debug: 7471 22413 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3023 Debug: 7472 22418 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bcf; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbcf Debug: 7473 22426 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3023 <- 0x0 Debug: 7474 22426 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_cfg15 (cacheable=false, valid=false, dirty=false) Debug: 7475 22426 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr0 Debug: 7476 22426 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr0 (valid=0). Debug: 7477 22426 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr0 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7478 22426 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3024 Debug: 7479 22426 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3024 [OpenOCD] Debug: 7480 22456 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd0; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd0 Debug: 7481 22464 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3024 <- 0x0 Debug: 7482 22465 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr0 (cacheable=false, valid=false, dirty=false) Debug: 7483 22465 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr1 Debug: 7484 22465 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr1 (valid=0). Debug: 7485 22465 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr1 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7486 22465 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3025 Debug: 7487 22465 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3025 Debug: 7488 22474 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd1; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd1 Debug: 7489 22495 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3025 <- 0x0 Debug: 7490 22495 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr1 (cacheable=false, valid=false, dirty=false) Debug: 7491 22495 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr2 Debug: 7492 22495 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr2 (valid=0). Debug: 7493 22495 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr2 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7494 22495 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3026 Debug: 7495 22495 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3026 Debug: 7496 22500 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd2; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd2 Debug: 7497 22508 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3026 <- 0x0 Debug: 7498 22508 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr2 (cacheable=false, valid=false, dirty=false) Debug: 7499 22508 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr3 Debug: 7500 22508 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr3 (valid=0). Debug: 7501 22508 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr3 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7502 22508 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3027 Debug: 7503 22508 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3027 Debug: 7504 22511 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd3; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd3 Debug: 7505 22515 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3027 <- 0x0 Debug: 7506 22515 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr3 (cacheable=false, valid=false, dirty=false) Debug: 7507 22515 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr4 Debug: 7508 22515 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr4 (valid=0). Debug: 7509 22515 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr4 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7510 22515 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3028 Debug: 7511 22515 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3028 Debug: 7512 22519 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd4; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd4 Debug: 7513 22525 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3028 <- 0x0 Debug: 7514 22525 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr4 (cacheable=false, valid=false, dirty=false) Debug: 7515 22525 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr5 Debug: 7516 22525 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr5 (valid=0). Debug: 7517 22525 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr5 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7518 22525 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3029 Debug: 7519 22525 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3029 [OpenOCD] Debug: 7520 22529 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd5; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd5 Debug: 7521 22536 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3029 <- 0x0 Debug: 7522 22537 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr5 (cacheable=false, valid=false, dirty=false) Debug: 7523 22537 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr6 Debug: 7524 22537 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr6 (valid=0). Debug: 7525 22537 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr6 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7526 22537 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3030 Debug: 7527 22537 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3030 Debug: 7528 22540 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd6; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd6 Debug: 7529 22547 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3030 <- 0x0 Debug: 7530 22547 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr6 (cacheable=false, valid=false, dirty=false) Debug: 7531 22547 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr7 Debug: 7532 22547 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr7 (valid=0). Debug: 7533 22547 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr7 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7534 22547 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3031 Debug: 7535 22547 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3031 Debug: 7536 22550 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd7; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd7 Debug: 7537 22556 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3031 <- 0x0 Debug: 7538 22556 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr7 (cacheable=false, valid=false, dirty=false) Debug: 7539 22556 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr8 Debug: 7540 22556 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr8 (valid=0). Debug: 7541 22556 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr8 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7542 22556 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3032 Debug: 7543 22556 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3032 Debug: 7544 22561 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd8; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd8 Debug: 7545 22566 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3032 <- 0x0 Debug: 7546 22567 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr8 (cacheable=false, valid=false, dirty=false) Debug: 7547 22567 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr9 Debug: 7548 22567 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr9 (valid=0). Debug: 7549 22567 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr9 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7550 22567 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3033 Debug: 7551 22567 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3033 Debug: 7552 22570 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bd9; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbd9 Debug: 7553 22575 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3033 <- 0x0 Debug: 7554 22575 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr9 (cacheable=false, valid=false, dirty=false) Debug: 7555 22575 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr10 Debug: 7556 22575 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr10 (valid=0). Debug: 7557 22575 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr10 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7558 22575 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3034 Debug: 7559 22575 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3034 Debug: 7560 22577 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bda; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbda Debug: 7561 22581 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3034 <- 0x0 Debug: 7562 22581 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr10 (cacheable=false, valid=false, dirty=false) Debug: 7563 22581 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr11 Debug: 7564 22581 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr11 (valid=0). Debug: 7565 22581 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr11 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7566 22581 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3035 Debug: 7567 22581 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3035 Debug: 7568 22583 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdb; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdb [OpenOCD] Debug: 7569 22589 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3035 <- 0x0 Debug: 7570 22589 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr11 (cacheable=false, valid=false, dirty=false) Debug: 7571 22589 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr12 Debug: 7572 22589 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr12 (valid=0). Debug: 7573 22589 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr12 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7574 22589 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3036 Debug: 7575 22589 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3036 Debug: 7576 22592 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdc; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdc Debug: 7577 22596 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3036 <- 0x0 Debug: 7578 22596 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr12 (cacheable=false, valid=false, dirty=false) Debug: 7579 22596 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr13 Debug: 7580 22596 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr13 (valid=0). Debug: 7581 22596 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr13 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7582 22596 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3037 Debug: 7583 22596 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3037 Debug: 7584 22600 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdd; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdd Debug: 7585 22607 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3037 <- 0x0 Debug: 7586 22607 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr13 (cacheable=false, valid=false, dirty=false) Debug: 7587 22607 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr14 Debug: 7588 22607 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr14 (valid=0). Debug: 7589 22607 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr14 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7590 22607 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3038 Debug: 7591 22607 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3038 Debug: 7592 22610 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bde; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbde Debug: 7593 22615 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3038 <- 0x0 Debug: 7594 22615 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr14 (cacheable=false, valid=false, dirty=false) Debug: 7595 22615 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore csr_pma_addr15 Debug: 7596 22615 riscv.c:5274 register_set(): [esp32c6] Write 0x00000000 to csr_pma_addr15 (valid=0). Debug: 7597 22615 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: csr_pma_addr15 <- 0x0 (cacheable=false, valid=false, dirty=false) Debug: 7598 22615 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register csr3039 Debug: 7599 22615 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to csr3039 Debug: 7600 22619 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230bdf; access register, size=32, postexec=0, transfer=1, write=1, regno=0xbdf Debug: 7601 22625 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3039 <- 0x0 Debug: 7602 22625 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x0 to csr_pma_addr15 (cacheable=false, valid=false, dirty=false) Debug: 7603 22625 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore hpmcounter16 Debug: 7604 22625 riscv.c:5274 register_set(): [esp32c6] Write 0x00000003 to hpmcounter16 (valid=0). Debug: 7605 22625 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: hpmcounter16 <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 7606 22625 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register csr3088 Debug: 7607 22625 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x3 to csr3088 Debug: 7608 22628 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10 Debug: 7609 22640 riscv-013.c:1532 register_write_direct(): [esp32c6] csr3088 <- 0x3 Debug: 7610 22640 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to hpmcounter16 (cacheable=false, valid=false, dirty=false) Debug: 7611 22640 esp_riscv.c:754 esp_riscv_wait_algorithm(): restore priv Debug: 7612 22640 riscv.c:5274 register_set(): [esp32c6] Write 0x03 to priv (valid=0). Debug: 7613 22640 riscv.c:4749 riscv_set_or_write_register(): [esp32c6] Writing to target: priv <- 0x3 (cacheable=false, valid=false, dirty=false) Debug: 7614 22640 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x3 to register priv Debug: 7615 22640 riscv-013.c:1541 register_read_direct(): [esp32c6] Reading dcsr Debug: 7616 22640 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 [OpenOCD] Debug: 7617 22699 riscv-013.c:1561 register_read_direct(): [esp32c6] dcsr = 0x400090c3 Debug: 7618 22699 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x400090c3 to dcsr Debug: 7619 22705 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 7620 22711 riscv-013.c:1532 register_write_direct(): [esp32c6] dcsr <- 0x400090c3 Debug: 7621 22711 riscv.c:4765 riscv_set_or_write_register(): [esp32c6] Wrote 0x3 to priv (cacheable=false, valid=false, dirty=false) Debug: 7622 22711 riscv.c:1575 riscv_flush_registers(): [esp32c6] dpc is dirty; write back 0x40000000 Debug: 7623 22711 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40000000 to register dpc Debug: 7624 22711 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40000000 to dpc Debug: 7625 22716 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 7626 22724 riscv-013.c:1532 register_write_direct(): [esp32c6] dpc <- 0x40000000 Debug: 7627 22724 riscv.c:1575 riscv_flush_registers(): [esp32c6] t6 is dirty; write back 0x0 Debug: 7628 22724 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t6 Debug: 7629 22724 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t6 Debug: 7630 22735 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f Debug: 7631 22741 riscv-013.c:1532 register_write_direct(): [esp32c6] t6 <- 0x0 Debug: 7632 22741 riscv.c:1575 riscv_flush_registers(): [esp32c6] t5 is dirty; write back 0x0 Debug: 7633 22741 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t5 Debug: 7634 22741 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t5 Debug: 7635 22743 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e Debug: 7636 22747 riscv-013.c:1532 register_write_direct(): [esp32c6] t5 <- 0x0 Debug: 7637 22747 riscv.c:1575 riscv_flush_registers(): [esp32c6] t4 is dirty; write back 0x0 Debug: 7638 22747 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t4 Debug: 7639 22747 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t4 Debug: 7640 22750 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d [OpenOCD] Debug: 7641 22756 riscv-013.c:1532 register_write_direct(): [esp32c6] t4 <- 0x0 Debug: 7642 22756 riscv.c:1575 riscv_flush_registers(): [esp32c6] t3 is dirty; write back 0x0 Debug: 7643 22756 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t3 Debug: 7644 22756 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t3 Debug: 7645 22759 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c Debug: 7646 22762 riscv-013.c:1532 register_write_direct(): [esp32c6] t3 <- 0x0 Debug: 7647 22763 riscv.c:1575 riscv_flush_registers(): [esp32c6] s11 is dirty; write back 0x0 Debug: 7648 22763 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s11 Debug: 7649 22763 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s11 Debug: 7650 22766 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b Debug: 7651 22772 riscv-013.c:1532 register_write_direct(): [esp32c6] s11 <- 0x0 Debug: 7652 22772 riscv.c:1575 riscv_flush_registers(): [esp32c6] s10 is dirty; write back 0x0 Debug: 7653 22772 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s10 Debug: 7654 22772 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s10 Debug: 7655 22776 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a Debug: 7656 22782 riscv-013.c:1532 register_write_direct(): [esp32c6] s10 <- 0x0 Debug: 7657 22782 riscv.c:1575 riscv_flush_registers(): [esp32c6] s9 is dirty; write back 0x0 Debug: 7658 22782 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s9 Debug: 7659 22782 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s9 Debug: 7660 22787 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019 Debug: 7661 22795 riscv-013.c:1532 register_write_direct(): [esp32c6] s9 <- 0x0 Debug: 7662 22795 riscv.c:1575 riscv_flush_registers(): [esp32c6] s8 is dirty; write back 0x0 Debug: 7663 22795 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s8 Debug: 7664 22795 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s8 Debug: 7665 22798 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018 Debug: 7666 22804 riscv-013.c:1532 register_write_direct(): [esp32c6] s8 <- 0x0 Debug: 7667 22804 riscv.c:1575 riscv_flush_registers(): [esp32c6] s7 is dirty; write back 0x0 Debug: 7668 22804 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s7 Debug: 7669 22804 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s7 Debug: 7670 22807 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017 Debug: 7671 22811 riscv-013.c:1532 register_write_direct(): [esp32c6] s7 <- 0x0 Debug: 7672 22811 riscv.c:1575 riscv_flush_registers(): [esp32c6] s6 is dirty; write back 0x0 Debug: 7673 22811 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s6 Debug: 7674 22811 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s6 Debug: 7675 22815 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016 [OpenOCD] Debug: 7676 22820 riscv-013.c:1532 register_write_direct(): [esp32c6] s6 <- 0x0 Debug: 7677 22820 riscv.c:1575 riscv_flush_registers(): [esp32c6] s5 is dirty; write back 0x0 Debug: 7678 22820 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s5 Debug: 7679 22820 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s5 Debug: 7680 22823 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015 Debug: 7681 22828 riscv-013.c:1532 register_write_direct(): [esp32c6] s5 <- 0x0 Debug: 7682 22828 riscv.c:1575 riscv_flush_registers(): [esp32c6] s4 is dirty; write back 0x0 Debug: 7683 22828 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s4 Debug: 7684 22828 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s4 Debug: 7685 22831 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014 Debug: 7686 22838 riscv-013.c:1532 register_write_direct(): [esp32c6] s4 <- 0x0 Debug: 7687 22838 riscv.c:1575 riscv_flush_registers(): [esp32c6] s3 is dirty; write back 0x0 Debug: 7688 22838 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s3 Debug: 7689 22838 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s3 Debug: 7690 22841 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013 Debug: 7691 22848 riscv-013.c:1532 register_write_direct(): [esp32c6] s3 <- 0x0 Debug: 7692 22848 riscv.c:1575 riscv_flush_registers(): [esp32c6] s2 is dirty; write back 0x0 Debug: 7693 22848 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s2 Debug: 7694 22848 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s2 Debug: 7695 22853 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012 Debug: 7696 22857 riscv-013.c:1532 register_write_direct(): [esp32c6] s2 <- 0x0 Debug: 7697 22858 riscv.c:1575 riscv_flush_registers(): [esp32c6] a7 is dirty; write back 0x80000000 Debug: 7698 22858 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x80000000 to register a7 Debug: 7699 22858 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x80000000 to a7 Debug: 7700 22860 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 7701 22864 riscv-013.c:1532 register_write_direct(): [esp32c6] a7 <- 0x80000000 Debug: 7702 22864 riscv.c:1575 riscv_flush_registers(): [esp32c6] a6 is dirty; write back 0x8 Debug: 7703 22864 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x8 to register a6 Debug: 7704 22864 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x8 to a6 Debug: 7705 22867 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010 Debug: 7706 22873 riscv-013.c:1532 register_write_direct(): [esp32c6] a6 <- 0x8 Debug: 7707 22873 riscv.c:1575 riscv_flush_registers(): [esp32c6] a5 is dirty; write back 0x4 Debug: 7708 22873 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x4 to register a5 Debug: 7709 22873 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x4 to a5 Debug: 7710 22875 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f Debug: 7711 22879 riscv-013.c:1532 register_write_direct(): [esp32c6] a5 <- 0x4 Debug: 7712 22879 riscv.c:1575 riscv_flush_registers(): [esp32c6] a4 is dirty; write back 0x408021e0 Debug: 7713 22879 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x408021e0 to register a4 Debug: 7714 22879 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x408021e0 to a4 [OpenOCD] Debug: 7715 22883 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e Debug: 7716 22887 riscv-013.c:1532 register_write_direct(): [esp32c6] a4 <- 0x408021e0 Debug: 7717 22887 riscv.c:1575 riscv_flush_registers(): [esp32c6] a3 is dirty; write back 0x10000 Debug: 7718 22887 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x10000 to register a3 Debug: 7719 22887 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x10000 to a3 Debug: 7720 22896 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d Debug: 7721 22907 riscv-013.c:1532 register_write_direct(): [esp32c6] a3 <- 0x10000 Debug: 7722 22907 riscv.c:1575 riscv_flush_registers(): [esp32c6] a2 is dirty; write back 0x10 Debug: 7723 22907 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x10 to register a2 Debug: 7724 22907 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x10 to a2 Debug: 7725 22912 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 7726 22919 riscv-013.c:1532 register_write_direct(): [esp32c6] a2 <- 0x10 Debug: 7727 22920 riscv.c:1575 riscv_flush_registers(): [esp32c6] a1 is dirty; write back 0x60002000 Debug: 7728 22920 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x60002000 to register a1 Debug: 7729 22920 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x60002000 to a1 Debug: 7730 22924 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 7731 22933 riscv-013.c:1532 register_write_direct(): [esp32c6] a1 <- 0x60002000 Debug: 7732 22933 riscv.c:1575 riscv_flush_registers(): [esp32c6] a0 is dirty; write back 0x20000000 Debug: 7733 22933 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x20000000 to register a0 Debug: 7734 22933 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x20000000 to a0 Debug: 7735 22938 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 7736 22945 riscv-013.c:1532 register_write_direct(): [esp32c6] a0 <- 0x20000000 Debug: 7737 22945 riscv.c:1575 riscv_flush_registers(): [esp32c6] s1 is dirty; write back 0x0 Debug: 7738 22945 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s1 Debug: 7739 22945 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s1 Debug: 7740 22950 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 7741 22955 riscv-013.c:1532 register_write_direct(): [esp32c6] s1 <- 0x0 Debug: 7742 22955 riscv.c:1575 riscv_flush_registers(): [esp32c6] fp is dirty; write back 0x0 Debug: 7743 22955 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register s0 Debug: 7744 22955 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to s0 Debug: 7745 22958 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 7746 22965 riscv-013.c:1532 register_write_direct(): [esp32c6] s0 <- 0x0 Debug: 7747 22965 riscv.c:1575 riscv_flush_registers(): [esp32c6] t2 is dirty; write back 0x0 Debug: 7748 22965 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register t2 Debug: 7749 22965 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to t2 [OpenOCD] Debug: 7750 22971 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007 Debug: 7751 22977 riscv-013.c:1532 register_write_direct(): [esp32c6] t2 <- 0x0 Debug: 7752 22977 riscv.c:1575 riscv_flush_registers(): [esp32c6] t1 is dirty; write back 0xffffffe0 Debug: 7753 22977 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0xffffffe0 to register t1 Debug: 7754 22977 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0xffffffe0 to t1 Debug: 7755 22984 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006 Debug: 7756 22993 riscv-013.c:1532 register_write_direct(): [esp32c6] t1 <- 0xffffffe0 Debug: 7757 22993 riscv.c:1575 riscv_flush_registers(): [esp32c6] t0 is dirty; write back 0x40027bd4 Debug: 7758 22993 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40027bd4 to register t0 Debug: 7759 22993 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40027bd4 to t0 Debug: 7760 22996 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005 Debug: 7761 23002 riscv-013.c:1532 register_write_direct(): [esp32c6] t0 <- 0x40027bd4 Debug: 7762 23002 riscv.c:1575 riscv_flush_registers(): [esp32c6] tp is dirty; write back 0x0 Debug: 7763 23002 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register tp Debug: 7764 23002 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to tp Debug: 7765 23006 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004 Debug: 7766 23012 riscv-013.c:1532 register_write_direct(): [esp32c6] tp <- 0x0 Debug: 7767 23012 riscv.c:1575 riscv_flush_registers(): [esp32c6] gp is dirty; write back 0x0 Debug: 7768 23012 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x0 to register gp Debug: 7769 23012 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x0 to gp Debug: 7770 23020 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003 Debug: 7771 23025 riscv-013.c:1532 register_write_direct(): [esp32c6] gp <- 0x0 Debug: 7772 23025 riscv.c:1575 riscv_flush_registers(): [esp32c6] sp is dirty; write back 0x40804780 Debug: 7773 23025 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40804780 to register sp Debug: 7774 23025 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40804780 to sp Debug: 7775 23031 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 7776 23042 riscv-013.c:1532 register_write_direct(): [esp32c6] sp <- 0x40804780 Debug: 7777 23042 riscv.c:1575 riscv_flush_registers(): [esp32c6] ra is dirty; write back 0x40801456 Debug: 7778 23042 riscv-013.c:4554 riscv013_set_register(): [esp32c6] writing 0x40801456 to register ra Debug: 7779 23042 riscv-013.c:1513 register_write_direct(): [esp32c6] Writing 0x40801456 to ra Debug: 7780 23059 riscv-013.c:806 execute_abstract_command(): [esp32c6] command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001 Debug: 7781 23071 riscv-013.c:1532 register_write_direct(): [esp32c6] ra <- 0x40801456 Debug: 7782 23071 esp_algorithm.c:130 algorithm_run_image(): Got algorithm RC 0x0 Debug: 7783 23076 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804794 Debug: 7784 23080 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 7785 23080 target.c:2138 target_free_working_area_restore(): freed 28 bytes of working area at address 0x40804794 Debug: 7786 23080 target.c:1938 print_wa_layout(): b* 0x40800000-0x40801453 (5204 bytes) Debug: 7787 23080 target.c:1938 print_wa_layout(): b* 0x40801454-0x40801457 (4 bytes) Debug: 7788 23080 target.c:1938 print_wa_layout(): * 0x40801458-0x40803fff (11176 bytes) Debug: 7789 23080 target.c:1938 print_wa_layout(): b* 0x40804000-0x4080427f (640 bytes) Debug: 7790 23080 target.c:1938 print_wa_layout(): b* 0x40804280-0x40804793 (1300 bytes) Debug: 7791 23080 target.c:1938 print_wa_layout(): 0x40804794-0x40823fff (129132 bytes) Debug: 7792 23080 esp.c:259 esp_common_assist_debug_monitor_restore(): [esp32c6] value 0x00000000 addr 0x600c2000 Debug: 7793 23080 target.c:2686 target_write_u32(): address: 0x600c2000, value: 0x00000000 [OpenOCD] Debug: 7794 23086 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x600c2000 Debug: 7795 23090 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 7796 23090 target.c:2166 target_free_all_working_areas_restore(): freeing all working areas Debug: 7797 23111 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800000 Debug: 7798 23132 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800200 Debug: 7799 23144 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800400 Debug: 7800 23153 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800600 Debug: 7801 23163 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800800 Debug: 7802 23174 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800a00 [OpenOCD] Debug: 7803 23186 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800c00 Debug: 7804 23196 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40800e00 Debug: 7805 23207 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801000 Debug: 7806 23219 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801200 Debug: 7807 23229 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801400 Debug: 7808 23233 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 7809 23238 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40801454 [OpenOCD] Debug: 7810 23242 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 7811 23248 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804000 Debug: 7812 23255 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804200 Debug: 7813 23260 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 7814 23266 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804280 Debug: 7815 23315 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804480 [OpenOCD] Debug: 7816 23338 riscv-013.c:4116 write_memory_bus_v1(): [esp32c6] Transferring burst starting at address 0x40804680 Debug: 7817 23346 riscv-013.c:3166 log_mem_access_result(): [esp32c6] Succeeded to write memory via system bus. Debug: 7818 23346 target.c:1938 print_wa_layout(): 0x40800000-0x40823fff (147456 bytes) Info : 7819 23346 esp_flash.c:412 esp_algo_flash_get_mappings(): Flash mapping 0: 0x20020 -> 0x42020020, 55 KB Info : 7820 23346 esp_flash.c:412 esp_algo_flash_get_mappings(): Flash mapping 1: 0x30020 -> 0x42000020, 109 KB Info : 7821 23346 esp_flash.c:1013 esp_algo_flash_probe(): Using flash bank 'esp32c6.drom' size 56 KB Debug: 7822 23346 esp_flash.c:1030 esp_algo_flash_probe(): allocated 14 sectors Debug: 7823 23346 gdb_server.c:1056 gdb_new_connection(): New GDB Connection: 1, Target esp32c6, state: halted Debug: 7824 23346 gdb_server.c:375 gdb_log_incoming_packet(): [esp32c6] received packet: qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+;memory-tagging+ Debug: 7825 23346 riscv.c:2402 riscv_get_gdb_reg_list_internal(): [esp32c6] reg_class=0, read=0 Debug: 7826 23346 gdb_server.c:392 gdb_log_outgoing_packet(): [esp32c6] sending packet: $PacketSize=4000;qXfer:memory-map:read+;qXfer:features:read+;qXfer:threads:read+;QStartNoAckMode+;vContSupported+#02 Warn : 7827 23346 gdb_server.c:343 gdb_write(): Error writing to GDB socket. Dropping the connection. Debug: 7828 23346 gdb_server.c:1101 gdb_connection_closed(): GDB Close, Target: esp32c6, state: halted, gdb_actual_connections=0 Debug: 7829 23346 target.c:1812 target_call_event_callbacks(): target event 8 (gdb-end) for core esp32c6 Debug: 7830 23346 target.c:1812 target_call_event_callbacks(): target event 23 (gdb-detach) for core esp32c6 Debug: 7831 23346 target.c:5047 target_handle_event(): target(0): esp32c6 (esp32c6) event: 23 (gdb-detach) action: $_TARGETNAME_0 esp gdb_detach_handler Debug: 7832 23346 command.c:151 script_debug(): command - esp32c6 esp gdb_detach_handler Info : 7833 23351 server.c:575 server_loop(): dropped 'gdb' connection [Debug Adapter] 2024-02-01 10:21:14,882 - Gdb - DEBUG - MI<-: [{'message': None, 'payload': 'Ignoring packet error, continuing...\\n', 'stream': 'stdout', 'type': 'console'}, {'message': None, 'payload': 'warning: unrecognized item \\"timeout\\" in \\"qSupported\\" ' 'response\\n', 'stream': 'stdout', 'type': 'log'}, {'message': None, 'payload': 'Ignoring packet error, continuing...\\n', 'stream': 'stdout', 'type': 'console'}, {'message': 'error', 'payload': {'msg': "Remote replied unexpectedly to 'vMustReplyEmpty': " 'timeout'}, 'stream': 'stdout', 'token': None, 'type': 'result'}] 2024-02-01 10:21:14,883 - Gdb - INFO - CONS: 'Ignoring packet error, continuing...\\n' 2024-02-01 10:21:14,883 - Gdb - DEBUG - LOG: 'warning: unrecognized item \\"timeout\\" in \\"qSupported\\" response\\n' 2024-02-01 10:21:14,883 - Gdb - INFO - CONS: 'Ignoring packet error, continuing...\\n' 2024-02-01 10:21:14,883 - Gdb - DEBUG - RESULT: error {'msg': "Remote replied unexpectedly to 'vMustReplyEmpty': timeout"} [Debug Adapter] 2024-02-01 10:21:14,883 - Debug Adapter (main) - ERROR - Failed to connect to "remote 127.0.0.1:3333"! Traceback (most recent call last): File "/home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter/command_processor.py", line 52, in __call__ on_request(protocol_message) File "/home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter/command_processor.py", line 75, in on_initialize_request raise e File "/home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter/command_processor.py", line 70, in on_initialize_request self.da.adapter_init() File "/home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter/debug_adapter.py", line 329, in adapter_init raise e File "/home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter/debug_adapter.py", line 325, in adapter_init self.start_gdb() File "/home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter/debug_adapter.py", line 678, in start_gdb raise e File "/home/slawek/.vscode-server/extensions/espressif.esp-idf-extension-1.7.0/esp_debug_adapter/debug_adapter/debug_adapter.py", line 675, in start_gdb self._gdb.connect() File "/home/slawek/.espressif_v52-beta1/python_env/idf5.2_py3.10_env/lib/python3.10/site-packages/esp_debug_backend/gdb.py", line 599, in connect self.target_select(remote_mode, self._remote_target, tmo=tmo) File "/home/slawek/.espressif_v52-beta1/python_env/idf5.2_py3.10_env/lib/python3.10/site-packages/esp_debug_backend/gdb.py", line 265, in target_select raise DebuggerError('Failed to connect to "%s %s"!' % (tgt_type, tgt_params)) esp_debug_backend.defs.DebuggerError: Failed to connect to "remote 127.0.0.1:3333"! 2024-02-01 10:21:14,883 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "response", "request_seq": 1, "success": false, "command": "initialize", "seq": 7, "message": "Failed to init Debug Adapter!", "body": {}} 2024-02-01 10:21:14,884 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Failed to connect to \"remote 127.0.0.1:3333\"!\n", "source": {}}, "seq": 8} 2024-02-01 10:21:14,884 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Failed to connect to \"remote 127.0.0.1:3333\"!\n", "source": {}}, "seq": 9} [Debug Adapter] 2024-02-01 10:21:14,909 - Debug Adapter (ReaderThread) - DEBUG - read line: >>b'Content-Length: 79\\r\\n'<< 2024-02-01 10:21:14,909 - Debug Adapter (ReaderThread) - DEBUG - read line: >>b'\\r\\n'<< 2024-02-01 10:21:14,909 - Debug Adapter(Command Processor) - DEBUG - Got json: { "arguments": { "restart": false }, "command": "disconnect", "seq": 2, "type": "request" } 2024-02-01 10:21:14,909 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Got json: {\n \"arguments\": {\n \"restart\": false\n },\n \"command\": \"disconnect\",\n \"seq\": 2,\n \"type\": \"request\"\n}\n", "source": {}}, "seq": 10} 2024-02-01 10:21:14,910 - Debug Adapter (main) - DEBUG - Adapter is Stopping... 2024-02-01 10:21:14,910 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Debug Adapter stopped\n", "source": {}}, "seq": 11} 2024-02-01 10:21:14,910 - Debug Adapter (main) - DEBUG - Stopping target poller 2024-02-01 10:21:14,911 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Adapter is Stopping...\n", "source": {}}, "seq": 12} 2024-02-01 10:21:14,911 - Debug Adapter (main) - DEBUG - Closing the GDB process 2024-02-01 10:21:14,911 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Stopping target poller\n", "source": {}}, "seq": 13} 2024-02-01 10:21:14,911 - Debug Adapter (main) - DEBUG - Closing the Socket 2024-02-01 10:21:14,911 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Closing the GDB process\n", "source": {}}, "seq": 14} 2024-02-01 10:21:14,912 - Debug Adapter (main) - DEBUG - Stopping of the Writer thread 2024-02-01 10:21:14,912 - Debug Adapter (WriterThread) - DEBUG - Writing: {"type": "event", "event": "output", "body": {"output": "Closing the Socket\n", "source": {}}, "seq": 15} 2024-02-01 10:21:14,912 - Debug Adapter (main) - DEBUG - Stopping of the Reader thread 2024-02-01 10:21:14,912 - Debug Adapter (main) - DEBUG - Adapter is Stopped DEBUG_ADAPTER_STOPPED 2024-02-01 10:21:14,912 - Debug Adapter (main) - CRITICAL - Debug adapter -> Extension: DEBUG_ADAPTER_STOPPED 2024-02-01 10:21:14,912 - Debug Adapter(Command Processor) - DEBUG - Processed command: disconnect [Stopped] : ESP-IDF Debug Adapter