make[1]: Entering directory '/home/Robert/esp/esp-idf/tools/kconfig'
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o mconf.o mconf.c
flex -L -P zconf -o zconf.lex.c zconf.l
bison -t -l -p zconf -o zconf.tab.c zconf.y
sed -E "s/\\x0D$//" zconf.gperf | gperf -t --output-file zconf.hash.c -a -C -E -g -k '1,3,$' -p -t
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o zconf.tab.o zconf.tab.c
lxdialog/check-lxdialog.sh -check /usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD -lncursesw -lintl
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o lxdialog/checklist.o lxdialog/checklist.c
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o lxdialog/util.o lxdialog/util.c
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o lxdialog/inputbox.o lxdialog/inputbox.c
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o lxdialog/textbox.o lxdialog/textbox.c
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o lxdialog/yesno.o lxdialog/yesno.c
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o lxdialog/menubox.o lxdialog/menubox.c
/usr/bin/gcc -o mconf mconf.o zconf.tab.o lxdialog/checklist.o lxdialog/util.o lxdialog/inputbox.o lxdialog/textbox.o lxdialog/yesno.o lxdialog/menubox.o -lncursesw -lintl
/usr/bin/gcc  -I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"  -DNCURSES_WIDECHAR=1 -DLOCALE -MD   -c -o conf.o conf.c
/usr/bin/gcc -o conf conf.o  zconf.tab.o -lncursesw -lintl
make[1]: Leaving directory '/home/Robert/esp/esp-idf/tools/kconfig'
GENCONFIG
*
* Restart config...
*
*
* Bootloader config
*
Bootloader log verbosity
  1. No output (LOG_BOOTLOADER_LEVEL_NONE)
  2. Error (LOG_BOOTLOADER_LEVEL_ERROR)
> 3. Warning (LOG_BOOTLOADER_LEVEL_WARN)
  4. Info (LOG_BOOTLOADER_LEVEL_INFO)
  5. Debug (LOG_BOOTLOADER_LEVEL_DEBUG)
  6. Verbose (LOG_BOOTLOADER_LEVEL_VERBOSE)
choice[1-6?]: 3
VDDSDIO LDO voltage
  1. 1.8V (BOOTLOADER_VDDSDIO_BOOST_1_8V)
> 2. 1.9V (BOOTLOADER_VDDSDIO_BOOST_1_9V)
choice[1-2?]: 2
GPIO triggers factory reset (BOOTLOADER_FACTORY_RESET) [N/y/?] (NEW) N
GPIO triggers boot from test app partition (BOOTLOADER_APP_TEST) [N/y/?] (NEW) N
*
* Partition Table
*
Partition Table
> 1. Single factory app, no OTA (PARTITION_TABLE_SINGLE_APP)
  2. Factory app, two OTA definitions (PARTITION_TABLE_TWO_OTA)
  3. Custom partition table CSV (PARTITION_TABLE_CUSTOM)
choice[1-3?]: 1
Offset of partition table (PARTITION_TABLE_OFFSET) [0x8000] (NEW) 1
Generate an MD5 checksum for the partition table (PARTITION_TABLE_MD5) [Y/n/?] (NEW) Y
*
* Compiler options
*
Optimization Level
> 1. Debug (-Og) (OPTIMIZATION_LEVEL_DEBUG)
  2. Release (-Os) (OPTIMIZATION_LEVEL_RELEASE)
choice[1-2?]: 1
Assertion level
> 1. Enabled (OPTIMIZATION_ASSERTIONS_ENABLED)
  2. Silent (saves code size) (OPTIMIZATION_ASSERTIONS_SILENT)
  3. Disabled (sets -DNDEBUG) (OPTIMIZATION_ASSERTIONS_DISABLED)
choice[1-3?]: 1
Stack smashing protection mode
> 1. None (STACK_CHECK_NONE)
  2. Normal (STACK_CHECK_NORM)
  3. Strong (STACK_CHECK_STRONG)
  4. Overall (STACK_CHECK_ALL)
choice[1-4?]: 1
Enable -Wwrite-strings warning flag (WARN_WRITE_STRINGS) [N/y/?] (NEW) N
*
* ADC configuration
*
Use the FSM to control ADC power (ADC_FORCE_XPD_FSM) [N/y/?] (NEW) N
Disable DAC when ADC2 is used on GPIO 25 and 26 (ADC2_DISABLE_DAC) [Y/n/?] (NEW) Y
*
* SPI configuration
*
Place transmitting functions of SPI master into IRAM (SPI_MASTER_IN_IRAM) [N/y/?] (NEW) N
Place SPI master ISR function into IRAM (SPI_MASTER_ISR_IN_IRAM) [Y/n/?] (NEW) Y
Place transmitting functions of SPI slave into IRAM (SPI_SLAVE_IN_IRAM) [N/y/?] (NEW) N
Place SPI slave ISR function into IRAM (SPI_SLAVE_ISR_IN_IRAM) [Y/n/?] (NEW) Y
*
* ESP32-specific
*
CPU frequency
  1. 80 MHz (ESP32_DEFAULT_CPU_FREQ_80)
  2. 160 MHz (ESP32_DEFAULT_CPU_FREQ_160)
> 3. 240 MHz (ESP32_DEFAULT_CPU_FREQ_240)
choice[1-3?]: 3
Support for external, SPI-connected RAM (SPIRAM_SUPPORT) [N/y/?] n
Use TRAX tracing feature (ESP32_TRAX) [N/y/?] n
Core dump destination
  1. Flash (ESP32_ENABLE_COREDUMP_TO_FLASH)
  2. UART (ESP32_ENABLE_COREDUMP_TO_UART)
> 3. None (ESP32_ENABLE_COREDUMP_TO_NONE)
choice[1-3?]: 3
Number of universally administered (by IEEE) MAC address
  1. Two (TWO_UNIVERSAL_MAC_ADDRESS)
> 2. Four (FOUR_UNIVERSAL_MAC_ADDRESS)
choice[1-2?]: 2
System event queue size (SYSTEM_EVENT_QUEUE_SIZE) [32] 32
Event loop task stack size (SYSTEM_EVENT_TASK_STACK_SIZE) [2048] 2048
Main task stack size (MAIN_TASK_STACK_SIZE) [4096] 4096
Inter-Processor Call (IPC) task stack size (IPC_TASK_STACK_SIZE) [1024] 1024
High-resolution timer task stack size (TIMER_TASK_STACK_SIZE) [3584] 3584
Line ending for UART output
> 1. CRLF (NEWLIB_STDOUT_LINE_ENDING_CRLF)
  2. LF (NEWLIB_STDOUT_LINE_ENDING_LF)
  3. CR (NEWLIB_STDOUT_LINE_ENDING_CR)
choice[1-3?]: 1
Line ending for UART input
  1. CRLF (NEWLIB_STDIN_LINE_ENDING_CRLF)
  2. LF (NEWLIB_STDIN_LINE_ENDING_LF)
> 3. CR (NEWLIB_STDIN_LINE_ENDING_CR)
choice[1-3?]: 3
Enable 'nano' formatting options for printf/scanf family (NEWLIB_NANO_FORMAT) [N/y/?] n
UART for console output
> 1. Default: UART0, TX=GPIO1, RX=GPIO3 (CONSOLE_UART_DEFAULT)
  2. Custom (CONSOLE_UART_CUSTOM)
  3. None (CONSOLE_UART_NONE)
choice[1-3?]: 1
UART console baud rate (CONSOLE_UART_BAUDRATE) [115200] 115200
Enable Ultra Low Power (ULP) Coprocessor (ULP_COPROC_ENABLED) [N/y/?] n
Panic handler behaviour
  1. Print registers and halt (ESP32_PANIC_PRINT_HALT)
> 2. Print registers and reboot (ESP32_PANIC_PRINT_REBOOT)
  3. Silent reboot (ESP32_PANIC_SILENT_REBOOT)
  4. Invoke GDBStub (ESP32_PANIC_GDBSTUB)
choice[1-4?]: 2
Make exception and panic handlers JTAG/OCD aware (ESP32_DEBUG_OCDAWARE) [Y/n/?] y
OpenOCD debug stubs (ESP32_DEBUG_STUBS_ENABLE) [Y/n/?] (NEW) Y
Interrupt watchdog (INT_WDT) [Y/n/?] y
  Interrupt watchdog timeout (ms) (INT_WDT_TIMEOUT_MS) [300] 300
  Also watch CPU1 tick interrupt (INT_WDT_CHECK_CPU1) [Y/n/?] y
Initialize Task Watchdog Timer on startup (TASK_WDT) [Y/n/?] y
  Invoke panic handler on Task Watchdog timeout (TASK_WDT_PANIC) [N/y/?] n
  Task Watchdog timeout period (seconds) (TASK_WDT_TIMEOUT_S) [5] 5
  Watch CPU0 Idle Task (TASK_WDT_CHECK_IDLE_TASK_CPU0) [Y/n/?] y
  Watch CPU1 Idle Task (TASK_WDT_CHECK_IDLE_TASK_CPU1) [Y/n/?] y
Hardware brownout detect & reset (BROWNOUT_DET) [Y/n/?] y
  Brownout voltage level
  > 1. 2.43V +/- 0.05 (BROWNOUT_DET_LVL_SEL_0)
    2. 2.48V +/- 0.05 (BROWNOUT_DET_LVL_SEL_1)
    3. 2.58V +/- 0.05 (BROWNOUT_DET_LVL_SEL_2)
    4. 2.62V +/- 0.05 (BROWNOUT_DET_LVL_SEL_3)
    5. 2.67V +/- 0.05 (BROWNOUT_DET_LVL_SEL_4)
    6. 2.70V +/- 0.05 (BROWNOUT_DET_LVL_SEL_5)
    7. 2.77V +/- 0.05 (BROWNOUT_DET_LVL_SEL_6)
    8. 2.80V +/- 0.05 (BROWNOUT_DET_LVL_SEL_7)
  choice[1-8?]: 1
Timers used for gettimeofday function
> 1. RTC and high-resolution timer (ESP32_TIME_SYSCALL_USE_RTC_FRC1)
  2. RTC (ESP32_TIME_SYSCALL_USE_RTC)
  3. High-resolution timer (ESP32_TIME_SYSCALL_USE_FRC1)
  4. None (ESP32_TIME_SYSCALL_USE_NONE)
choice[1-4?]: 1
RTC clock source
> 1. Internal 150kHz RC oscillator (ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC)
  2. External 32kHz crystal (ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL)
  3. External 32kHz oscillator at 32K_XP pin (ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC) (NEW)
  4. Internal 8.5MHz oscillator, divided by 256 (~33kHz) (ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256) (NEW)
choice[1-4?]: 1
Number of cycles for RTC_SLOW_CLK calibration (ESP32_RTC_CLK_CAL_CYCLES) [1024] 1024
Extra delay in deep sleep wake stub (in us) (ESP32_DEEP_SLEEP_WAKEUP_DELAY) [2000] 2000
Main XTAL frequency
> 1. 40 MHz (ESP32_XTAL_FREQ_40)
  2. 26 MHz (ESP32_XTAL_FREQ_26)
  3. Autodetect (ESP32_XTAL_FREQ_AUTO)
choice[1-3?]: 1
Permanently disable BASIC ROM Console (DISABLE_BASIC_ROM_CONSOLE) [N/y/?] n
No Binary Blobs (NO_BLOBS) [N/y/?] n
Enable esp_timer profiling features (ESP_TIMER_PROFILING) [N/y/?] n
App compatible with bootloaders before IDF v2.1 (COMPATIBLE_PRE_V2_1_BOOTLOADERS) [N/y/?] n
Enable lookup of error code strings (ESP_ERR_TO_NAME_LOOKUP) [Y/n/?] (NEW) Y
*
* Wi-Fi
*
Max number of WiFi static RX buffers (ESP32_WIFI_STATIC_RX_BUFFER_NUM) [10] 10
Max number of WiFi dynamic RX buffers (ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM) [32] 32
Type of WiFi TX buffers
  1. Static (ESP32_WIFI_STATIC_TX_BUFFER)
> 2. Dynamic (ESP32_WIFI_DYNAMIC_TX_BUFFER)
choice[1-2?]: 2
Max number of WiFi dynamic TX buffers (ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM) [32] 32
WiFi CSI(Channel State Information) (ESP32_WIFI_CSI_ENABLED) [N/y/?] (NEW) N
WiFi AMPDU TX (ESP32_WIFI_AMPDU_TX_ENABLED) [Y/n/?] y
  WiFi AMPDU TX BA window size (ESP32_WIFI_TX_BA_WIN) [6] 6
WiFi AMPDU RX (ESP32_WIFI_AMPDU_RX_ENABLED) [Y/n/?] y
  WiFi AMPDU RX BA window size (ESP32_WIFI_RX_BA_WIN) [6] 6
WiFi NVS flash (ESP32_WIFI_NVS_ENABLED) [Y/n/?] y
WiFi Task Core ID
> 1. Core 0 (ESP32_WIFI_TASK_PINNED_TO_CORE_0) (NEW)
  2. Core 1 (ESP32_WIFI_TASK_PINNED_TO_CORE_1) (NEW)
choice[1-2?]: 1
*
* ESP HTTP client
*
Enable https (ESP_HTTP_CLIENT_ENABLE_HTTPS) [Y/n/?] (NEW) Y
*
* Ethernet
*
Number of DMA RX buffers (DMA_RX_BUF_NUM) [10] 10
Number of DMA TX buffers (DMA_TX_BUF_NUM) [10] 10
Enable copy between Layer2 and Layer3 (EMAC_L2_TO_L3_RX_BUF_MODE) [N/y/?] n
Period(ms) of checking Ethernet linkup status (EMAC_CHECK_LINK_PERIOD_MS) [2000] (NEW)
EMAC_TASK_PRIORITY (EMAC_TASK_PRIORITY) [20] 20
*
* HTTP Server
*
Max HTTP Request Header Length (HTTPD_MAX_REQ_HDR_LEN) [512] (NEW)
Max HTTP URI Length (HTTPD_MAX_URI_LEN) [512] (NEW)
*
* LWIP
*
Enable copy between Layer2 and Layer3 packets (L2_TO_L3_COPY) [N/y/?] n
Enable LWIP IRAM optimization (LWIP_IRAM_OPTIMIZATION) [N/y/?] (NEW)
Max number of open sockets (LWIP_MAX_SOCKETS) [4] 4
Support LWIP socket select() only (USE_ONLY_LWIP_SELECT) [N/y/?] (NEW)
Enable SO_REUSEADDR option (LWIP_SO_REUSE) [N/y/?] n
Enable SO_RCVBUF option (LWIP_SO_RCVBUF) [Y/?] y
Maximum number of NTP servers (LWIP_DHCP_MAX_NTP_SERVERS) [1] 1
Enable fragment outgoing IP packets (LWIP_IP_FRAG) [N/y/?] n
Enable reassembly incoming fragmented IP packets (LWIP_IP_REASSEMBLY) [N/y/?] n
Enable LWIP statistics (LWIP_STATS) [N/y/?] n
Enable LWIP ARP trust (LWIP_ETHARP_TRUST_IP_MAC) [Y/n/?] y
TCPIP task receive mail box size (TCPIP_RECVMBOX_SIZE) [32] 32
DHCP: Perform ARP check on any offered address (LWIP_DHCP_DOES_ARP_CHECK) [Y/n/?] y
TCP/IP Task Stack Size (TCPIP_TASK_STACK_SIZE) [2048] 2048
*
* mbedTLS
*
Enable custom mbedTLS memory allocation layer. (MBEDTLS_PLATFORM_MEMORY) [N/y/?] (NEW)
TLS maximum message content length (MBEDTLS_SSL_MAX_CONTENT_LEN) [16384] 16384
Enable mbedTLS debugging (MBEDTLS_DEBUG) [N/y/?] n
Enable hardware AES acceleration (MBEDTLS_HARDWARE_AES) [Y/n/?] y
Enable hardware MPI (bignum) acceleration (MBEDTLS_HARDWARE_MPI) [Y/n/?] y
  Use interrupt for MPI operations (MBEDTLS_MPI_USE_INTERRUPT) [Y/n/?] y
Enable hardware SHA acceleration (MBEDTLS_HARDWARE_SHA) [N/y/?] n
Enable mbedtls time (MBEDTLS_HAVE_TIME) [Y/n/?] y
  Enable mbedtls time data (MBEDTLS_HAVE_TIME_DATE) [N/y/?] n
TLS Protocol Role
> 1. Server & Client (MBEDTLS_TLS_SERVER_AND_CLIENT)
  2. Server (MBEDTLS_TLS_SERVER_ONLY)
  3. Client (MBEDTLS_TLS_CLIENT_ONLY)
  4. None (MBEDTLS_TLS_DISABLED)
choice[1-4?]: 1
Support TLS renegotiation (MBEDTLS_SSL_RENEGOTIATION) [Y/n/?] y
Legacy SSL 3.0 support (MBEDTLS_SSL_PROTO_SSL3) [N/y/?] n
Support TLS 1.0 protocol (MBEDTLS_SSL_PROTO_TLS1) [Y/n] y
Support TLS 1.1 protocol (MBEDTLS_SSL_PROTO_TLS1_1) [Y/n] y
Support TLS 1.2 protocol (MBEDTLS_SSL_PROTO_TLS1_2) [Y/n] y
Support DTLS protocol (all versions) (MBEDTLS_SSL_PROTO_DTLS) [N/y/?] n
Support ALPN (Application Layer Protocol Negotiation) (MBEDTLS_SSL_ALPN) [Y/n/?] y
TLS: Support RFC 5077 SSL session tickets (MBEDTLS_SSL_SESSION_TICKETS) [Y/n/?] y
Enable RIPEMD-160 hash algorithm (MBEDTLS_RIPEMD160_C) [N/y/?] n
*
* mDNS
*
Max number of services (MDNS_MAX_SERVICES) [10] (NEW)
*
* SPIFFS Configuration
*
Maximum Number of Partitions (SPIFFS_MAX_PARTITIONS) [3] 3
Enable SPIFFS Page Check (SPIFFS_PAGE_CHECK) [Y/n/?] y
Set Maximum GC Runs (SPIFFS_GC_MAX_RUNS) [10] 10
Enable SPIFFS GC Statistics (SPIFFS_GC_STATS) [N/y/?] n
SPIFFS logical page size (SPIFFS_PAGE_SIZE) [256] (NEW)
Set SPIFFS Maximum Name Length (SPIFFS_OBJ_NAME_LEN) [32] 32
Enable SPIFFS Filesystem Magic (SPIFFS_USE_MAGIC) [Y/n/?] y
  Enable SPIFFS Filesystem Length Magic (SPIFFS_USE_MAGIC_LENGTH) [Y/n/?] y
Size of per-file metadata field (SPIFFS_META_LENGTH) [4] 4
  Save file modification time (SPIFFS_USE_MTIME) [Y/n/?] y
*
* TCP/IP Adapter
*
IP Address lost timer interval (seconds) (IP_LOST_TIMER_INTERVAL) [120] 120
TCP/IP Stack Library
> 1. LwIP (TCPIP_LWIP) (NEW)
choice[1]: 1
*
* Virtual file system
*
Suppress select() related debug outputs (SUPPRESS_SELECT_DEBUG_OUTPUT) [Y/n/?] (NEW)
#
# configuration written to /home/Robert/esp/eita/sdkconfig
#
CC build/bootloader/bootloader_support/src/bootloader_random.o
CC build/bootloader/bootloader_support/src/flash_encrypt.o
CC build/bootloader/bootloader_support/src/bootloader_sha.o
CC build/bootloader/bootloader_support/src/esp_image_format.o
CC build/bootloader/bootloader_support/src/flash_partitions.o
CC build/bootloader/bootloader_support/src/secure_boot_signatures.o
CC build/bootloader/bootloader_support/src/bootloader_clock.o
CC build/bootloader/bootloader_support/src/secure_boot.o
CC build/bootloader/bootloader_support/src/bootloader_common.o
CC build/bootloader/bootloader_support/src/bootloader_utility.o
CC build/bootloader/bootloader_support/src/bootloader_init.o
CC build/bootloader/bootloader_support/src/efuse.o
CC build/bootloader/bootloader_support/src/flash_qio_mode.o
CC build/bootloader/bootloader_support/src/bootloader_flash.o
AR build/bootloader/bootloader_support/libbootloader_support.a
CC build/bootloader/log/log.o
AR build/bootloader/log/liblog.a
CC build/bootloader/spi_flash/spi_flash_rom_patch.o
AR build/bootloader/spi_flash/libspi_flash.a
CC build/bootloader/micro-ecc/micro-ecc/uECC.o
AR build/bootloader/micro-ecc/libmicro-ecc.a
CC build/bootloader/soc/esp32/rtc_clk.o
CC build/bootloader/soc/esp32/rtc_time.o
CC build/bootloader/soc/esp32/rtc_sleep.o
CC build/bootloader/soc/esp32/gpio_periph.o
CC build/bootloader/soc/esp32/rtc_clk_init.o
CC build/bootloader/soc/esp32/spi_periph.o
CC build/bootloader/soc/esp32/rtc_init.o
CC build/bootloader/soc/esp32/sdio_slave_periph.o
CC build/bootloader/soc/esp32/rtc_wdt.o
CC build/bootloader/soc/esp32/sdmmc_periph.o
CC build/bootloader/soc/esp32/cpu_util.o
CC build/bootloader/soc/esp32/rtc_periph.o
CC build/bootloader/soc/esp32/rtc_pm.o
CC build/bootloader/soc/esp32/soc_memory_layout.o
CC build/bootloader/soc/src//memory_layout_utils.o
AR build/bootloader/soc/libsoc.a
CC build/bootloader/main/flash_qio_mode.o
In file included from C:/msys32/home/Robert/esp/esp-idf/components/esp32/include/rom/ets_sys.h:21:0,
                 from C:/msys32/home/Robert/esp/esp-idf/components/log/include/esp_log.h:21,
                 from C:/msys32/home/Robert/esp/esp-idf/components/bootloader/subproject/main/flash_qio_mode.c:17:
C:/msys32/home/Robert/esp/esp-idf/components/bootloader/subproject/main/flash_qio_mode.c: In function 'enable_qio_mode':
C:/msys32/home/Robert/esp/esp-idf/components/bootloader/subproject/main/flash_qio_mode.c:179:66: error: 'EFUSE_RD_CHIP_VER_RESERVE_S' undeclared (first use in this function)
         uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE);
                                                                  ^
C:/msys32/home/Robert/esp/esp-idf/components/soc/esp32/include/soc/soc.h:191:32: note: in definition of macro 'REG_GET_FIELD'
             ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
                                ^
C:/msys32/home/Robert/esp/esp-idf/components/bootloader/subproject/main/flash_qio_mode.c:179:66: note: each undeclared identifier is reported only once for each function it appears in
         uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE);
                                                                  ^
C:/msys32/home/Robert/esp/esp-idf/components/soc/esp32/include/soc/soc.h:191:32: note: in definition of macro 'REG_GET_FIELD'
             ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
                                ^
C:/msys32/home/Robert/esp/esp-idf/components/bootloader/subproject/main/flash_qio_mode.c:179:66: error: 'EFUSE_RD_CHIP_VER_RESERVE_V' undeclared (first use in this function)
         uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE);
                                                                  ^
C:/msys32/home/Robert/esp/esp-idf/components/soc/esp32/include/soc/soc.h:191:44: note: in definition of macro 'REG_GET_FIELD'
             ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
                                            ^
make[2]: *** [/home/Robert/esp/esp-idf/make/component_wrapper.mk:286: flash_qio_mode.o] Error 1
make[1]: *** [/home/Robert/esp/esp-idf/make/project.mk:481: component-main-build] Error 2
make: *** [/home/Robert/esp/esp-idf/components/bootloader/Makefile.projbuild:41: /home/Robert/esp/eita/build/bootloader/bootloader.bin] Error 2

