I saw that new implementation connects gpio to gpio out signal when set direction.
I think one pad can be connected to only one signal. Then the serial signal are disconnected.
static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
{
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output ...
Search found 6 matches
- Fri Apr 12, 2024 8:32 pm
- Forum: General Discussion
- Topic: TX UART open drain mode
- Replies: 3
- Views: 3454
- Fri Apr 12, 2024 7:44 pm
- Forum: General Discussion
- Topic: TX UART open drain mode
- Replies: 3
- Views: 3454
Re: TX UART open drain mode
Did you found a way to use od in uart tx?
In esp-idf 4.4 it works using:
But not in 5.2.
In esp-idf 4.4 it works using:
Code: Select all
gpio_set_direction(tx_io_num, GPIO_MODE_OUTPUT_OD)- Fri Jun 21, 2019 11:58 am
- Forum: ESP-IDF
- Topic: Use of UART_RX_IDLE_THRHD
- Replies: 2
- Views: 3543
Re: Use of UART_RX_IDLE_THRHD
I do not think so. I activated all interrupts and set multiple values for this property, but I could not find what it would be.
UART_BRK_DET_INT: Triggered when the receiver detects at 0 level after the STOP bit.
UART_TX_BRK_IDLE_DONE_INT: Triggered when the transmitter's idle state has been kept ...
UART_BRK_DET_INT: Triggered when the receiver detects at 0 level after the STOP bit.
UART_TX_BRK_IDLE_DONE_INT: Triggered when the transmitter's idle state has been kept ...
- Wed Jun 19, 2019 8:22 pm
- Forum: ESP-IDF
- Topic: Use of UART_RX_IDLE_THRHD
- Replies: 2
- Views: 3543
Use of UART_RX_IDLE_THRHD
Hi,
there is a configuration "UART_RX_IDLE_THRHD" on UART, but I don't found any use for it.
Can someone explain the use of "UART_RX_IDLE_THRHD"?
From Reference Manual (p.361):
UART_RX_IDLE_THRHD When the receiver takes more time to receive Byte data than what this
register indicates, it will ...
there is a configuration "UART_RX_IDLE_THRHD" on UART, but I don't found any use for it.
Can someone explain the use of "UART_RX_IDLE_THRHD"?
From Reference Manual (p.361):
UART_RX_IDLE_THRHD When the receiver takes more time to receive Byte data than what this
register indicates, it will ...
- Wed May 29, 2019 6:31 pm
- Forum: ESP-IDF
- Topic: UART Baud Timing Pattern Interrupt / J1708
- Replies: 4
- Views: 5211
Re: UART Baud Timing Pattern Interrupt / J1708
For APB_CLK as source for UART, it's 10 baud cycles, i.e., 100 bits (without parity).
But I don't know what is the default source clock. I think it's APB_CLK.
From Reference Manual:
UART_RX_TOUT_THRHD This register is used to configure the UART receiver’s timeout value when receiving a byte. When ...
But I don't know what is the default source clock. I think it's APB_CLK.
From Reference Manual:
UART_RX_TOUT_THRHD This register is used to configure the UART receiver’s timeout value when receiving a byte. When ...
- Tue May 28, 2019 5:54 pm
- Forum: ESP-IDF
- Topic: UART Baud Timing Pattern Interrupt / J1708
- Replies: 4
- Views: 5211
UART Baud Timing Pattern Interrupt / J1708
Hi,
I want to implement J1708 with ESP32. J1708 is a modified version of RS485.
I am using RS485 UART with modified tranceiver and everything is going well for sending and receiving data.
But the J1708 has a standard of time to distinguish messages. It's simple:
After a message, consisting of a ...
I want to implement J1708 with ESP32. J1708 is a modified version of RS485.
I am using RS485 UART with modified tranceiver and everything is going well for sending and receiving data.
But the J1708 has a standard of time to distinguish messages. It's simple:
After a message, consisting of a ...