Should be possible to achieve this in the wake-up stub. I suggest not complicating it with interrupts etc, simply polling for the gpio in the stub sounds like it should be sufficient? It is not like your CPU will be doing anything else while in the stub anyways.
Not sure what you mean by "hang-up ...
Search found 78 matches
- Wed May 06, 2026 1:50 am
- Forum: General Discussion
- Topic: ESP32C3 wakeup from deepsleep and quickly capture data pulses on a GPIO
- Replies: 3
- Views: 68
- Fri Jan 30, 2026 2:45 am
- Forum: ESP-IDF
- Topic: ESP32C2 data retention between deep-sleep resets
- Replies: 4
- Views: 383
Re: ESP32C2 data retention between deep-sleep resets
FWIW I have long abused the RTC_x_DATE_REG registers on ESP32 without issue. They don't seem to have any purpose and are RW.
Yeah, that is another good option, but DATE_REGs are also occasionally used for "patching" stuff. So if IDF ever does need another RTC STORE register this is probably the ...
- Fri Jan 30, 2026 2:01 am
- Forum: ESP-IDF
- Topic: ESP32C2 data retention between deep-sleep resets
- Replies: 4
- Views: 383
Re: ESP32C2 data retention between deep-sleep resets
As far as I see you are correct. Those registers dont have any available space you can use without conflicts with IDF functionality.
The other way I could think of is to "abuse" other RTC related registers. One example would be RTC_CNTL_WDTCONFIG4_REG which has the stage 3 hold time for the RTC WDT ...
The other way I could think of is to "abuse" other RTC related registers. One example would be RTC_CNTL_WDTCONFIG4_REG which has the stage 3 hold time for the RTC WDT ...
- Mon Sep 22, 2025 7:17 am
- Forum: ESP-IDF
- Topic: ULP core program stops after deep sleep
- Replies: 2
- Views: 812
Re: ULP core program stops after deep sleep
Seems like the issue here is that if esp_sleep_enable_ulp_wakeup() is not set then the sleep code do not correctly keep the RTC periph powered on. Causing it the ULP to get powered down.
We'll take a look at it.
We'll take a look at it.
- Wed Nov 22, 2023 3:29 am
- Forum: General Discussion
- Topic: Getting Wake Cause in Wake Stub not working on S3
- Replies: 3
- Views: 5427
Re: Getting Wake Cause in Wake Stub not working on S3
Looking at the TRM, RTC_CNTL_WAKEUP_STATE_REG does not seem to be the correct register for reading the wake-up cause on S3. RTC_CNTL_WAKEUP_CAUSE is from RTC_CNTL_SLP_WAKEUP_CAUSE_REG
You can take a look at rtc_cntl_ll_get_wakeup_cause() to see how it is done on different chips (you could use this ...
You can take a look at rtc_cntl_ll_get_wakeup_cause() to see how it is done on different chips (you could use this ...
- Fri Oct 22, 2021 3:20 am
- Forum: Hardware
- Topic: RSA peripheral 50% slower on ESP32-S3/C3 than S2?
- Replies: 11
- Views: 20888
Re: RSA peripheral 50% slower on ESP32-S3/C3 than S2?
Sorry, as far as I know there is no secret registers that allow you to perform just one modular multiplication instead of two on these newer chips.
I'll forward the question to the guy on our digital team responsible for this peripheral and see if he has any ideas, but most likely there isn't any ...
I'll forward the question to the guy on our digital team responsible for this peripheral and see if he has any ideas, but most likely there isn't any ...
- Mon Oct 18, 2021 2:48 am
- Forum: Hardware
- Topic: RSA peripheral 50% slower on ESP32-S3/C3 than S2?
- Replies: 11
- Views: 20888
Re: RSA peripheral 50% slower on ESP32-S3/C3 than S2?
You are correct that the peripheral is the same, but the way we access the memory has changed and unfortunately this means the RSA on C3/S3 will be slower than S2, but still an improvement from ESP32. 50% seems to be within the expected range.
I see that the TRM RSA performance data for S3/C3 do ...
I see that the TRM RSA performance data for S3/C3 do ...
- Fri Oct 15, 2021 1:50 am
- Forum: ESP-IDF
- Topic: ESP download modes
- Replies: 5
- Views: 12286
Re: ESP download modes
Hi,
Any updates regarding how to enable the "Permanently switch to Secure mode (recommended) option?
SECURE_ENABLE_SECURE_ROM_DL_MODE is only supported on S2 and later chips, so that's why you are unable to enable it. Sorry for your confusion, the latest docs have a note mentioning that it is ...
Any updates regarding how to enable the "Permanently switch to Secure mode (recommended) option?
SECURE_ENABLE_SECURE_ROM_DL_MODE is only supported on S2 and later chips, so that's why you are unable to enable it. Sorry for your confusion, the latest docs have a note mentioning that it is ...
- Thu Sep 02, 2021 2:37 am
- Forum: ESP-IDF
- Topic: esp_aes_gcm_finish(): assert triggered (BUG?)
- Replies: 4
- Views: 4602
Re: esp_aes_gcm_finish(): assert triggered (BUG?)
Hi,
Yeah this looks like a bug. I think the length here should always be 16 bytes, and for smaller tags it should be clipped afterwards.
I'll look into and fix this. In the meanwhile you should be able to bypass this by disabling MBEDTLS_HARDWARE_GCM if this is issue is a blocker for you.
Yeah this looks like a bug. I think the length here should always be 16 bytes, and for smaller tags it should be clipped afterwards.
I'll look into and fix this. In the meanwhile you should be able to bypass this by disabling MBEDTLS_HARDWARE_GCM if this is issue is a blocker for you.
- Sat Jul 31, 2021 12:47 am
- Forum: ESP-IDF
- Topic: UART ROM download mode when using Flash Encryption
- Replies: 1
- Views: 4536
Re: UART ROM download mode when using Flash Encryption
Hi,
With secure mode you would still be able to encrypt your binary on the host, flash it and boot successfully. This is of course only possible if you already know the key burned to the ESP32.
If you don't have any specific reason to keep secure mode on we still recommend disabling the download ...
With secure mode you would still be able to encrypt your binary on the host, flash it and boot successfully. This is of course only possible if you already know the key burned to the ESP32.
If you don't have any specific reason to keep secure mode on we still recommend disabling the download ...