Hello,
I'm working on an application where high-speed access to a framebuffer is critical, which resides in PSRAM. The framebuffer is processed and the result is stored in a queue, from which data is consumed by the LCD peripheral.
Afaik, the ESP32 S3 PSRAM should in the capable of reading at 80 ...
Search found 7 matches
- Fri Oct 07, 2022 7:10 pm
- Forum: ESP-IDF
- Topic: Settings for best PSRAM Speed with ESP32 S3
- Replies: 0
- Views: 2457
- Tue Feb 02, 2021 10:18 am
- Forum: Hardware
- Topic: PSRAM read-only performance
- Replies: 9
- Views: 8391
Re: PSRAM read-only performance
All right, I'll try that. Thank you for your help!
- Mon Feb 01, 2021 1:58 pm
- Forum: Hardware
- Topic: PSRAM read-only performance
- Replies: 9
- Views: 8391
Re: PSRAM read-only performance
Hi, ESP_Sprite,
thanks for the informative answer. That's good to know. I need the second core for computation unfortunately, so switching to the S2 wouldn't help much. But at least I know I'm not leaving that performance on the table because of stupidity.
Another question if you don't mind: Do you ...
thanks for the informative answer. That's good to know. I need the second core for computation unfortunately, so switching to the S2 wouldn't help much. But at least I know I'm not leaving that performance on the table because of stupidity.
Another question if you don't mind: Do you ...
- Sat Jan 30, 2021 4:51 pm
- Forum: Hardware
- Topic: PSRAM read-only performance
- Replies: 9
- Views: 8391
Re: PSRAM read-only performance
Hi WiFive,
Yes, the Workaround is disabled in menuconfig and the minimum chip revision is set to 3.
The serial debug output on satrtup seems reasonable:
I (32) boot: chip revision: 3
I (36) qio_mode: Enabling default flash chip QIO
I (41) boot.esp32: SPI Speed : 80MHz
I (46) boot.esp32: SPI Mode ...
Yes, the Workaround is disabled in menuconfig and the minimum chip revision is set to 3.
The serial debug output on satrtup seems reasonable:
I (32) boot: chip revision: 3
I (36) qio_mode: Enabling default flash chip QIO
I (41) boot.esp32: SPI Speed : 80MHz
I (46) boot.esp32: SPI Mode ...
- Sat Jan 30, 2021 1:04 pm
- Forum: Hardware
- Topic: PSRAM read-only performance
- Replies: 9
- Views: 8391
Re: PSRAM read-only performance
Interestingly, when switching the above code to use memcpy() instead of reading *(test++) in a loop, i get up to 25.7 MB/s. So I can go above 20MB/s, but cannot quite reach 40. I already tried to reduce the freeRTOS tick rate, etc. to prevent context switches from interfering, but that doesn't ...
- Mon Jan 25, 2021 4:57 pm
- Forum: Hardware
- Topic: PSRAM read-only performance
- Replies: 9
- Views: 8391
Re: PSRAM read-only performance
Hi, sorry to revive this, but I'm still struggling.
The following code:
double GetTime() { return (double)esp_timer_get_time() / 1000000; }
int IRAM_ATTR RamTest()
{
int rs[] = { 1,2,4,8,16,32,64,128,256,512,1024,2048,3600 };
printf("Ram Speed Test!\n\n");
uint32_t xx = 0;
for (int a = 0; a ...
The following code:
double GetTime() { return (double)esp_timer_get_time() / 1000000; }
int IRAM_ATTR RamTest()
{
int rs[] = { 1,2,4,8,16,32,64,128,256,512,1024,2048,3600 };
printf("Ram Speed Test!\n\n");
uint32_t xx = 0;
for (int a = 0; a ...
- Sun Jun 14, 2020 11:50 am
- Forum: Hardware
- Topic: PSRAM read-only performance
- Replies: 9
- Views: 8391
PSRAM read-only performance
Hello,
Finding this forum very helpful as a silent reader, I now hope to get my own question answered as well :)
I'm working on a E-Ink driver board based on the ESP32 (https://hackaday.io/project/168193-epdiy-976-e-paper-controller). Those displays are driven by scanning an active matrix and ...
Finding this forum very helpful as a silent reader, I now hope to get my own question answered as well :)
I'm working on a E-Ink driver board based on the ESP32 (https://hackaday.io/project/168193-epdiy-976-e-paper-controller). Those displays are driven by scanning an active matrix and ...