Search found 11 matches

by wjxway
Wed Aug 12, 2020 8:03 am
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

Maybe your ISR is being mugged by another ISR? Working out of IRAM/cache will also hurt. I have seen similar with big 2mS hits on I2C transactions to the extant that someone starting producing I2C corruptions. My guess was that Ethernet caused the ISR/bus block but not sure if device or ESP caused ...
by wjxway
Wed Aug 12, 2020 7:57 am
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

Maybe your ISR is being mugged by another ISR? Working out of IRAM/cache will also hurt. I have seen similar with big 2mS hits on I2C transactions to the extant that someone starting producing I2C corruptions. My guess was that Ethernet caused the ISR/bus block but not sure if device or ESP caused ...
by wjxway
Tue Aug 11, 2020 4:30 pm
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

@ESP_Sprite Thanks for your reply, now the polarity is correct and ready to go. There's just one issue left regarding timing. I'm transferring nine 16bits data at a time, and I would like it to happen immediately after I execute the code (or after a fixed, short time delay). If no data is feed in, t...
by wjxway
Mon Aug 10, 2020 3:50 pm
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

Whooo, I have managed to get it working at BCK@40MHz, that is 1.25M@16bits transfers/sec! That is when I'm using a DAC with SPI interface, if someone is using a DAC with I2S interface, the number could ramp up to 2.5M@16bits transfers/sec! The trick is just as described in https://esp32.com/viewtopi...
by wjxway
Mon Aug 10, 2020 2:55 pm
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

You may want to set USE_APLL to 1 as well as use a larger dma_buf_len... could be that the issue is that the ISR gets called too often or that the I2S driver has issues generating the frequencies you need. Hi, my oscilloscope has arrived and I managed to get I2S interface running. Well, the good ne...
by wjxway
Sun Aug 09, 2020 6:14 pm
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

Hey, Not sure about Ardunio but DMA under IDF adds a 20uS+ (ish) hit. A key point is the construction of the SPI transaction. IDF you can create this 'command' on the fly or you can create a command and then reuse. The performance difference is very important as frequency increaces... I am not sure...
by wjxway
Wed Aug 05, 2020 5:19 pm
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

You may want to set USE_APLL to 1 as well as use a larger dma_buf_len... could be that the issue is that the ISR gets called too often or that the I2S driver has issues generating the frequencies you need. Changing .USE_APLL to 1 couldn't improve performance. Changing .dma_buf_len = 2048 or larger ...
by wjxway
Wed Aug 05, 2020 11:30 am
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

Whoops, I initially imagined you wanted to set up an ADC. A DAC may be even easier. Effectively, I2S allows you to set up a continuous SPI-like stream of data, read from a memory buffer without any CPU interference; the only thing the CPU needs to do is to make sure the memory buffer gets 'topped u...
by wjxway
Wed Aug 05, 2020 8:58 am
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

Whoops, I initially imagined you wanted to set up an ADC. A DAC may be even easier. Effectively, I2S allows you to set up a continuous SPI-like stream of data, read from a memory buffer without any CPU interference; the only thing the CPU needs to do is to make sure the memory buffer gets 'topped u...
by wjxway
Wed Aug 05, 2020 7:30 am
Forum: General Discussion
Topic: Reduce time between two consecutive SPI transfers
Replies: 16
Views: 2624

Re: Reduce time between two consecutive SPI transfers

It's a hard problem in general... as you need software to set up the start of each separate 16-bit transaction, there will be a lot of overhead. Only way I can imagine to do it in software would be to abuse the I2S hardware.... theoretically, you can put it into 16-bit mode and use the data output ...

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