For such an XIP kernel and constrained 16MiB device, we can skip u-boot entirely and jump into kernel from OpenSBI directly.
But u-boot may be useful to load a normal kernel from external device if later s31 SoC comes with larger PSRAM.

Isn’t this board for esp32-s31?

Which DMAs support external memory, including descriptor (if applicable) and buffer?

1. AHB & AXI GDMA (supported)
2. LP AHB GDMA (?)
3. DMA2D (supported to psram)
4. SDIO (supported)
5. DWC2 (supported by p4 but ? for s31)
6. EMAC (supported by p4 but ? for s31)

Some hint from the agent skills. But lacks instruction cycles of SIMD instructions and overhead of unaligned access.

Yes, any invalid PIE use will trigger illegal instruction exception. In panic_handler, the task will be pinned to core 1 automatically.

Two HP cores plus one LP core. For HP cores, only HP core 1 with SIMD (xespv).

For bus system:
1. Does any bus master support hardware coherency?
2. Which memory supports AMO transactions, and from which core?

For HP cpu cluster:
1. Does CLINT of each HP core have their own builtin MTIME system timer?
2. Does the SIMD unit on HP core 1 support the same instructions as P4 (v3 ...

同问，RGB/CAM引脚分配在GPIO矩阵或是IO Mux时钟频率上限分别是多少？

ESP32-S31NRV32 with 32 MiB of PSRAM is/will be available as chip form, but the -R32V variants are missing from the preliminary ESP32-S31-WROOM-3 datasheet. Will it appear in a foreseeable timeframe?

BTW, can’t wait for the fully equipped ESP32-S31NRV64

See the fresh datasheet , it's sv32 MMU, so we can expect for a full Linux on this chip.
The old "MMU" on S3 and other chips are still some sort of programmable flash / psram mapper, not a virtual memory system from the aspect of CPU. It still presents on esp32-s31 for interfacing with PSRAM and ...