Some more information (brief description of (many of?) the instructions) here:
https://github.com/espressif/esp-dl/blo ... uctions.md

On the S3, and AFAIK on the P4 too, there are no unaligned memory accesses via the SIMD. Every access is always aligned, see the S3's TRM for example.

Hm, ok.
The C3's TRM in fact does not seem to indicate any alignment restrictions, neither for RAM nor for peripheral registers. From the CPU's perspective, everything is accessed via the same data bus.
Could try out this for peripheral access:

#include <stdint.h>
#include "soc/systimer_struct.h ...

https://github.com/espressif/esp-idf/issues/18418

Quick hack would be to insert a "\" in https://github.com/espressif/esp-idf/blob/bc6616854ea6303c538b97de66b7aaf290f8f1b0/components/esp_rom/gen_gdbinit.py#L52, or

rom_file = os.path.join(rom_elfs_dir, f'{target}_rev{k["rev"]}_rom.elf')
r.append ...

Can you use C++?

You should be able to just initialize TX&RX on the same pin, then set that pin to OD via gpio_od_enable().

I use a fixed-size blob of 8192 bytes (4096*2) stored under the key "blob" in namespace "EEPROM". Is this a valid and recommended approach?


No.
https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/storage/nvs_flash.html#keys-and-values:

NVS works best for storing many ...

Can these exceptions actually occur on ESP32 RISC-V devices?

I imagine they would occur when you attempt a misaligned access on peripheral registers, or RTC RAM.

Yes.

3. How do you typically diagnose problems that are difficult to reproduce consistently?

Capture the log output around the time of the unexpected reboot, ideally multiple times. Check if you can determine the issue from that. If not, post the logs here.

Stable power supply is of course essential ...