In your code, you're initializing two channels with the same i2s_std_config_t; i.e. you tell two channels to use the same pins (like you would do for one full-duplex channel). This might be causing issues.

How about https://github.com/hideakitai/ESP32SPISlave ?

I don't think that I'm an AI. - But maybe I am and only programmed to think otherwise? Will go and try some CAPTCHAs to find out.


You do not want dropped frames, do you ?

Rather not. But I also don't get any frames dropped. Why would I?


I am saying that there is value to have a callback that ...

cache coherency

Frame buffer in PSRAM? Then yes, that might be an issue.

1. On re-randomizing the key. I understand eFuses are one-time and can't be rewritten, which is what breaks the clean version of this.

Yes, every eFuse (bit) can either stay "0", or be written to "1" once; you could destroy a key by setting all its bits to "1".


is destroying/invalidating a ...

The TRM says

RISC-V instruction set architecture (ISA) comprising base integer (I), multiplication/division (M), atomic (A) and compressed (C) standard extensions

[...]

RISC-V RV32IMAC ISA

Not sure if keys stored in the eFuses can be wiped/"overwritten", but if so, you may be able to come up with a scheme where you use a read-protected eFuse key for encryption/decryption of (only) sensitive data. Then you only allow (OTA) firmware flashing after having destroyed the key. That'd ...

- atomics: under the hood they are stdatomics

I think you got that one backwards. "__atomic_store_n()", for example, is (likely) "under gcc's hood" of the standard C "atomic_store_explicit()".

- looking more into this.

The problem is, if, for whatever (scheduling/priority) reason, the ...

When dealing with microcontrollers, you always have the electronics/hardware and the software side. You won't get anywhere without enough understanding of electronics for your purpose. The bar for entry is pretty low; you need to know what voltage is and current, because if you don't you're bound to ...

I can't seem to find a good answer as to if/how "continuous" transfer is supported in slave mode.

An SPI transaction ends when either /CS is pulled high or when the corresponding RX buffer is full.
My suggestion is to test how this is handled by enqueuing two (or more) transactions and checking ...