I know I'm necroing a thread, but, because Google refuses to index the real project when you search for this and you get this thread instead, I wanted to post the link to this tool:

https://github.com/cpq/esputil

This is a C version of esptool.py, that has no dependencies and just works on OSX ...

This is not an uncommon error state in a single-master system. If the host is reset at a bad time, i.e. when a slave was sending a 0 bit on the SDA.


int gpio_no = 41;
// Shake any device off the bus.
int i;
for( i = 0; i < 16; i++ )
{
gpio_matrix_out( gpio_no, 256, 1, 0 );
GPIO.out1_w1tc ...

When using I2C, sometimes downstream devices are in the middle of a transaction when the ESP resets. This causes them to hold the SDA line low, while the SCL line is high, which apparently confuses the ESP I2C stack?

Is there a proper way to "flush" I2C transactions by toggling the clock line ...

I could, but it would be very difficult to make this work without the APLL, which as far as I understand has been dropped from the S3 :-/.

It may be worth fabbing up an S3 board to give it a shot to see if I can make it work with a clunkier clock.

I will just try to duplex it. At least as of ...

I have a situation where I need to output a WS clock that is over a cadence of 512 bits not 32- or 64- per flip. Is there some mechanism that can be used to provide a WS clock that is of a wider bit width?

One idea I had was to use the I2S engine in duplex mode, and shift out the "ideal" WS, but ...

Also, in case anyone else was peaking around here... It looks like the FSM is pretty fast, but I/O with the FSM is even slower than the RISC-V . Looks like ~12 cycles to set or clear any bits. Jumps are ~4 cycles.

I did some tests on this myself. And in general I'm finding it takes 7 to 9 cycles per `sw` instruction depending on instruction alignment, with either a 10MHz clock (if you use the XTAL divider) or a variable clock between about 6MHz and 10.5MHz if you use the RC filter, with the undocumented ...

I know I'm late here, but if anyone else was wondering, you can force this by:


// Maybe we need to consider tweaking these?
chip_usb_set_persist_flags( 0 ); //NOT USBDC_PERSIST_ENA (1<<31)

// We **must** unset this, otherwise we'll end up back in the bootloader.
REG_WRITE(RTC_CNTL_OPTION1 ...

I am having an issue with this again. Now when I include the above code, I get this error:


CMake Error at CMakeLists.txt:20 (add_dependencies):
Cannot add target-level dependencies to non-existent target "flash".

The add_dependencies works for top-level logical targets created by the
add ...

Thank you! This worked wonders.