@thefury I moved from using an Arduino library to using the ESP-IDF I2S library. In what order should I start the master and slave I2S channels? And do I start them before or after connecting the matrix?

Now that I looked at the logic analyzer screenshots it seems that there isn't a sample delay but just a slight phase delay. The data output still happens before the BCLK rising edge.

Thank you for your post.

The data doesn't start at the same time, is the only issue.

What's the delay? One sample?

I want to have two synchronized (bit and frame) I2S output streams on an ESP32. I've read that this can be done by making one the master and the other the slave, and connecting the BCLK and WS pins externally. Of course it would be ideal to avoid using two pairs of pins and instead reuse the pins ...

I'm looking to develop a Bluetooth speaker using the TAS6424 class-D amplifier IC. This chip takes either TDM or I2S with two SDIN pins. For compatibility, it is imperative that the device supports Bluetooth Classic.

The problem is that all ESP32 SoCs that support the TDM mode , do not support ...

I'm looking to build a True Wireless Stereo speaker pair using ESP32 or ESP32-S3 (if necessary).

I've done a bit of research and I found that there's generally two kinds of configuration that TWS peripherals employ. The first configuration, which I'll refer to as "daisy chained" is where only one ...