Very minor thing: Currently, when I click preview, it reloads the page. It would be nice if preview didn't require a full page refresh.

S31 could be a good fit for a few different things. It looks like the eval boards have castellated modules, any news or plan about them? Any chance for wide Flash & DRAM across the lineup?

SIMD Unaligned access?

Will ESP32-S31 GCC support autovectorization?

Will ESP32-S31 GCC support https://gcc.gnu.org/onlinedocs/gcc/Vect ... sions.html ?

Is the SIMD instruction set more ESP32-S3 or RISCV SIMD?

How will that be managed with the scheduler? If you use SIMD, will it pin to core1?

What's new comparing ESP32-S3 to ESP32-S31 MMU-wise?

OpenOCD multi-histogram encoder has been merged to mainline in time for the next OpenOCD release

It seems the older RISCV cores do not: https://github.com/espressif/vscode-esp ... 3236319637

Hopefully it might be enabled for future RISCV cores.

Thanks Microcontroller! That's really helpful.

> (On a note, some of the SIMD instructions (VMUL...) use the value from the Xtensa core "shift amount register" ("special register SAR") which is also used by the compiler, so may be "clobbered" at any time "outside" of assembly code.)

I'll be sure ...

Is there a recommended calling convention for stacking the SIMD/PIE registers across function and subroutine calls?

Which registers are preserved by the RTOS?

Are there registers I should preserve before using?