Search found 205 matches

by urbanze
Wed Oct 17, 2018 1:28 am
Forum: General Discussion
Topic: ULP ADC conflit
Replies: 0
Views: 26

ULP ADC conflit

I using ULP to do an interrupt in main core when adc value goes to below threshold value and after this, main core takes control of adc and do a better filter. However, when main core stop usage of adc, ulp has "bricked" and dont work any more UNTIL ulp halt and main core start ulp again. ...
by urbanze
Sun Oct 14, 2018 5:32 pm
Forum: General Discussion
Topic: Precise voltage drop in output
Replies: 1
Views: 80

Precise voltage drop in output

In the datasheet it is said only about the maximum and minimum voltage when applied X current, however, I need something more precise to apply in the switching of a load cell. Is there any formula for calculating the voltage drop with X current at an output? A graphic on this in the datasheet, detai...
by urbanze
Mon Oct 08, 2018 5:47 pm
Forum: ESP32 IDF
Topic: task watchdog user handler
Replies: 0
Views: 44

task watchdog user handler

I trying to handle tsk wdt user function with void esp_task_wdt_isr_user_handler(void) { ets_printf("\n\n\nABCDEFG\n\n\n"); ets_delay_us(10000); } but doesnt work, however, I write this code in original function in task_wdt.c and work perfecly. Why my custom function in main.c doesnt worki...
by urbanze
Sun Oct 07, 2018 4:30 pm
Forum: General Discussion
Topic: vTaskDelay issue bit me
Replies: 9
Views: 261

Re: vTaskDelay issue bit me

I'm using v3.1 release. I put a loop in the beginning of my program calling vTaskDelay(100) and printing the time. I am getting the correct delay of 1000msec (1 sec). t:1 msec t:1000 msec t:2000 msec t:3000 msec t:4000 msec t:5000 msec t:6000 msec t:7000 msec t:8000 msec t:9000 msec Time is straigh...
by urbanze
Fri Oct 05, 2018 5:15 pm
Forum: General Discussion
Topic: vTaskDelay issue bit me
Replies: 9
Views: 261

Re: vTaskDelay issue bit me

Delay with RTOS methods is limited to FreeRTOS frequency, if freq. is 100Hz, minimum delay is 10ms and if 1000Hz (maximum freq), minimum delay is 1ms.

Check in menuconfig if rtos frequency is >=500Hz to get 2ms delay
by urbanze
Fri Oct 05, 2018 3:56 pm
Forum: General Discussion
Topic: Newbie question about BOD|WDT
Replies: 1
Views: 93

Newbie question about BOD|WDT

By default, in many MCUs, watchdog's and BOD's are disabled by default and are required to activate them in the software. If this is true, this must be done as soon as possible after powering the MCU. However, what happens if the MCU crashes because of power or any random reason BEFORE the bootloade...
by urbanze
Wed Oct 03, 2018 4:45 pm
Forum: General Discussion
Topic: What would you like to see in The Next Chip?
Replies: 251
Views: 39747

Re: What would you like to see in The Next Chip?

1. More detailed documentation. 2. More RAM (as has been quoted hundreds of times). 3. Low power is an interesting question that could also be improved. However, one of the problems when in sleep on set of batteries, is the converter (often buck), consumes several times more than the own esp. The im...
by urbanze
Thu Sep 27, 2018 6:46 pm
Forum: ESP32 Arduino
Topic: Can I write to an INPUT GPIO pin?
Replies: 7
Views: 296

Re: Can I write to an INPUT GPIO pin?

In some boards, write in an input will active pull up or pull down.
by urbanze
Mon Sep 24, 2018 5:33 pm
Forum: General Discussion
Topic: Deep sleep edge wake-up
Replies: 4
Views: 155

Re: Deep sleep edge wake-up

Could you please expand the "does not look very good"? As far as I know, edge wake up was not a requirement for the part of hardware responsible for deep/light sleep wake up. If signal change between code invert logic or between GPIO_READ (to check signal level) and invert logic wakeup, t...
by urbanze
Mon Sep 24, 2018 4:56 pm
Forum: General Discussion
Topic: Deep sleep edge wake-up
Replies: 4
Views: 155

Re: Deep sleep edge wake-up

There is no hardware support for edge triggered wake up, however once wake up happens, you can invert GPIO wake up trigger and enter sleep again. Alternatively, you can implement edge trigger in a ULP program. Yes, I did logic inversion but it does not look very good... I think about ulp early and ...

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