The suggested workaround only reduced the ISR to being called twice per interrupt instead of the 7 times I was seeing: uint32_t rtc_intr = READ_PERI_REG(RTC_CNTL_INT_ST_REG); // disable and clear interrupt CLEAR_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, RTC_CNTL_ULP_CP_INT_ENA); WRITE_PERI_REG(RTC_CNTL_IN...

I'm working on a project that needs to monitor a GPIO to see if it goes high then back to low and deep-sleep when no activity. So I have started experimenting with the ULP coprocessor using the pulse counter examples/system/ulp/ example and am getting the RTC interrupt when ulp executes`wake` instru...

Official FreeRTOS doesn't support multiple core processors and so the ESP32 FreeRTOS BSP/port is unique that it does support both processor cores. And in the documentation they have mentioned that some FreeRTOS functions are flagged as untested that haven't been fully vetted to be compatible with th...