Search found 9 matches
- Thu Apr 23, 2026 1:32 pm
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
Re: ESP32-S3 SPI slave clock only stable on GPIO43
It was a hardware defect. With a new board with 500 ohm resistor in series it works perfectly. Thanks a lot for thinking along @MicroController!
- Sun Apr 05, 2026 12:40 pm
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
Re: ESP32-S3 SPI slave clock only stable on GPIO43
Thanks, I've tried that by putting a 1.2K resistor in parallel to the 10k on the mosfet (3v3 side). This compares the 10k+1.2K situation (white line) to the stock of just 10k (blue). I do see that the curve starts to bend at around 2.5V, which is also around 0.75 * VDD, the high-level input voltage ...
- Sat Apr 04, 2026 3:24 pm
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
Re: ESP32-S3 SPI slave clock only stable on GPIO43
I just tested with the ESP32-S3-DevKitC-1 using my signal generator and it works fine on that one. I also found that the ESP32-S3-MINI-1 has a resistor on the U0TXD line internally, so I guess that might filter out some glitches and that's why it works?
I also looked at lowering the clock of the ...
I also looked at lowering the clock of the ...
- Sun Mar 29, 2026 6:03 pm
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
Re: ESP32-S3 SPI slave clock only stable on GPIO43
Yes, I have the correct SPI mode selected (3, CPOL=1, CPHA=1).
- Thu Mar 26, 2026 7:53 pm
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
Re: ESP32-S3 SPI slave clock only stable on GPIO43
I tested, the interrupts are not the problem. When I provide my own CS with the generator it still has the same issues with the SPI peripheral counting one clock too many, sometimes.
Reducing the interrupts is a nice improvement indeed. It was on my list but low prio, since it does not seem to hurt ...
Reducing the interrupts is a nice improvement indeed. It was on my list but low prio, since it does not seem to hurt ...
- Sun Mar 22, 2026 6:01 pm
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
Re: ESP32-S3 SPI slave clock only stable on GPIO43
I've created two test projects to demonstrate the issue. One of them generates the signal and the other one reads it:
* https://github.com/hberntsen/mhi-ac-spi ... -generator
* https://github.com/hberntsen/mhi-ac-spi-signal-tester
* https://github.com/hberntsen/mhi-ac-spi ... -generator
* https://github.com/hberntsen/mhi-ac-spi-signal-tester
- Sun Mar 22, 2026 8:58 am
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
Re: ESP32-S3 SPI slave clock only stable on GPIO43
MicroController I've put an interrupt on the CLK signal that resets a timer. When the timer reaches 1 millisecond that means the clock is idle and I toggle the CS. I originally did that by physically connecting two GPIOs together, that is now done internally through the GPIO matrix (using the ...
- Fri Mar 20, 2026 6:15 pm
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
Re: ESP32-S3 SPI slave clock only stable on GPIO43
What genuis decided it'd be a good idea to connect the same USB data lines to two USB connectors plus two other connectors, then also put pull-up resistors on them, label them as "TX" and "RX", and wire them together to two IO pins each?! That board is a mess!
As the webshop says:
A USB-A ...
As the webshop says:
A USB-A ...
- Thu Mar 19, 2026 9:20 pm
- Forum: ESP-IDF
- Topic: ESP32-S3 SPI slave clock only stable on GPIO43
- Replies: 16
- Views: 505
ESP32-S3 SPI slave clock only stable on GPIO43
Hi,
I'm running into a problem: on the ESP32-S3, using the SPI slave often generates transactions with too many bits received. In a rare case I get less bits.
* It is a 30KHz clock with 160 or 264 bits of data (configurable), sending 20 transactions per second.
* The code is over here: https ...
I'm running into a problem: on the ESP32-S3, using the SPI slave often generates transactions with too many bits received. In a rare case I get less bits.
* It is a 30KHz clock with 160 or 264 bits of data (configurable), sending 20 transactions per second.
* The code is over here: https ...