Hi Rudy,

Both components were intentionally left unpopulated to accommodate any potential future requirements:
Top left: corresponds to C10 (marked as NC in the datasheet)
Middle right: corresponds to R11 (marked as NC in the datasheet)

You may find the details here: https://documentation ...

We expect them be available around mid~end June, stay tuned!

Regarding bus system:
1. ESP32-S31 dual RISC-V cores share the same D-cache, so there is no separate inter-core D-cache coherency issue between the CPUs.
However, there is no hardware coherency protocol support for:
- I-cache / D-cache coherency
- CPU and DMA coherency
2. When DMA and other non-cpu ...

Thanks for the enthusiasm! The -R32V variant information will be reflected in our documentation as things progress on our end. Stay tuned to our official channels for updates!