Thanks for your reply, i have tested the RTC RAM with
void __attribute__((noreturn)) call_start_cpu0(void)
{
// SOC_RTC_DRAM_LOW = 0x50000000
volatile uint8_t *rtc = (volatile uint8_t *)SOC_RTC_DRAM_LOW;
uint32_t val;
rtc[0]=0x01; rtc[1]=0x02; rtc[2]=0x03; rtc[3]=0x04;
asm volatile("lw %0 ...
Search found 2 matches
- Tue Jun 09, 2026 7:31 am
- Forum: General Discussion
- Topic: ESP32 RISC-V implementation Load/Store misalignment behaviour
- Replies: 3
- Views: 132
- Wed Jun 03, 2026 3:35 pm
- Forum: General Discussion
- Topic: ESP32 RISC-V implementation Load/Store misalignment behaviour
- Replies: 3
- Views: 132
ESP32 RISC-V implementation Load/Store misalignment behaviour
Hi,
I would like to get a clear understanding of how ESP32 RISC-V implementations handle misaligned load/store memory accesses.
The RISC-V specification states that the behavior of misaligned accesses is implementation-specific (The RISC-V Instruction Set Manual, Volume I: Unprivileged ...
I would like to get a clear understanding of how ESP32 RISC-V implementations handle misaligned load/store memory accesses.
The RISC-V specification states that the behavior of misaligned accesses is implementation-specific (The RISC-V Instruction Set Manual, Volume I: Unprivileged ...