Thanks. Well I use whole word only with needed bits so masking is not necessary.
Actually XOR operation might not be needed and data will be precalculated ready to write)
I want to use assembler instructions to repeat inline few times for speeding execution.

So operations steps would be:

val => W1TS
val ~= val
val => W1TC

How that would look in asm ?

May I ask - why not 2 cores?

Let's say I want to set 12 bits/pins simultaneously with specific values 0/1 to gpio output register but I do not want to change other bits - must be done with one 32bit word write and possibly one write instruction. Do I have to disable/enable bits with mask first? I don't want to change settings o...

I have a feeling there will be also same chip with 2 cores and maybe BT
LCD and camera support looks great - I hope it is not through I2S only.
Also if all that extra 128MB spiram is fully addressable in continuous blocks this is a huge hardware improvement.

Is it possible to connect two separate Esp32 modules in a way that they could share and access same memory?
If so - how? And would it be easy to implement in SDK?

I wonder if the display process can be done only by CPU. I tried to drive it without I2S and it worked however my panel seems to have very strange behavior. There is something related to OE pin - must be triggered after every row or I am doing something wrong. They specify OE as active low so it act...

Hey CalinB!
Thanks for your input! I will definitely look at those tools because VSC needs some extension that would make things easier for esp development. Intellisense should be more filtered just to the project objects.
Thanks again!

Updated links to newest version (as of right now)

I managed to modify the blink code and compile with CMake and latest ESP-IDF )
It was necessary to upgrade Idf to the latest version - newest toolchain comes with full ULP support and even nice examples which is very nice. I used just VSC and CMake (Win10) - no need for PlatformIO