Search found 40 matches

by chrismerck
Thu Jun 06, 2019 1:42 pm
Forum: ESP32 IDF
Topic: [SOLVED] Boot Different Partition from Application
Replies: 7
Views: 1702

Re: [SOLVED] Boot Different Partition from Application

Hi Jerome, So I'm late, but better late than never? Those two defines are arbitrary values you decided to use ? Yes, they are essentially arbitrary. Values to avoid are 0x0, 0xFFFFFFFF, 0xCCCCCCCC, and 0x55555555, since those may be default conditions. The 1/2BADBABE is chosen because it is immediat...
by chrismerck
Wed May 01, 2019 3:26 pm
Forum: General Discussion
Topic: 40 kHz GPIO interrupt
Replies: 6
Views: 641

Re: 40 kHz GPIO interrupt

@WiFive: THANK YOU! HelWeb's work is just what we needed to see. It's amazing how well you know the ESP community. -- Will update when we have a full solution to our issue, and describe what we learned.
by chrismerck
Wed May 01, 2019 3:23 pm
Forum: General Discussion
Topic: RTOS running on one core only
Replies: 24
Views: 2136

Re: RTOS running on one core only

@HelWeb:

Just want to thank you for posting your technique for running without RTOS on Core1. This is extremely useful information to my team here to work around interrupt performance issues on Core0. We will let you know our results!

Merci vielmal!
by chrismerck
Wed May 01, 2019 12:21 pm
Forum: General Discussion
Topic: 40 kHz GPIO interrupt
Replies: 6
Views: 641

Re: 40 kHz GPIO interrupt

Is there any chance you could e.g. use the I2S or SPI peripheral to do this? We have tried, but no luck so far. I2S seems to require a higher external clock speed. External protocol clock is 40kHz. We need to continuously stream data from the GPIO into the application, and we don't see how to do th...
by chrismerck
Wed Apr 24, 2019 11:15 pm
Forum: ESP32 IDF
Topic: Google WiFi Compatibility
Replies: 0
Views: 191

Google WiFi Compatibility

Is there a known issue with ESP32 and Google WiFi compatibility? We are getting reports from the field, and are closing in on a reproduction of the issue.

Using IDF v3.1.2 at this time.

(Will update with more details in ~48 hours.)
by chrismerck
Wed Apr 24, 2019 11:08 pm
Forum: General Discussion
Topic: 40 kHz GPIO interrupt
Replies: 6
Views: 641

Re: 40 kHz GPIO interrupt

Thanks WiFive. Indeed we were considering ULP, but would prefer to use the XTENSA cores.

Update: We are exploring running FreeRTOS only on core 0 and putting our ISR on core 1.
by chrismerck
Fri Apr 19, 2019 11:28 am
Forum: General Discussion
Topic: 40 kHz GPIO interrupt
Replies: 6
Views: 641

40 kHz GPIO interrupt

How can I get a GPIO interrupt to pre-empt WiFi and RMT operations? I need high priority I have tried using ESP_INTR_FLAG_LEVELn, but I get exceptions for even LEVEL1. Only the default flags, or IRAM flag work. --- DETAIL: We've got a 40 kHz clock running to an ESP32 GPIO pin, with an interrupt ena...
by chrismerck
Mon Mar 04, 2019 8:52 pm
Forum: Hardware
Topic: ESP32 5GHz
Replies: 16
Views: 8969

Re: ESP32 5GHz

Thanks Sprite. Hopefully we do not need to switch platforms, but smart-home customers are demanding 5GHz.
by chrismerck
Wed Feb 27, 2019 7:39 pm
Forum: Hardware
Topic: [SOLVED] RTC Memory Corruption after Deep Sleep
Replies: 2
Views: 539

Re: RTC Memory Corruption after Deep Sleep

:facepalm: Thanks Igrr. Your quick response saved us a lot of headache!

Increasing the deep sleep time made the situation worse (as expected), and adding the following before deep_sleep totally fixed the issue:

Code: Select all

esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_SLOW_MEM, ESP_PD_OPTION_ON);
by chrismerck
Mon Feb 25, 2019 9:46 pm
Forum: Hardware
Topic: [SOLVED] RTC Memory Corruption after Deep Sleep
Replies: 2
Views: 539

[SOLVED] RTC Memory Corruption after Deep Sleep

We've observed a strange behavior on 2 units of ESP32 dev kits where the RTC memory becomes corrupted after deep sleep. We are still working to isolate the problem, and hope to provide an example project that shows the issue, but for now I just want to share what we are seeing: /* application writes...

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