Hello

With the ESP32-S3-WROOM-2-N32R8V marked EoL and the ESP32-S3-WROOM-2-N32R16V starting production I wonder...
Will the new 16MB version be 100% backwards compatible to the 8MB one or will there be any code changes necessary as long as one does not utilize the upper half of the bigger memory ...

I wasn't very satisfied with the original "flash download tool" offered by Espressif so I've decided to write my own based on Espressifs esp-serial-flasher library. The result is a little Qt CLI/GUI tool called "QtESPFlasher" and is available here: https://github.com/higaski/QtESPFlasher

Thank you very much for this in-depth explanation.

Your reply could easily go into the docs... Currently you'd have to piece that kind of information together from 3x different sources (esptool, SPI and bootloader).

Note that while the application app image also has these configuration bytes, I'm ...

Hello

Can someone explain a few things to me about the SPI settings? I'm trying to understand how the "Serial flasher config" settings relate to idf.py, the *-flash_args files generated during a build and the SPI peripheral settings ultimately used in the chip.

So, for starters, do the "Serial ...

I have no problems including <bitset> with

A websocket is a bidirectional communication. As long as the socket is open you can send data at any time. The example you've linked even does that by using the function.

Thank you, you've been on the right track.
This was indeed an ESP-IDF bug, quote:

The interrupt allocator internally allocated some buffer from the PSRAM, so causing the crash.

sh_vec->isr(sh_vec->arg); // Backtrace points here

This seems to indicate one of two things:
a) the shared_vector_desc_t @ *sh_vec is located in flash/PSRAM, or
b) the ISR it tries to call is in flash and not IRAM.
Maybe double-check the IRAM configuration of all relevant ISRs; and make sure ...

My question is how we might do this with a local file instead?

In particular, if we don't have WIFI working, it seems a web page served by the ESP using the AP mode, could provide the OTA binary from the users computer and an OTA update could be performed. I don't know how the write stream would ...

How can I interpret this?

To me it looks as though the issue could be that during an SPI flash read an interrupt is triggered and the ISR tries to access cached memory.
What version of the IDF are you using? Specifically, what does this version do in line 446 of esp-idf/components/esp_hw ...