Search found 67 matches

by jsam589
Tue May 26, 2020 12:45 pm
Forum: ESP32 IDF
Topic: Task not launching even with plenty of free internal RAM
Replies: 4
Views: 428

Re: Task not launching even with plenty of free internal RAM

Memory fragmentation could explain my issue, but I thought that the call to

heap_caps_get_largest_free_block(MALLOC_CAP_INTERNAL);

tells me the largest contiguous block that can be obtained (9808) and this should be more than adequate.
by jsam589
Mon May 25, 2020 11:50 pm
Forum: ESP32 IDF
Topic: Task not launching even with plenty of free internal RAM
Replies: 4
Views: 428

Task not launching even with plenty of free internal RAM

I am running low on internal RAM for task stack usage, but I have around 10000 bytes available and want to launch a task with a stack of only 3072 bytes. However, the task creation fails and returns -1 (memory). Any idea why this would happen? These are the results on which I base my numbers. At the...
by jsam589
Sun May 17, 2020 11:35 pm
Forum: ESP32 IDF
Topic: Is compression during flash programming just for the transfer?
Replies: 1
Views: 167

Is compression during flash programming just for the transfer?

When programming my device, I have a 2 MB partition allocated. Is the programming message below saying that 1495920 bytes of flash were consumed? And the data was compressed to 908774 only for transfer? Or is it stored compressed? This matters because I want to properly size my partition and leave r...
by jsam589
Mon May 11, 2020 7:50 pm
Forum: ESP32 IDF
Topic: How can I increase wifi task stack size?
Replies: 0
Views: 208

How can I increase wifi task stack size?

Task "wifi" is overflowing its stack sometimes and when I just checked the high water mark, it was 48 bytes (i.e. very close to stack overflow!). I am using v4.0 stable IDF. I don't see a CONFIG parameter to increase the stack for wifi. Although many other system tasks have adjustable sizes. Am I mi...
by jsam589
Mon May 11, 2020 6:44 pm
Forum: ESP32 IDF
Topic: BLE CCCD limit and need to erase?
Replies: 0
Views: 182

BLE CCCD limit and need to erase?

I adapted the bleprph example into my application. After several rounds of testing, it seems to hit a limit related to NVS and CCCD storage. If I try to pair (same phone always) after it reports having 8 CCCD already, the BLE task seems to hang and I eventually get a Task WDT reset. After this probl...
by jsam589
Thu Apr 16, 2020 1:01 am
Forum: ESP32 IDF
Topic: Documentation discrepancy RTC fast clock
Replies: 5
Views: 1051

Re: Documentation discrepancy RTC fast clock

Thanks for the responses. I think things make sense now and since I do use the IDF, I can count on 8M as fast clock source.
by jsam589
Wed Apr 15, 2020 9:27 pm
Forum: ESP32 IDF
Topic: Documentation discrepancy RTC fast clock
Replies: 5
Views: 1051

Re: Documentation discrepancy RTC fast clock

I thought I was looking at the latest, v4.1 from Nov 2019.
https://www.espressif.com/sites/default ... ual_en.pdf
In section 30.3.7 Low-Power Clocks
???
by jsam589
Wed Apr 15, 2020 7:59 pm
Forum: ESP32 IDF
Topic: Documentation discrepancy RTC fast clock
Replies: 5
Views: 1051

Documentation discrepancy RTC fast clock

In esp32 tech reference manual, fig 166 RTC Low-Power Clocks, it shows that the default clock source for RTC fast clock is CK_40M_DIG* (div 4). However, everything else I read, and try, indicates that the ~8.5 MHz internal osc is the source. For example, in esp_clk_init(), it has hardcoded rtc_clk_f...
by jsam589
Sun Apr 12, 2020 9:34 pm
Forum: ESP32 IDF
Topic: Is there a ULP workaround to change sleep time?
Replies: 5
Views: 948

Re: Is there a ULP workaround to change sleep time?

@boarchuz, you mention forcing RTC peripherals on. I notice in the online docs that the RTC PERIPH domain supposedly includes ULP. esp_sleep_pd_domain_t Power domains which can be powered down in sleep mode. ESP_PD_DOMAIN_RTC_PERIPH - RTC IO, sensors and ULP co-processor. Did you first try changing ...
by jsam589
Sun Apr 12, 2020 9:25 pm
Forum: ESP32 IDF
Topic: Are ULP restrictions gone in silicon V3?
Replies: 4
Views: 1024

Re: Are ULP restrictions gone in silicon V3?

Thanks for responding! All my sensor GPIOs are among the RTC pins. I may try assigning ext1 wakeup for ESP32 and not ext0. The online docs don't mention caveats if using ext1. But I wonder if it draws extra power to support the ext1 mode? I will eventually measure the power draw when all three wake ...

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