Makes sense. So DMA spi operations are possible though?

Nice! No spi DMA?

How does the separate IRAM and SPI cache affect the ability of threads/tasks/ISRs to run on both cores dynamically? Thanks

The ROM may not be finalized at this point and the SDK probably isn't linking to ROM functions for debugging purposes.

Fyi, do not take this as an indication on the amount of memory that will be available in the final SDK and on the final ESP32 chip. Because of the memory map of the ESP31, we only use a specific bit of memory (the shared RAM) as heap. Don't quote me on this, but I estimate the free heap in the ESP3...

Planning on using solder paste and hot air to avoid this problem.

Nice to see they are shipping out. Wonder if they are shipping all at once or in smaller batches.

So ESP31 vs ESP32 Pins 36-45 are different pinout, mostly just rearranged. ESP32 loses Vdigital supply input which is used for digital IO logic levels? Instead is combined with Vpll? Or Vcore? ESP32 gains GPIO23 pin @ pin #42 No labels for RTC_GPIO pins yet? Pins 10 & 11? GPIO #1 is mirrored on two ...

Any sign of BTLE stack in the SDK? Hopefully there will be capability for master, slave, and dual-mode roles. Also hopefully there will be some kind of mesh support either broadcast or routed, or the stack will be open source enough to build one.