Search found 8912 matches
- Thu Mar 31, 2022 1:27 am
- Forum: Hardware
- Topic: ADC ISR pinned in a specific core
- Replies: 3
- Views: 2059
Re: ADC ISR pinned in a specific core
To answer your main question: the ADC ISR (and ISRs in general) can't be migrated between cores, so they're defacto 'pinned' to a core already. (The core is the one that installs the interrupt. Installing the interrupt generally happens when you install the driver, so the ISR is 'pinned' to the task...
- Thu Mar 31, 2022 1:17 am
- Forum: Documentation
- Topic: ESP32-S3 LCD and I2S FULL documentation
- Replies: 134
- Views: 1463118
Re: ESP32-S3 LCD and I2S FULL documentation
Cache is described in section 3 of the TRM, but here's the Cliffs Notes: There's a certain amount (configurable, I think 32 or 16K) of cache between the CPU and the PSRAM/flash. The idea is that if you access a byte in psram, the cache loads not only that byte but an entire cache line (32 or 64 byte...
- Wed Mar 30, 2022 8:18 am
- Forum: Hardware
- Topic: ESP32-S3-WROOM-1 On Custom PCB
- Replies: 9
- Views: 6419
Re: ESP32-S3-WROOM-1 On Custom PCB
You should not need a DTR/RTS/whatever circuit with the internal USB-JTAG-serial adapter. However, I think C8 in this case is the culprit: on bootup the cap is empty and will pull down GPIO0 to ground, meaning the chip will start in download mode. Remove that cap and you'll probably have normal beha...
- Wed Mar 30, 2022 1:01 am
- Forum: ESP-IDF
- Topic: One Time programmable area - OTP area in ESP partition
- Replies: 4
- Views: 2313
Re: One Time programmable area - OTP area in ESP partition
Protected flash regions are highly dependent on the flash chip in use - the flash chip must support them, you need to align your request with what the flash chips actual protected region boundary size are, and the ESP-IDF driver for the flash chip must have support for setting these protected regions.
- Wed Mar 30, 2022 12:54 am
- Forum: Hardware
- Topic: ESP32-S3-WROOM-1 On Custom PCB
- Replies: 9
- Views: 6419
Re: ESP32-S3-WROOM-1 On Custom PCB
In normal situations, the USB-serial-JTAG adapter should be able to take you from a running program back into download mode and back to a running program all on its own. There's a few situations where it cannot (for instance, if your software accidentally reconfigures the pins used for USB) and in t...
- Wed Mar 30, 2022 12:51 am
- Forum: Documentation
- Topic: ESP32-S3 LCD and I2S FULL documentation
- Replies: 134
- Views: 1463118
Re: ESP32-S3 LCD and I2S FULL documentation
You may be on to something wrt caching being the issue. To answer your questions: You can't disable cache. You also can't make it coherent wrt edma. What you need to do is make sure the data is written back to the PSRAM after you write it (using the CPU) and before it is read by DMA. You can use the...
- Tue Mar 29, 2022 7:36 am
- Forum: ESP-IDF
- Topic: esp_http_client PSRAM use
- Replies: 5
- Views: 2114
Re: esp_http_client PSRAM use
Can you take a look at the startup messages; can you see the PSRAM being detected in there?
- Tue Mar 29, 2022 7:34 am
- Forum: Hardware
- Topic: ESP32-S3-WROOM-1 On Custom PCB
- Replies: 9
- Views: 6419
Re: ESP32-S3-WROOM-1 On Custom PCB
First of all, you don't need or want R14; the ESP32S3 already has that resistor built in. Secondly, did you reset the chip with GPIO0 low? If so, the USB peripheral can't get you out of that state; you'll need to reset the chip with GPIO0 high.
- Tue Mar 29, 2022 4:49 am
- Forum: Documentation
- Topic: ESP32-S2: SPI documentation ambiguities
- Replies: 4
- Views: 4991
Re: ESP32-S2: SPI documentation ambiguities
I can't answer your questions directly, but I've made an internal issue with the documentation team; if they squirrel out the answers we'll reply here.
- Tue Mar 29, 2022 4:44 am
- Forum: ESP-IDF
- Topic: esp_http_client PSRAM use
- Replies: 5
- Views: 2114
Re: esp_http_client PSRAM use
No, those examples are supposed to run even on a board without psram, so them using up a full 4MiB sounds odd. How did you measure this?