I have enabled CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION and now will test how is it working. Sorry let me rephrase: PHY calibration data is never stored in the phy_init partition. That is for PHY init data (and only if enabled via CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION) which is not relevant to your is...

Can you clarify what do you mean? Something like this: # Default for system config (PHY, WiFi, etc): nvs, data, nvs, , 0x6000, # Separate NVS partition for user settings: settings, data, nvs, , 0x6000, To avoid any confusion, PHY calibration data is not stored in the phy_init partition. If you have...

How would you do an RTC reset? #include "soc/rtc_cntl_struct.h" #include "hal/wdt_types.h" #include "hal/rwdt_ll.h" void __attribute__((noreturn)) esp_rtc_reset(void) { rwdt_ll_write_protect_disable(&RTCCNTL); rwdt_ll_disable(&RTCCNTL); rwdt_ll_config_stage(&RTCCNTL, WDT_STAGE0, 0, WDT_STAGE_ACTION...

zazas321 wrote: ↑

Wed Jan 19, 2022 11:40 am

1What is this calibration data exactly?

It's not documented, unfortunately. Some kind of tuning parameters for RF transmission vs power.

If you'd like this to change, please add a comment here: https://github.com/espressif/esp-idf/issues/7324
NVS failure is another good case.

0x1105 = ESP_ERR_NVS_NOT_ENOUGH_SPACE Calibration data is almost 2kB, your NVS partition is small, and you use this particular device a lot. NVS is full. https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/RF_calibration.html#full-calibration Full calibration is relatively slow an...

Your best shot would be to gracefully shut it down before a soft reset, although it might not be possible to do this in all cases (eg. a failed assertion somewhere). On startup, try to clear RTC_CNTL_ULP_CP_SLP_TIMER_EN and hope the ULP hits a halt soon? Fill ULP program memory with halt instruction...

I had another look at this today out of interest, as there have been significant improvements to light sleep since my comment in the linked thread - average ESP32 light sleep current now settles <400uA with the right config. With a very high listen interval of 30 (ie. max ~3 seconds between receivin...

ULP can access RTC slow clock ticks (48 bits, usually ~150khz) so this is possible. You need to set a bit to update the ticks register, and wait until valid as here: https://github.com/boarchuz/HULP/blob/efdf5df7ef750584274bc743fa6374f4691c2d8f/src/hulp_macros.h#L550-L558 Example using this to do a ...

Check VDD on the CP2102N

Using a simple RTC wakeup stub to set a pin high after ext0 trigger, I noted today that ESP32S3 takes over 8ms while the ESP32 gets it done in just 1.27ms . While it's still pretty quick, that is a relatively huge increase in ROM latency. For context, this would mean the ESP32 can potentially get th...