Reserve an area using the partition table esp_partition_read(), esp_partition_write(), esp_partition_erase_range() are equivalent to spi_flash_read(), spi_flash_write(), spi_flash_erase_range(), but operate within partition boundaries https://esp-idf.readthedocs.io/en/latest/api-reference/storage/sp...

That is exactly what the gpio isr service does for you

Gpio interrupts are already multiplexed into one cpu interrupt so you don't need any flags to make it shared.

http://esp-idf.readthedocs.io/en/latest ... gpio_num_t

But you probably should be using latching relays or latching solenoid valves

Nice. I think it is possible to give each cpu access to separate external 4MB memory regions so 8 total, but they access it through same address space. Mmu/cache handles the mapping.

https://github.com/nkolban/ESP32_Explorer

Spend some time searching GitHub

Well it would be very strange to have modules in the same reel have some with calibration data and some not so you'd only have to test one. Unless calibration hardware is fully integrated into 100% production flow it seems like a waste to do it for applications that aren't even going to use adc, whi...