That 4k is longer reserved in IDF: https://github.com/espressif/esp-idf/commit/ef10c2576ff14afa033ef22105406399abc570af You can use RTC_DATA_ATTR macro to place there or access memory at 0x50000000, eg. https://github.com/espressif/esp-idf/blob/178b122c145c19e94ac896197a3a4a9d379cd618/components/ulp...

Not directly possible. You'll either need to include all variations of ADC instruction in the ULP program and have the ULP jump to the correct one based on a variable that can be changed by the SoC, or change the ULP program when you want to change the ADC channel. You could try updating just the on...

Looks like it's because adc_set_init_code, which includes a ESP_LOGD, is being called in a critical section from adc1_get_raw.

Comment out that line or reduce logging level, and consider filing an issue on GitHub.

Is there a busy loop in Buzzer and other wdt-triggering tasks? Perhaps in some function common to them all?
Post Buzzer task here?

As an aside, can someone confirm that the second OTA's offset is 0x20000 because it has to be aligned on a multiple of 0x1000? 0x200000, aligned to 0x10000 after the end of the previous partition. I think you're seeing this error because flash is erased in 4K (SPI_FLASH_SEC_SIZE) sectors and your a...

As I understand, it's a boolean to enable the check (not the expected logic level as perhaps you're interpreting it?).

Try "true" in its place.

i2c_master_write_byte(cmd, (address << 1) | I2C_MASTER_WRITE , I2C_MASTER_ACK);

That third arg is for ACK check, and I2C_MASTER_ACK == 0.

You need to poke the RTC controller to update the register.

eg. with macros it would look something like this:

You are dereferencing the arg "(void *)TIMER_0" (ie. NULL) in your handler.