Okay, so the register sets are similar, but the register *names* used in the ESP8266 Arduino core are not compatible with the ESP32. ESP8266 Arduino core uses register names defined here: https://github.com/esp8266/Arduino/blob/master/cores/esp8266/esp8266_peri.h Note that these names are different ...

Whenever software changes APB frequency, it stores the new value into RTC_APB_FREQ_REG (that's one of the general purpose retention registers). There is a function which gets APB frequency value from this register in rtc_clk.c: static uint32_t reg_val_to_clk_val(uint32_t val) { return val & UINT16_M...

That's correct, rtc_clk_apll_enable(true, 0, 0, 6, 2) gives 50 MHz output.

With the above change rtc_clk_apll_enable works well both on rev0 and rev1 chips. The reason why rtc_clk_apll_enable(true, 0, 0, 1, 0) doesn't work is that the arguments don't meet the range given in the function documentation: apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) ...

spurious watchdog resets ... which used to happen after second wakeup Thanks for giving the description of the problem. Yes, this was an issue in the master branch a few commits ago; I remember giving this workaround in one of the github issues. This does not solve any hardware bug (would have been...

This would depend on whether the pin you wish to use is an RTC_IO or not. Assuming this is not an RTC IO, you may take a look at the source code of gpio_set_direction and gpio_set_pull_mode functions. They are not defined in ROM, see components/driver/gpio.c. gpio_pad_select_gpio function is equival...

REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, 4); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, 4); Could you explain the reason behind the change? This doesn't look like it fixes any hardware bug, at least none that we know of. Could you describe the difference between behavior you see with an...

It should probably be SET_PERI_REG_BITS(RTC_CNTL_ANA_CONF_REG, 1, enable ? 0 : 1, RTC_CNTL_PLLA_FORCE_PD_S); SET_PERI_REG_BITS(RTC_CNTL_ANA_CONF_REG, 1, enable ? 1 : 0, RTC_CNTL_PLLA_FORCE_PU_S); SET_PERI_REG_BITS(RTC_CNTL_OPTIONS0_REG, 1, enable ? 0 : 1, RTC_CNTL_BIAS_I2C_FORCE_PD_S); instead.

Could you please clarify which "files" you are referring to? ESP-IDF register header files (inside soc directory)? ESP-IDF spi_master driver? Arduino SPI HAL? Arduino SPI library? The peripherals do have many things in common, so basic usage with FIFO in master mode can be implemented the same way, ...

Thanks for the report. What argument values are you passing to rtc_clk_apll_enable?