Proper EMAC/PHY design: RMII Timing Documentation Missing

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Joined: Wed Nov 21, 2018 6:53 pm

Proper EMAC/PHY design: RMII Timing Documentation Missing

Postby mikea101 » Tue Aug 13, 2019 1:10 am

EMAC RMII Timing Documentation Missing
I have combed through the ESP32 and WROOM documentation and cannot find any information on the EMAC signal AC specifications such as:
  • Clock-to-out timing of outputs such as transmit data TXD[0,1], TX_EN
  • Input setup/hold times for input signals such as RXD[0,1], CRS_DV
  • Clock spec for the ESP32 clock output on GPIO16 and GPIO17 (LAN8710AI requires < 50PPM drift and < 150ps jitter, does the ESP meet this spec?)
I have looked in:
  • Technical Reference Manual V4.0
  • ESP32 Datasheet V3.1
  • ESP32-WROOM-32 Datasheet V2.8
This detailed timing information is required to ensure that the EMAC to PHY interface is going to work properly across all variations of voltage, temperature, silicon process (and PCB layout). I’m doing an industrial design and the timing of RMII is a little tight at worst/worst/worst case (setup time) and best/best/best (hold time).
There are designs out there that seem to “work” at typical/typical/typical and yet probably don’t meet timing requirements at one or the other corner cases.

One of the most extensive EMAC forum threads is:

However, NEVER is there any due diligence about interface timing. People try things, get it working on one board, and then declare it working. However, at least some of these designs are going to be marginal and will FAIL in mass production. For example, Olimex has two different boards (ESP32-EVB, ESP32-GATEWAY) and both have completely different clocking. Even on the same board, the clocking changes over different versions!

The 3 main strategies seem to be:
  1. Use an external 50MHz clock
  2. Use GPIO16 as a 50MHz clock output for the PHY
  3. Use GPIO17 as a 50MHz clock output for the PHY (clock inverted)
The Espressif ESP32-Ethernet-Kit_A schematic shows option 1 and option 3.
For option 3 (GPIO17) this seems to be an inverted clock and yet the RMII spec requires both PHY and EMAC to be driven by the same clock phase. So how can this work across all variations of voltage, temperature, silicon process???

Could an authority from Espressif please provide the PROPER method of clocking the EMAC/PHY that meets the timing specifications across all conditions? Alternately, please provide the actual timing specification for your EMAC interface.


Posts: 10
Joined: Mon Jul 22, 2019 2:29 pm

Re: Proper EMAC/PHY design: RMII Timing Documentation Missing

Postby AloyseTech » Tue Sep 03, 2019 10:36 am

From the latest documentation ( ... t-kit.html) :
  • GPIO2 is used to enable external oscillator of the PHY.
  • GPIO0 is a source of 50 MHz reference clock for the PHY. The clock signal is first inverted, to account for transmission line delay, and then supplied to the PHY.
  • To prevent affecting the power-on state of GPIO0 by the clock output on the PHY side, the PHY external oscillator is enabled using GPIO2 after ESP32 is powered up.
  • The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-B module and therefore not available for use. If you need to use these pins, please solder a module without SPIRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
The phase inversion might be used to correct the GPIO internal line delay.

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