ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

q2222ch
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Joined: Mon Feb 27, 2017 8:30 pm

ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby q2222ch » Sat Mar 04, 2017 11:56 am

Hello,
I have a question concerning the QFN 5*5 package:
In the ESP32 Hardware Design Guidelines (V1.2, 2017.03) the Pins25 and Pins26 are swapped in the Pin Layout compared to the QFN 6*6 footprint (Figure 3, page 10 compared to Figure 2, page 9). Is this just a typo, copy/paste error or intentional?

Concerning the two different packages: When will the first devices in the QFN 5*5 package be available?- Do you plan to retire the QFN 6*6 package?


Thank you

Update: The same figure can be found in the datasheet (V1.1, Fig. 3, page 7).

q2222ch
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Joined: Mon Feb 27, 2017 8:30 pm

Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby q2222ch » Mon Mar 13, 2017 11:54 am

Is it really a new pinout as the addition of the GPIO20 at pin 39 suggests?- What is happening with pin 48 and 47?- What is the new functionality of "CAP_10N+ (pin 48) and "RES_14K" (pin 47)?

Thanks.

iosixllc
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Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby iosixllc » Fri Mar 17, 2017 12:15 am

I have the same question. Is CAP_10N+ really just CAP1 on the 6x6 and is RES_14K really just CAP2 on the 6x6? That would make sense... Also datasheet is missing information about GPIO20 and (new?) VDDA3P3 power domain...

q2222ch
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Joined: Mon Feb 27, 2017 8:30 pm

Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby q2222ch » Thu Mar 23, 2017 8:21 pm

Are there any news concerning the pinout of the QFN5*5 package or the planned availability of the device in this package?- Excuse me when I am asking again: I have finished a design with a 64MBit PSRAM chip and the QFN6*6 version of the package and I am not sure if I should wait till the QFN5*5 package will be available (especially because GPIO20 seems to be routed to a pin of the device- I am short on I/O's in my project).

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rudi ;-)
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Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby rudi ;-) » Fri Mar 24, 2017 12:07 am

q2222ch wrote:
I have finished a design with a 64MBit PSRAM chip and the QFN6*6 version of the package ....
only for interest, can you link to the type of 64MBIT PSRAM ( 1.8V ? ) ...

best wishes
rudi ;-)
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ESP_igrr
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Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby ESP_igrr » Fri Mar 24, 2017 1:51 am

Hi q2222ch,
I have forwarded these questions to the documentation team. Will update this topic soon.

q2222ch
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Joined: Mon Feb 27, 2017 8:30 pm

Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby q2222ch » Fri Mar 24, 2017 7:26 am

The devices are from Lyontek Link. However just to make it clear: I have not tested the chips till now that's what my finished but waiting design is intended for...The devices Link are- based on my information- partially introduced. The 1.8V type (LY68S6400) is available and the 3.3V type (LY68L6400) will be introduced later this year. For this reason I have asked the question in my other post viewtopic.php?f=12&t=1313 if there is really a technical reason to switch to 1.8V for the SPI flash and the PSRAM on the coming WROVER module or it is just because the 3.3V chip is not available at the moment (making the probably wrong assumption it could theoretically be possible that the PSRAM on the WROVER module could be based on the same technology).

ajaymm58
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Joined: Fri Jan 29, 2016 6:02 pm

Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby ajaymm58 » Fri Mar 24, 2017 8:39 pm

I have noticed following differences in pin assignments between the 6mm x 6mm QFN48 and 5mm x 5mm QFN48.
Referring to ESP32 Datasheet V1.2 Fig 2 on pp 6 and Fig 3 pp 7.
So it will be useful to get confirmation on these items.
It would be much better if section 2.2 "Table 1 : Pin Description" is updated with two columns for "No."
  1. Awaiting response on PIN 25/26 swap in actuality or typo?
    6x6 : P25=GPIO16 P26=VDD3P3_SDIO
    5x5 : P26=VDD3P3_SDIO P25=GPIO16
  2. One less VDDA pin on 5x5 package, correct?
    6x6 : P43=VDDA
    5x5 : P43=GPIO21
  3. Assuming #2 is correct, 5 pins have a different functionality
    6x6 : P[39:43]=GPIO22, U0RXD, U0TXD, GPIO21, VDDA
    5x5 : P[39:43]=GPIO20, GPIO22, U0RXD, U0TXD, GPIO21
    This is not specified correctly in Table 1
  4. Change in Signal names only, no change in functionality correct?
    6x6 : P[47:48]=CAP2, CAP1
    5x5 : P[47:48]=RES_14K, CAP_10N
  5. Need clarification on PAD power domain for GPIO20
    Considering that GPIO20 is between GPIO19 and GPI22, it would be reasonable that
    it's I/O PAD is powered by VDD3P3_CPU.
    But, ESP32 Pin List V2.1 document pp 4 Table IO_MUX has a row above Pin No 25 that
    indicates GPIO20 Power Domain as VSDIO
    Note: Can we also get more information on the IO_MUX functions for GPIO20 (if any)?

ajaymm58
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Joined: Fri Jan 29, 2016 6:02 pm

Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby ajaymm58 » Mon Mar 27, 2017 5:35 pm

ajaymm58 wrote:I have noticed following differences in pin assignments between the 6mm x 6mm QFN48 and 5mm x 5mm QFN48.
Referring to ESP32 Datasheet V1.2 Fig 2 on pp 6 and Fig 3 pp 7.
So it will be useful to get confirmation on these items.
It would be much better if section 2.2 "Table 1 : Pin Description" is updated with two columns for "No."
The ESP32 Datasheet released on March 27, 2017 now clearly indicates that pin assignment for 5x5 mm and 6x6 mm QFN48 packages are the SAME.
Thanks.

iosixllc
Posts: 71
Joined: Fri Mar 17, 2017 12:13 am

Re: ESP32 Pin Layout (for QFN 5*5), Pin25, Pin26

Postby iosixllc » Mon Mar 27, 2017 8:29 pm

I'm sorry, the SAME?! Exactly?

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