I2S BCK problem

Thorbijoern
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Joined: Wed Jun 03, 2020 12:57 pm

I2S BCK problem

Postby Thorbijoern » Wed Jun 03, 2020 1:33 pm

Hi,

i'm trying to get sound out of my esp32 (wemos D32 Pro) and bought a PCM5102a-Module.
I don't have much experiences with microcontrollers and the esp32, so i tried the esp-idf examples first.
I tried the peripherals/i2s and bluetooth/bluedroid/classic_bt/a2dp_sink, but both did not work.
With my oscilloscope i could see, that the BCK allways has a DC-offset of atleast 1V and only has low peak-to-peak voltages of under 1V (0.3-0.9). The offset and amplitude changes with the peripherals/i2s example every 5 seconds though.
I tried using GPIO26 and GPIO13 with both examples, but it's the same with both pins.
the data on the other pins seems to be fine.
the FMT pin on the PCM5102a-Module is wired to ground.

What am i doing wrong?
Thanks for your help, i've been trying around for quite some time allready.

(i hope i didn't pick the wrong sub-forum)

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Jakobsen
Posts: 85
Joined: Mon Jan 16, 2017 8:12 am

Re: I2S BCK problem

Postby Jakobsen » Wed Jun 03, 2020 9:06 pm

Hi Thorbjørn
Hard to tell what you are doing wrong - The IDF examples are good high quality so I guess you have something not right in you hardware setup.
Try to upload a picture or 2 - Make sure your ground are good grounds and your supply rails are stable. 5V from USB, 3V3 from esp32 module to your dac. Disconnect you line out from any other hifi - you could have a nasty ground loop here - test with headphones.

/J
Analog Digital IC designer / DevOps @ Merus Audio, Copenhagen, Denmark.
We do novel and best in class Audio amplifiers for consumer products.
Programmed assembler for C-64 back in 1980's, learned some electronics - hacking since then

Thorbijoern
Posts: 5
Joined: Wed Jun 03, 2020 12:57 pm

Re: I2S BCK problem

Postby Thorbijoern » Sun Jun 14, 2020 2:42 pm

Thank you for your answer Jakobsen.

I testet the suggestions but had no luck. The grounding and supply voltage seem fine.
I also tested with headphones but still nothing.

I took some photos so maybe you can figgure it out.
I also took photos of my scope. Wordclock and Data lines seem fine to me, but the bitclock looks off.

(had to split it in two posts, sorry)
Attachments
wordclock_LR-clock.jpg
wordclock
wordclock_LR-clock.jpg (1.02 MiB) Viewed 1037 times
setup.jpg
hardware setup
setup.jpg (1.5 MiB) Viewed 1037 times
data.jpg
i2s data
data.jpg (955.72 KiB) Viewed 1037 times

Thorbijoern
Posts: 5
Joined: Wed Jun 03, 2020 12:57 pm

Re: I2S BCK problem

Postby Thorbijoern » Sun Jun 14, 2020 2:50 pm

I took the photos of my scope with the simple i2s example running (changed the pins in the code to match the default pins from the a2dp_sink example).
As the i2s example cycles through the bitlengs the bitclock is changing (which it should i guess) but it looks off to me, it has an offset and pretty low signal amplitudes.
The pictures i took are with bitlength 24bit and with 16bit. With 16 bit the signal hat the highes and with 32bit the lowest amplitude.

I also checked that the PCM5102 isn't defective and just checked the signal directly from the esp32 withoud DAC connected, but the signal is directly from the esp.

Am I wrong and that is totaly normal?
Attachments
bitclock_middle.jpg
bitclock when 24bits
bitclock_middle.jpg (914.84 KiB) Viewed 1037 times
bitclock_high.jpg
bitclock when 16bits
bitclock_high.jpg (943.94 KiB) Viewed 1037 times

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Jakobsen
Posts: 85
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Re: I2S BCK problem

Postby Jakobsen » Mon Jun 15, 2020 8:24 am

Hi
No not normal at all - your LR clock should be you sample rate. I do not know of any setup that will end up with 36 Khz.
If you able to connect you phone audio source over Bluetooth you will be notified on any sample rate change from the source and the resulting call to set i2s clock with the resulting BCK clock.

Try to get that rolling and look for monitor log:

I (613) I2S: DMA Malloc info, datalen=blocksize=240, dma_buf_count=6
I (613) I2S: PLL_D2: Req RATE: 44100, real rate: 44642.000, BITS: 16, CLKM: 14, BCK: 8, MCLK: 11289966.924, SCLK: 1428544.000000, diva: 64, divb: 11

resulting for this call in a2dp_sink example

case ESP_A2D_AUDIO_CFG_EVT: {
a2d = (esp_a2d_cb_param_t *)(p_param);
ESP_LOGI(BT_AV_TAG, "A2DP audio stream configuration, codec type %d", a2d->audio_cfg.mcc.type);
// for now only SBC stream is supported
if (a2d->audio_cfg.mcc.type == ESP_A2D_MCT_SBC) {
int sample_rate = 16000;
char oct0 = a2d->audio_cfg.mcc.cie.sbc[0];
if (oct0 & (0x01 << 6)) {
sample_rate = 32000;
} else if (oct0 & (0x01 << 5)) {
sample_rate = 44100;
} else if (oct0 & (0x01 << 4)) {
sample_rate = 48000;
}
i2s_set_clk(0, sample_rate, 16, 2);

ESP_LOGI(BT_AV_TAG, "Configure audio player %x-%x-%x-%x",
a2d->audio_cfg.mcc.cie.sbc[0],
a2d->audio_cfg.mcc.cie.sbc[1],
a2d->audio_cfg.mcc.cie.sbc[2],
a2d->audio_cfg.mcc.cie.sbc[3]);
ESP_LOGI(BT_AV_TAG, "Audio player configured, sample rate=%d", sample_rate);
}
break;
}
/j
Analog Digital IC designer / DevOps @ Merus Audio, Copenhagen, Denmark.
We do novel and best in class Audio amplifiers for consumer products.
Programmed assembler for C-64 back in 1980's, learned some electronics - hacking since then

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Jakobsen
Posts: 85
Joined: Mon Jan 16, 2017 8:12 am

Re: I2S BCK problem

Postby Jakobsen » Mon Jun 15, 2020 8:30 am

Full log

Code: Select all

x40081278: call_start_cpu1 at /home/jkj/esp/esp-idf/components/esp32/cpu_start.c:286

I (0) cpu_start: App cpu up.
I (459) heap_init: Initializing. RAM available for dynamic allocation:
I (466) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
I (472) heap_init: At 3FFB6388 len 00001C78 (7 KiB): DRAM
I (478) heap_init: At 3FFB9A20 len 00004108 (16 KiB): DRAM
I (484) heap_init: At 3FFCC350 len 00013CB0 (79 KiB): DRAM
I (490) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (496) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (503) heap_init: At 40094358 len 0000BCA8 (47 KiB): IRAM
I (509) cpu_start: Pro cpu start user code
I (527) spi_flash: detected chip: generic
I (528) spi_flash: flash io: dio
I (528) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (614) I2S: DMA Malloc info, datalen=blocksize=240, dma_buf_count=6
I (614) I2S: PLL_D2: Req RATE: 44100, real rate: 44642.000, BITS: 16, CLKM: 14, BCK: 8, MCLK: 11289966.924, SCLK: 1428544.000000, diva: 64, divb: 11
I (624) BTDM_INIT: BT controller compile version [1ee1530]
I (634) system_api: Base MAC address is not set
I (634) system_api: read default base MAC address from EFUSE
I (734) phy: phy_version: 4181, c9a03e2, Mar 10 2020, 12:45:06, 0, 0
I (1324) BT_AV: event: 10
I (1334) BT_AV: event: 10
I (1334) BT_AV: event: 10
I (1334) BT_AV: event: 10
I (22174) BT_AV: ESP_BT_GAP_CFM_REQ_EVT Please compare the numeric value: 41479
I (25954) BT_AV: authentication success: p10
I (25964) BT_AV: 14 5f 94 fc f4 c9 
E (26404) BT_APPL: bta_av_rc_create ACP handle exist for shdl:0
I (26414) BT_AV: A2DP connection state: Connecting, [14:5f:94:fc:f4:c9]
I (26434) BT_AV: A2DP audio stream configuration, codec type 0
I (26434) I2S: PLL_D2: Req RATE: 44100, real rate: 44642.000, BITS: 16, CLKM: 14, BCK: 8, MCLK: 11289966.924, SCLK: 1428544.000000, diva: 64, divb: 11
I (26444) BT_AV: Configure audio player 21-15-2-35
I (26444) BT_AV: Audio player configured, sample rate=44100
W (26454) BT_APPL: new conn_srvc id:19, app_id:0
I (26464) BT_AV: A2DP connection state: Connected, [14:5f:94:fc:f4:c9]
I (26544) RCCT: AVRC conn_state evt: state 1, [14:5f:94:fc:f4:c9]
I (26544) RCCT: AVRC remote features 259, TG features d1
I (26564) RCCT: remote rn_cap: count 8, bitmask 0x1f26
I (26584) RCCT: AVRC metadata rsp: attribute id 0x1, 
I (26584) RCCT: AVRC metadata rsp: attribute id 0x2, 
I (26584) RCCT: AVRC metadata rsp: attribute id 0x4, UNKNOWN
I (26584) RCCT: AVRC metadata rsp: attribute id 0x20, 
I (26594) RCTG: AVRC register event notification: 13, param: 0x0
I (26604) RCCT: AVRC event notification: 1
I (26604) BT_AV: Playback status changed: 0x2
I (42734) RCCT: AVRC event notification: 5
I (42734) BT_AV: Play position changed: -1-ms
I (47744) BT_LOG: bta_av_link_role_ok hndl:x41 role:1 conn_audio:x1 bits:1 features:x824b

W (47744) BT_APPL: new conn_srvc id:19, app_id:1
I (47754) RCCT: AVRC event notification: 1
I (47754) BT_AV: Playback status changed: 0x0
I (47754) RCCT: AVRC event notification: 5
I (47764) BT_AV: Play position changed: -1-ms
I (47764) BT_AV: A2DP audio state: Started
I (47794) RCCT: AVRC event notification: 1
I (47794) BT_AV: Playback status changed: 0x2
I (49784) BT_AV: Audio packet count 100
I (50514) BT_AV: A2DP audio state: Suspended
I (50514) RCCT: AVRC event notification: 5
I (50514) BT_AV: Play position changed: -1-ms
I (54624) RCCT: AVRC event notification: 1
I (54624) BT_AV: Playback status changed: 0x0
I (54624) RCCT: AVRC event notification: 5
I (54624) BT_AV: Play position changed: -1-ms
I (54804) BT_LOG: bta_av_link_role_ok hndl:x41 role:1 conn_audio:x1 bits:1 features:x824b

I (54814) BT_AV: A2DP audio state: Started
I (54814) RCCT: AVRC event notification: 1
I (54814) BT_AV: Playback status changed: 0x1
I (55234) RCCT: AVRC event notification: 1
I (55234) BT_AV: Playback status changed: 0x2
I (55234) RCCT: AVRC event notification: 5
I (55234) BT_AV: Play position changed: -1-ms
I (56844) BT_AV: Audio packet count 100
I (58234) BT_AV: A2DP audio state: Suspended
I (58354) RCCT: AVRC event notification: 5
I (58354) BT_AV: Play position changed: -1-ms
I (63884) BT_LOG: bta_av_link_role_ok hndl:x41 role:1 conn_audio:x1 bits:1 features:x824b

I (63894) RCCT: AVRC event notification: 1
I (63894) BT_AV: Playback status changed: 0x1
I (63894) RCCT: AVRC event notification: 5
I (63904) BT_AV: Play position changed: -1-ms
I (63904) BT_AV: A2DP audio state: Started
I (63914) RCCT: AVRC event notification: 2
I (63964) RCCT: AVRC metadata rsp: attribute id 0x1, Footsteps
I (63964) RCCT: AVRC metadata rsp: attribute id 0x2, Alison Moyet
I (63964) RCCT: AVRC metadata rsp: attribute id 0x4, Hoodoo
I (63974) RCCT: AVRC metadata rsp: attribute id 0x20, 
I (65374) RCCT: AVRC event notification: 5
I (65374) BT_AV: Play position changed: 1513-ms
I (65924) BT_AV: Audio packet count 100
Analog Digital IC designer / DevOps @ Merus Audio, Copenhagen, Denmark.
We do novel and best in class Audio amplifiers for consumer products.
Programmed assembler for C-64 back in 1980's, learned some electronics - hacking since then

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jgustavoam
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Location: Belo Horizonte , Brazil
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Re: I2S BCK problem

Postby jgustavoam » Mon Jun 15, 2020 11:23 pm

Hi ,
I found this project:
https://github.com/smurf0969/ESP32_ESP8 ... eaker_OLED

In the I2S example of IDF firmware:
https://github.com/espressif/esp-idf/bl ... ple_main.c

#define I2S_BCK_IO (GPIO_NUM_13) connect to PCM5102 BCK ( serial clock)
#define I2S_WS_IO (GPIO_NUM_15) connect to PCM5102 LRCK (left/right clock)
#define I2S_DO_IO (GPIO_NUM_21) Conect to PCM5102 DIN

Did you used these pins?

There is a lot of configuration to make a DAC to play sounds!
https://www.espressif.com/sites/default ... ual_en.pdf
Chapter 12 - I2S

PCM5102 Datasheet:
https://www.ti.com/lit/ds/symlink/pcm51 ... 52FPCM5102

Be careful with some protoboards, some of them do not have extended connections on the bus on the gnd and the VCC! Check with ohmmeter.
Retired IBM Brasil
Electronic hobbyist since 1976.

Thorbijoern
Posts: 5
Joined: Wed Jun 03, 2020 12:57 pm

Re: I2S BCK problem

Postby Thorbijoern » Wed Jun 17, 2020 3:47 pm

@Jakobsen i used the i2s example and not the a2dp_sink example for the pictures.
there the sample rate is defined as 36000, so everything fine with the wordclock. in the source: https://github.com/espressif/esp-idf/bl ... main.c#L21

@jgustavoam as stated i changed the pin definitions in the i2s example source to match the pins used by the a2dp_sink example.

changed pin definitions of the i2s example:

Code: Select all

#define I2S_BCK_IO (GPIO_NUM_26)
#define I2S_WS_IO (GPIO_NUM_22)
#define I2S_DO_IO (GPIO_NUM_25)
i don't get what you mean wth the board not having GND and VCC... it clearly has like shown in the picture.
and i don't think i have to make a ton of changes to good-quality examples that where meant to work with this chip i use or with other standards-following chips...


As stated previously the only thing i can't explain are the workings of the bitclock which is just all ower the place but somehow totally ignored by you...

wordclock is atleast a nice digital squarewave wich is more or less 3.3V, but why does BCK have 1.6V offset and <1V peak-to-peak? shouldn't BCK also be a 3.3V squarewave?

Thorbijoern
Posts: 5
Joined: Wed Jun 03, 2020 12:57 pm

Re: I2S BCK problem

Postby Thorbijoern » Wed Jun 17, 2020 9:12 pm

So I got new DAC modules today and it's working just fine with both I2S and a2dp_sink examples... the new modules are kinda simpler and have usefull solder bridges simplifying the "settings" of the DAC chip.
Guess BCK is fine, but i'm still confused why BCK is so different.
I'll do some testing to figgure out whats wrong about the other type of modules.
Thanks for your help though @Jakobsen and @jgustavoam.

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