ESP32-WROVER tests & issues

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loboris
Posts: 514
Joined: Wed Dec 21, 2016 7:40 pm

Re: ESP32-WROVER tests & issues

Postby loboris » Mon Jul 03, 2017 10:10 am

@ESP_Sprite:
For tests on ESP-WROOVER_KIT v3 with ESP-WROVER module I'm using the demo program from
https://github.com/loboris/ESP32_TFT_library.
You can clone or download it for testing.

Configure with menuconfig:
→ Serial flasher config→ Flash SPI mode: QIO
→ Serial flasher config→ Flash SPI speed: 80 MHz
→ Serial flasher config→ Flash size: 4 MB
→ TFT Display DEMO Configuration→ Running on ESP-WROVER-KIT [*][/b]
→ Component config → ESP32-specific→ Panic handler behaviour: Print registers and halt

All other settings default.

Use make flashfs to flash spiffs image before first run.

Resistors R140-145, R146 and R147 removed.

The crash message is usually:

Code: Select all

Guru Meditation Error of type IllegalInstruction occurred on core  0. Exception was unhandled.
With → Serial flasher config→ Flash SPI speed: 40 MHz tested for 12 hours without crash.

-------------------------------------------------------

Tested on SparkFun ESP32 Thing with → Serial flasher config→ Flash SPI speed: 80 MHz for more than 24 hours run without crash.

ESP_Sprite
Posts: 3914
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32-WROVER tests & issues

Postby ESP_Sprite » Mon Jul 03, 2017 11:12 am

Thanks, will look into this.

Edit: You don't happen to have a way to measure Vdd_SIO, have you?

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loboris
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Re: ESP32-WROVER tests & issues

Postby loboris » Mon Jul 03, 2017 3:44 pm

ESP_Sprite wrote:... You don't happen to have a way to measure Vdd_SIO, have you?
No, the ESP-WROVER module is shielded. But it should be 1.8V, as it has PSRAM chip ...

Image
Last edited by loboris on Mon Jul 03, 2017 10:43 pm, edited 1 time in total.

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loboris
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Joined: Wed Dec 21, 2016 7:40 pm

Re: ESP32-WROVER tests & issues

Postby loboris » Mon Jul 03, 2017 8:32 pm

The crash with 80MHz spi flash clock also happens when running ESP32-Doom.
With 40 MHz spi flash clock, it runs for hours without crash.

WiFive
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Joined: Tue Dec 01, 2015 7:35 am

Re: ESP32-WROVER tests & issues

Postby WiFive » Mon Jul 03, 2017 9:09 pm

loboris wrote:
ESP_Sprite wrote:... You don't happen to have a way to measure Vdd_SIO, have you?
No, the ESP-WROVER module is shilded. But it should be 1.8V, as it has PSRAM chip ...
I think maybe he meant to imply measuring to see if there were any glitches on vdd_sdio

WiFive
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Joined: Tue Dec 01, 2015 7:35 am

Re: ESP32-WROVER tests & issues

Postby WiFive » Mon Jul 03, 2017 9:12 pm

ESP_Sprite wrote:I also ran into the 80MHz QIO mode problem. The issue is essentially that the SPI clock and cs lines (iirc) are made available on pins as well, but the parasitic capacitance that results from that kills the SPI signals at 80MHz. If you have a soldering iron, the fix is simple: on the V3 board, you can remove R140-145, R146 and R147 (all 0 ohm resistors, if you ever need to replace them) and the thing should be stable at QIO and 80MHz. At the moment, for some reason I can't get the SPI flash to work reliably on 80MHz yet; we're in the process of investigating why this is. For now, please set it to 40MHz mode (option is somewhere in menuconfig, under 'esp32-specific options').
So just to clarify, spiram works at 80mhz with resistor mod but spiflash does not work at 80mhz and this is consistent with observations by both loboris and sprite?

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loboris
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Re: ESP32-WROVER tests & issues

Postby loboris » Mon Jul 03, 2017 10:36 pm

WiFive wrote:So just to clarify, spiram works at 80mhz with resistor mod but spiflash does not work at 80mhz and this is consistent with observations by both loboris and sprite?
spiflash does work at 80mhz (with resistor mod), but always crashes after some time (minutes to hours).
spiram can work at 80Mhz, but only if spiflash runs at 80MHz

From components/esp32/Kconfig:
choice SPIRAM_CACHE_MODE
bool "Set FLASH and SRAM cache mode"
default SRAM_CACHE_SPEED_40M
help
The ESP32 can access both of the flash and sram chip by CACHE.
If SPI SRAM is enabled, we only support three combinations of SPI speed mode we supported now:
1. Flash SPI running at 40Mhz and SRAM SPI running at 40Mhz
2. Flash SPI running at 80Mhz and SRAM SPI running at 40Mhz
3. Flash SPI running at 80Mhz and SRAM SPI running at 80Mhz
note: If the third mode(80Mhz+80Mhz) is enabled, VSPI port will be occupied by the system,
Application code should never touch VSPI hardware in this case.
WiFive wrote:I think maybe he meant to imply measuring to see if there were any glitches on vdd_sdio
I can't access Vdd_sdio without removing the shield.

ESP_Sprite
Posts: 3914
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32-WROVER tests & issues

Postby ESP_Sprite » Tue Jul 04, 2017 2:16 am

Spiflash works at 40MHz, but for Loboris it always crashes at 80MHz. I'm not sure if that's incidental or not, to be honest, because my board does not seem to do it. When I left the office yesterday I left the Doom demo running at 80MHz SPI flash, so I can find out more when I return there, though :)
Edit: It crashed.

I never have gotten PSRAM to work at 80MHz without some weird crashes, but that functionality is still very new, so I suspect a timing bug or something there.

User avatar
loboris
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Re: ESP32-WROVER tests & issues

Postby loboris » Tue Jul 04, 2017 8:49 am

ESP_Sprite wrote:I never have gotten PSRAM to work at 80MHz without some weird crashes, but that functionality is still very new, so I suspect a timing bug or something there.
I have successfully run the simple test program with PSRAM at 80MHz for hours.
The program only does simple allocate/compare/free of the PSRAM the memory:

Code: Select all

    #ifdef CONFIG_MEMMAP_SPIRAM_ENABLE    
    uint32_t t1, t2;
    uint8_t *buf1 = NULL;
    uint8_t *buf2 = NULL;
    uint8_t testb;
    int pass = 0;
    while (1)  {  
        vTaskDelay(1000 / portTICK_PERIOD_MS);
        pass++;

        if (pass % 2) testb = 0xA5;
        else testb = 0x5A;
        
        printf("\n======= PSRAM Test pass %d =======\n", pass);
        uint32_t heap_free = esp_get_free_heap_size();
        //goto rlc2;

        #ifdef CONFIG_MEMMAP_SPIRAM_ENABLE_MALLOC
        printf("Allocating 2 memory buffers (2 * %u bytes) with \"malloc\"\n\n", BUF_SIZE);
        buf1 = malloc(BUF_SIZE);
        buf2 = malloc(BUF_SIZE);
        #else
        printf("Allocating 2 memory buffers (2 * %u bytes) with \"pvPortMallocCaps:MALLOC_CAP_SPIRAM\"\n\n", BUF_SIZE);
        buf1 = pvPortMallocCaps(BUF_SIZE, MALLOC_CAP_SPIRAM);
        buf2 = pvPortMallocCaps(BUF_SIZE, MALLOC_CAP_SPIRAM);
        #endif
        if ((buf1 == NULL) || (buf2 == NULL)) {
            printf("Buffer allocation error!\n");
            continue;
        }
        uint32_t heap_free_after = esp_get_free_heap_size();

        t1 = clock();
        memset(buf1, testb, BUF_SIZE);
        memset(buf2, testb, BUF_SIZE);
        t1 = clock() - t1;
        
        t2 = clock();
        int res = memcmp(buf1, buf2, BUF_SIZE);
        t2 = clock() - t2;
        
        float bs = ((1000.0 / (float)t1 * (float)(BUF_SIZE*2))) / 1048576.0;
        printf("  free heap (before alloc): %u\n", heap_free);
        printf("   free heap (after alloc): %u\n", heap_free_after);
        printf("               memset time: %u ms; %f MB/sec\n", t1, bs);
        bs = ((1000.0 / (float)t2 * (float)(BUF_SIZE))) / 1048576.0;
        if (res == 0) printf("               memcmp time: %u ms; %f MB/sec\n", t2, bs);
        else printf("               memcmp time: %u ms; FAILED\n", t2);

        free(buf2);
        free(buf1);
    }
    #endif

Code: Select all

I (44) boot: ESP-IDF v2.0-rc1-892-gded1cd3d 2nd stage bootloader
I (44) boot: compile time 10:41:42
I (60) boot: Enabling RNG early entropy source...
I (62) qio_mode: Enabling QIO for flash chip GD
I (78) boot: SPI Speed      : 80MHz
I (91) boot: SPI Mode       : QIO
I (103) boot: SPI Flash Size : 4MB
I (116) boot: Partition Table:
I (127) boot: ## Label            Usage          Type ST Offset   Length
I (150) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (173) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (196) boot:  2 factory          factory app      00 00 00010000 00100000
I (219) boot:  3 storage          Unknown data     01 81 00110000 00100000
I (243) boot: End of partition table
I (256) boot: Disabling RNG early entropy source...
I (273) boot: Loading app partition at offset 00010000
I (647) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512) 
I (648) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x06088 ( 24712) map
I (664) boot: segment 2: paddr=0x00026098 vaddr=0x3ffb0000 size=0x02b48 ( 11080) load
I (692) boot: segment 3: paddr=0x00028be8 vaddr=0x40080000 size=0x00400 (  1024) load
0x40080000: _iram_start at ??:?

I (716) boot: segment 4: paddr=0x00028ff0 vaddr=0x40080400 size=0x13dd4 ( 81364) load
I (759) boot: segment 5: paddr=0x0003cdcc vaddr=0x400c0000 size=0x00000 (     0) load
I (769) boot: segment 6: paddr=0x0003cdd4 vaddr=0x00000000 size=0x03234 ( 12852) 
I (793) boot: segment 7: paddr=0x00040010 vaddr=0x400d0018 size=0x1cb18 (117528) map
0x400d0018: _flash_cache_start at ??:?

I (820) cpu_start: PSRAM mode: flash 80m sram 80m
I (836) cpu_start: PSRAM initialized, cache is in even/odd (2-core) mode.
I (859) cpu_start: Pro cpu up.
I (870) cpu_start: Starting app cpu, entry point is 0x40080e68
0x40080e68: call_start_cpu1 at /home/LoBo2_Razno/ESP32/esp-idf_psram/components/esp32/./cpu_start.c:217

I (0) cpu_start: App cpu up.
I (903) heap_alloc_caps: Initializing. RAM available for dynamic allocation:
I (925) heap_alloc_caps: At 3F800000 len 00400000 (4096 KiB): SPIRAM
I (947) heap_alloc_caps: At 3FFAE2A0 len 00001D60 (7 KiB): DRAM
I (967) heap_alloc_caps: At 3FFB5D80 len 0002A280 (168 KiB): DRAM
I (988) heap_alloc_caps: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (1009) heap_alloc_caps: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (1030) heap_alloc_caps: At 400941D4 len 0000BE2C (47 KiB): IRAM
I (1051) cpu_start: Pro cpu start user code
I (1107) cpu_start: Starting scheduler on PRO CPU.
I (219) cpu_start: Starting scheduler on APP CPU.

Hello world!
ESP32 with 2 CPU cores, silicon rev 1, 4MB external flash

FreeRTOS RUNNING ON BOTH CORES

======= PSRAM Test pass 1 =======
Allocating 2 memory buffers (2 * 2048000 bytes) with "pvPortMallocCaps:MALLOC_CAP_SPIRAM"

  free heap (before alloc): 4488212
   free heap (after alloc): 392196
               memset time: 270 ms; 14.467592 MB/sec
               memcmp time: 250 ms; 7.812500 MB/sec

======= PSRAM Test pass 2 =======
Allocating 2 memory buffers (2 * 2048000 bytes) with "pvPortMallocCaps:MALLOC_CAP_SPIRAM"

  free heap (before alloc): 4487896
   free heap (after alloc): 391880
               memset time: 270 ms; 14.467592 MB/sec
               memcmp time: 250 ms; 7.812500 MB/sec

If I add the code to enable WiFi and simple SNTP function, the program crashes after some time (or on start) with FreeRTOR running on both cores. It looks it is not related to PSRAM running at 80MHz, as the same happens with PSRAM running at 40MHz.

Code: Select all

I (44) boot: ESP-IDF v2.0-rc1-892-gded1cd3d 2nd stage bootloader
I (44) boot: compile time 10:37:54
I (60) boot: Enabling RNG early entropy source...
I (62) qio_mode: Enabling QIO for flash chip GD
I (78) boot: SPI Speed      : 80MHz
I (90) boot: SPI Mode       : QIO
I (103) boot: SPI Flash Size : 4MB
I (115) boot: Partition Table:
I (127) boot: ## Label            Usage          Type ST Offset   Length
I (149) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (173) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (196) boot:  2 factory          factory app      00 00 00010000 00100000
I (219) boot:  3 storage          Unknown data     01 81 00110000 00100000
I (243) boot: End of partition table
I (255) boot: Disabling RNG early entropy source...
I (273) boot: Loading app partition at offset 00010000
I (946) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512) 
I (946) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x09598 ( 38296) map
I (962) boot: segment 2: paddr=0x000295a8 vaddr=0x3ffb0000 size=0x02b60 ( 11104) load
I (990) boot: segment 3: paddr=0x0002c110 vaddr=0x40080000 size=0x00400 (  1024) load
0x40080000: _iram_start at ??:?

I (1015) boot: segment 4: paddr=0x0002c518 vaddr=0x40080400 size=0x152ac ( 86700) load
I (1060) boot: segment 5: paddr=0x000417cc vaddr=0x400c0000 size=0x00000 (     0) load
I (1068) boot: segment 6: paddr=0x000417d4 vaddr=0x00000000 size=0x0e834 ( 59444) 
I (1093) boot: segment 7: paddr=0x00050010 vaddr=0x400d0018 size=0x4d4f4 (316660) map
0x400d0018: _flash_cache_start at ??:?

I (1120) cpu_start: PSRAM mode: flash 80m sram 80m
I (1136) cpu_start: PSRAM initialized, cache is in even/odd (2-core) mode.
I (1159) cpu_start: Pro cpu up.
I (1171) cpu_start: Starting app cpu, entry point is 0x40080f58
0x40080f58: call_start_cpu0 at /home/LoBo2_Razno/ESP32/esp-idf_psram/components/esp32/./cpu_start.c:135

I (0) cpu_start: App cpu up.
I (1203) heap_alloc_caps: Initializing. RAM available for dynamic allocation:
I (1226) heap_alloc_caps: At 3F800000 len 00400000 (4096 KiB): SPIRAM
I (1248) heap_alloc_caps: At 3FFAE2A0 len 00001D60 (7 KiB): DRAM
I (1269) heap_alloc_caps: At 3FFB7B48 len 000284B8 (161 KiB): DRAM
I (1290) heap_alloc_caps: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (1311) heap_alloc_caps: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (1333) heap_alloc_caps: At 400956AC len 0000A954 (42 KiB): IRAM
I (1354) cpu_start: Pro cpu start user code
I (1409) cpu_start: Starting scheduler on PRO CPU.
I (220) cpu_start: Starting scheduler on APP CPU.

Hello world!
ESP32 with 2 CPU cores, silicon rev 1, 4MB external flash

FreeRTOS RUNNING ON BOTH CORES
GET NTP TIME
I (320) [PSRAM Test]: Time is not set yet. Connecting to WiFi and getting time over NTP.
I (380) wifi: wifi firmware version: 6c86a1c
I (380) wifi: config NVS flash: enabled
I (380) wifi: config nano formating: disabled
I (380) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE
I (390) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE
Guru Meditation Error: Core  1 panic'ed (Cache disabled but cached memory region accessed)
Register dump:
PC      : 0x40083654  PS      : 0x00060534  A0      : 0x800812fe  A1      : 0x3ffaf1c0  
0x40083654: spi_flash_disable_interrupts_caches_and_other_cpu at /home/LoBo2_Razno/ESP32/esp-idf_psram/components/spi_flash/./cache_utils.c:117 (discriminator 1)

A2      : 0x3ffb3205  A3      : 0x00000001  A4      : 0x3ffae5c4  A5      : 0x00000000  
A6      : 0x00000000  A7      : 0x00000000  A8      : 0x00000000  A9      : 0x3ffaf1a0  
A10     : 0x00000820  A11     : 0x3ffb3210  A12     : 0x00000006  A13     : 0x3ff00058  
A14     : 0x00000828  A15     : 0x20000000  SAR     : 0x00000000  EXCCAUSE: 0x00000007  
EXCVADDR: 0x00000000  LBEG    : 0x00000000  LEND    : 0x00000000  LCOUNT  : 0x00000000  

Backtrace: 0x40083654:0x3ffaf1c0 0x400812fe:0x3ffaf1e0
0x40083654: spi_flash_disable_interrupts_caches_and_other_cpu at /home/LoBo2_Razno/ESP32/esp-idf_psram/components/spi_flash/./cache_utils.c:117 (discriminator 1)

0x400812fe: esp_intr_disable at /home/LoBo2_Razno/ESP32/esp-idf_psram/components/esp32/./intr_alloc.c:626


CPU halted.
With FreeRTOS running only on first core the program runs without crash.

Code: Select all

I (43) boot: ESP-IDF v2.0-rc1-892-gded1cd3d 2nd stage bootloader
I (44) boot: compile time 09:56:35
I (55) boot: Enabling RNG early entropy source...
I (62) qio_mode: Enabling QIO for flash chip GD
I (78) boot: SPI Speed      : 80MHz
I (90) boot: SPI Mode       : QIO
I (103) boot: SPI Flash Size : 4MB
I (115) boot: Partition Table:
I (127) boot: ## Label            Usage          Type ST Offset   Length
I (149) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (173) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (196) boot:  2 factory          factory app      00 00 00010000 00100000
I (219) boot:  3 storage          Unknown data     01 81 00110000 00100000
I (243) boot: End of partition table
I (255) boot: Disabling RNG early entropy source...
I (273) boot: Loading app partition at offset 00010000
I (945) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512) 
I (946) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x09314 ( 37652) map
I (962) boot: segment 2: paddr=0x00029324 vaddr=0x3ffb0000 size=0x02358 (  9048) load
I (989) boot: segment 3: paddr=0x0002b684 vaddr=0x40080000 size=0x00400 (  1024) load
0x40080000: _iram_start at ??:?

I (1014) boot: segment 4: paddr=0x0002ba8c vaddr=0x40080400 size=0x14bbc ( 84924) load
I (1059) boot: segment 5: paddr=0x00040650 vaddr=0x400c0000 size=0x00000 (     0) load
I (1067) boot: segment 6: paddr=0x00040658 vaddr=0x00000000 size=0x0f9b0 ( 63920) 
I (1092) boot: segment 7: paddr=0x00050010 vaddr=0x400d0018 size=0x4d294 (316052) map
0x400d0018: _flash_cache_start at ??:?

I (1119) cpu_start: PSRAM mode: flash 80m sram 80m
I (1135) cpu_start: PSRAM initialized, cache is in normal (1-core mode.
I (1158) cpu_start: Pro cpu up.
I (1169) cpu_start: Single core mode
I (1183) heap_alloc_caps: Initializing. RAM available for dynamic allocation:
I (1206) heap_alloc_caps: At 3F800000 len 00400000 (4096 KiB): SPIRAM
I (1228) heap_alloc_caps: At 3FFAE2A0 len 00001D60 (7 KiB): DRAM
I (1249) heap_alloc_caps: At 3FFB72E0 len 00008D20 (35 KiB): DRAM
I (1270) heap_alloc_caps: At 3FFC0000 len 00008000 (32 KiB): DMAONLY
I (1291) heap_alloc_caps: At 3FFC8000 len 00018000 (96 KiB): DRAM
I (1312) heap_alloc_caps: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (1334) heap_alloc_caps: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (1355) heap_alloc_caps: At 40094FBC len 0000B044 (44 KiB): IRAM
I (1376) cpu_start: Pro cpu start user code
I (1430) cpu_start: Starting scheduler on PRO CPU.

Hello world!
ESP32 with 2 CPU cores, silicon rev 1, 4MB external flash

FreeRTOS RUNNING ON FIRST CORE
GET NTP TIME
I (2462) [PSRAM Test]: Time is not set yet. Connecting to WiFi and getting time over NTP.
I (2472) wifi: wifi firmware version: 6c86a1c
I (2472) wifi: config NVS flash: enabled
I (2472) wifi: config nano formating: disabled
I (2482) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE
I (2482) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE
I (2502) wifi: Init dynamic tx buffer num: 32
I (2502) wifi: Init dynamic rx buffer num: 32
I (2502) wifi: wifi driver task: 3ffbc7f4, prio:23, stack:4096
I (2512) wifi: Init static rx buffer num: 10
I (2512) wifi: Init dynamic rx buffer num: 32
I (2522) wifi: Init rx ampdu len mblock:7
I (2522) wifi: Init lldesc rx ampdu entry mblock:4
I (2522) wifi: wifi power manager task: 0x3ffc9be8 prio: 21 stack: 2560
I (2532) [PSRAM Test]: Setting WiFi configuration SSID LoBoInternet...
I (2542) wifi: wifi timer task: 3ffcac50, prio:22, stack:3584
I (2562) phy: phy_version: 350, Mar 22 2017, 15:02:06, 0, 0
I (2562) wifi: mode : sta (24:0a:c4:11:a4:0c)
I (3882) wifi: n:11 0, o:1 0, ap:255 255, sta:11 0, prof:1
I (4642) wifi: state: init -> auth (b0)
I (4642) wifi: state: auth -> assoc (0)
I (4642) wifi: state: assoc -> run (10)
I (4692) wifi: connected with LoBoInternet, channel 11
I (9122) event: ip: 192.168.0.21, mask: 255.255.255.0, gw: 192.168.0.1
I (9122) [PSRAM Test]: Initializing SNTP
I (9622) [PSRAM Test]: System time is set.
System time is set.

======= PSRAM Test pass 1 =======
Allocating 2 memory buffers (2 * 2048000 bytes) with "malloc"

  free heap (before alloc): 4440608
   free heap (after alloc): 344592
               memset time: 270 ms; 14.467592 MB/sec
               memcmp time: 260 ms; 7.512019 MB/sec

======= PSRAM Test pass 2 =======
Allocating 2 memory buffers (2 * 2048000 bytes) with "malloc"

  free heap (before alloc): 4440380
   free heap (after alloc): 344364
               memset time: 270 ms; 14.467592 MB/sec
               memcmp time: 260 ms; 7.512019 MB/sec

Ritesh
Posts: 1158
Joined: Tue Sep 06, 2016 9:37 am
Location: India
Contact:

Re: ESP32-WROVER tests & issues

Postby Ritesh » Fri Sep 01, 2017 10:11 pm

Hi Loboris,

We have started to work on ESP32 WROVER V3 Kit in which LCD and SD card have been supported along with 4 MB SPI Flash and PSRAM support.

So, Initially, we have just checked some of IO pins and UART + I2C interface along with WiFi and other basic stuff which works fine.

Now, we want to connect 16 MB external flash into that kit. So do you have pin configuration idea to connect external SPI Flash Memory along with 4 MB Flash memory.? How it can be accessed it? Can it be accessed like total 20 MB Flash memory or in different way?

Please let me know if anyone has checked extra SPI Flash memory on this kit.
Regards,
Ritesh Prajapati

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