I2S PDM clock

kazam70
Posts: 3
Joined: Thu Nov 29, 2018 3:50 pm

I2S PDM clock

Postby kazam70 » Tue Dec 04, 2018 4:18 pm

Hi everyone,
I would like to capture audio via a mems microphone on the pdm bus.
I've already purchased an esp32-wroom-32 card with which I'm starting to try. using the configuration below I checked with the oscilloscope that the shape of the clock is poor and also has a duty cycle of 60% contrary to the PDM bus standard.
my question is: is the signal shape expected or is this shape indicative of a problem?
I'm using the configuration below.
Thanks, Paolo

i2s_config_t i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_PDM,
.sample_rate = 48000,
.bits_per_sample = 16,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_PCM,
.dma_buf_count = 2,
.dma_buf_len = 8,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1
};
pin_config = {
.ws_io_num = 4, //PDM clock
.data_in_num = 2, //PDM data
};
i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL);
i2s_set_pin(I2S_NUM_0, &pin_config);
Attachments
PDM Clock_01.jpg
PDM Clock_01.jpg (152.09 KiB) Viewed 96 times

costaud
Posts: 34
Joined: Wed Dec 30, 2015 5:09 pm

Re: I2S PDM clock

Postby costaud » Fri Dec 07, 2018 9:29 am

What kind of scope are you using, e.g. the bandwidth and sample rate ?
It's also related to the way you connect the signal and ground.

kazam70
Posts: 3
Joined: Thu Nov 29, 2018 3:50 pm

Re: I2S PDM clock

Postby kazam70 » Fri Dec 07, 2018 3:10 pm

Hi, costaud

I have used a Hantek6022BE bandwith of 20MHz e 48MS/sec. the probe ground was the esp32-wroom-32 GND pin and the probe pin is the IO4 (ws_io_in). of course I have try many other pin bat with no difference. The duty cicle it's result about 60% that is a upper limit for the i2s bus of the mic i want to use. I have five peace of ESP32-WROOM-32 board and all have the same 60% dutycicle when I use I2s PDM. however, if I use i2s standard (NO PDM) at 3 MHz clock the BCLK and WS have very good shape with perfect falling and rising front and no asimmetric dutycicle. all ather board signal are ok! only the ws_io_in clock in PDM mode of I2S_0 present this problem.
would you have any suggestions?
thanks, Paolo

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