WROOM-32 (DevKitC) QIO/40MHz operation keeps resetting

ajaymm58
Posts: 12
Joined: Fri Jan 29, 2016 6:02 pm

WROOM-32 (DevKitC) QIO/40MHz operation keeps resetting

Postby ajaymm58 » Wed Jan 18, 2017 2:35 am

I tried to configure QIO/40MHz operation (using menuconfig), and I see the following on UART0-console:

Code: Select all

ets Jun  8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
flash read err, 1000
Falling back to built-in command interpreter.
OK
>ets Jun  8 2016 00:22:57

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x3fff0008,len:8
load:0xffffffff,len:-1
ets Jun  8 2016 00:22:57

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x3fff0008,len:8
load:0xffffffff,len:-1
Is this a known issue?
Programming the image using 'make flahsh' is ok.

DIO mode it operates correctly.

Code: Select all

ets Jun  8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:8
load:0x3fff0010,len:3384
load:0x40078000,len:7452
ho 0 tail 12 room 4
load:0x40080000,len:252
entry 0x40080034
I (46) boot: ESP-IDF v1.0-387-gca9f62a 2nd stage bootloader
My build environment is Windows 10 host running MSYS2 (from esp32_win32_msys2_environment_and_toolcahin-20170111.zip)
and esp-idf sync from 1/15/2017

Also, I would like to run QSPI flash at 80MHz on DevKitC. Is that supported?

ESP_Sprite
Posts: 4396
Joined: Thu Nov 26, 2015 4:08 am

Re: WROOM-32 (DevKitC) QIO/40MHz operation keeps resetting

Postby ESP_Sprite » Wed Jan 18, 2017 3:26 am

Yes, it is a known issue. The boot code in the ROM of the ESP32 isn't directly compatible with the specific instructions the flash chip needs to use QIO mode. We are working on a workaround, expected to get into esp-idf in the coming weeks, but for now, QIO mode does not work here.

ajaymm58
Posts: 12
Joined: Fri Jan 29, 2016 6:02 pm

Re: WROOM-32 (DevKitC) QIO/40MHz operation keeps resetting

Postby ajaymm58 » Thu Jan 19, 2017 1:25 am

Thanks for the confirmation regarding QIO mode support.
1. Is DIO @80MHz tested on DevKitC (ESP-WROOM-32)?
2. Can you kindly list the target device families from GigaDevice and Winbond for which QIO mode will be supported?
3. For the planned feature support on this matter, will SPI Flash devices with QPI mode of operation in consideration?

User avatar
loboris
Posts: 514
Joined: Wed Dec 21, 2016 7:40 pm

Re: WROOM-32 (DevKitC) QIO/40MHz operation keeps resetting

Postby loboris » Thu Jan 19, 2017 5:00 pm

ajaymm58 wrote:Thanks for the confirmation regarding QIO mode support.
1. Is DIO @80MHz tested on DevKitC (ESP-WROOM-32)?
2. Can you kindly list the target device families from GigaDevice and Winbond for which QIO mode will be supported?
3. For the planned feature support on this matter, will SPI Flash devices with QPI mode of operation in consideration?
SparkFun ESP32 Thing has Winbond W25Q32FVSS SPI Flash and works without problem in QIO mode on 80MHz.

Code: Select all

configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:1
load:0x3fff0008,len:8
load:0x3fff0010,len:3384
load:0x40078000,len:7504
load:0x40080000,len:252
entry 0x40080034
I (28) boot: ESP-IDF v1.0-434-ga14bef8 2nd stage bootloader
I (29) boot: compile time 17:51:24
I (62) boot: Enabling RNG early entropy source...
I (63) boot: SPI Speed      : 80MHz
I (63) boot: SPI Mode       : QIO
I (73) boot: SPI Flash Size : 4MB

ajaymm58
Posts: 12
Joined: Fri Jan 29, 2016 6:02 pm

Re: WROOM-32 (DevKitC) QIO/40MHz operation keeps resetting

Postby ajaymm58 » Fri Mar 24, 2017 8:48 pm

ESP_Sprite wrote:Yes, it is a known issue. The boot code in the ROM of the ESP32 isn't directly compatible with the specific instructions the flash chip needs to use QIO mode. We are working on a workaround, expected to get into esp-idf in the coming weeks, but for now, QIO mode does not work here.
Is there any update on QIO mode support?
Can you confirm if W25Q32FVZPIG device is supported to work in QIO mode at 80MHz?

I appreciate the response from loboris @SparkFun, but would like to see support for in the bootloader in ESP-IDF

ESP_Angus
Posts: 2278
Joined: Sun May 08, 2016 4:11 am

Re: WROOM-32 (DevKitC) QIO/40MHz operation keeps resetting

Postby ESP_Angus » Sun Mar 26, 2017 11:33 pm

ajaymm58 wrote:
ESP_Sprite wrote:Yes, it is a known issue. The boot code in the ROM of the ESP32 isn't directly compatible with the specific instructions the flash chip needs to use QIO mode. We are working on a workaround, expected to get into esp-idf in the coming weeks, but for now, QIO mode does not work here.
Is there any update on QIO mode support?
Can you confirm if W25Q32FVZPIG device is supported to work in QIO mode at 80MHz?

I appreciate the response from loboris @SparkFun, but would like to see support for in the bootloader in ESP-IDF
Sorry for not updating this thread earlier. Support for QIO mode on other flash chips (including Winbond) has been added to IDF and is supported in the V2.0 release candidates and the current IDF master branch.

If you select QIO mode in "make menuconfig" and reflash the bootloader then it should correctly detect the chip model and enable QIO.

ESP-WROOM32 modules support QIO mode at 80MHz provided that no other devices are connected to the relevant SPI pins of the module. For other module/board designs, QIO support and maximum clock speed will depend on the board design.

Angus

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