EFUSE read/write VDD_SDIO from user application

iosixllc
Posts: 43
Joined: Fri Mar 17, 2017 12:13 am

EFUSE read/write VDD_SDIO from user application

Postby iosixllc » Sun Sep 10, 2017 6:02 pm

I need to write the EFUSE settings for VDD_SDIO in the field via firmware update. Long story, but we released boards for production before documentation came out mentioning the need for 1.8V setting for flash on ESP32-D2WD.

I'm aware of these headers but some information is missing on how to apply them:
https://github.com/espressif/esp-idf/bl ... sp_efuse.h
https://github.com/espressif/esp-idf/bl ... om/efuse.h

XPD_SDIO_FORCE Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = 0 R/W (0x0)
XPD_SDIO_REG If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = 0 R/W (0x0)
XPD_SDIO_TIEH If XPD_SDIO_FORCE & XPD_SDIO_REG, 1=3.3V 0=1.8V = 0 R/W (0x0)

I need to write the first two to enabled, and the 3rd to 1.8V. I'm also open if there is a runtime configuration available (someone on the forum mentioned some RTC registers to configure VDD_SDIO). I'm seeing a situation where our device will hard crash upon reset/flash update attempt, presumably because it is too hot (if we let it cool it will boot again).

Thanks!

ESP_igrr
Posts: 784
Joined: Tue Dec 01, 2015 8:37 am

Re: EFUSE read/write VDD_SDIO from user application

Postby ESP_igrr » Mon Sep 11, 2017 6:00 am

The procedure for writing EFUSE from software is described in the EFUSE chapter of the TRM. You also need to enable peripheral clock before accessing EFUSE, see "driver/periph_ctrl.h".

As for the software override option, you can use

Code: Select all

REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_XPD_SDIO_REG, 1);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_TIEH, 0);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE, 1);


(these are defined in soc/rtc_cntl_reg.h)

iosixllc
Posts: 43
Joined: Fri Mar 17, 2017 12:13 am

Re: EFUSE read/write VDD_SDIO from user application

Postby iosixllc » Tue Sep 12, 2017 7:37 am

Ok, so I've implemented this at startup - and the device will not boot. I've also tried running this later after the device is booted. This results in execution slowing down significantly and the wifi connection disconnecting. Thoughts?

ESP_Angus
Posts: 488
Joined: Sun May 08, 2016 4:11 am

Re: EFUSE read/write VDD_SDIO from user application

Postby ESP_Angus » Wed Sep 13, 2017 2:24 am

iosixllc wrote:Ok, so I've implemented this at startup - and the device will not boot. I've also tried running this later after the device is booted. This results in execution slowing down significantly and the wifi connection disconnecting. Thoughts?


This is certainly unexpected. Can you show exactly what you implemented?

ESP_igrr
Posts: 784
Joined: Tue Dec 01, 2015 8:37 am

Re: EFUSE read/write VDD_SDIO from user application

Postby ESP_igrr » Wed Sep 13, 2017 10:35 am

If the you are changing SDIO voltage while the CPU is running code from flash, there may be an issue due to a bounce on flash signal lines. If that is the case, you may need to place this bit of code into IRAM and wait a couple of milliseconds to let things settle down.

Also be advised that our hardware team does not recommend overriding VDD_SDIO voltage at runtime, because there will be significant amount of time between SoC reset and your app_main when VDD_SDIO will be 3.3V, damaging the flash chip. Overriding efuse values is also not a perfect solution, by the way: reading efuses takes time, and until that is done, the chip will choose VDD_SDIO level from bootstrap pin. So setting the VDD_SDIO level using a bootstrap pin is the only reliable solution.

iosixllc
Posts: 43
Joined: Fri Mar 17, 2017 12:13 am

Re: EFUSE read/write VDD_SDIO from user application

Postby iosixllc » Thu Sep 14, 2017 5:19 am

Thanks. For the runtime approach, this is what happened when I put the following lines at the very start of app_main() - it boots normally with the lines removed:
#include "soc/rtc_cntl_reg.h"
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_XPD_SDIO_REG, 1);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_TIEH, 0);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE, 1);

I (901) heap_init: Initializing. RAM available for dynamic allocation:
I (901) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
I (903) heap_init: At 3FFB3000 len 00005000 (20 KiB): DRAM
I (910) heap_init: At 3FFBBB28 len 00002000 (8 KiB): DRAM
I (917) heap_init: At 3FFCDF70 len 00012090 (72 KiB): DRAM
I (924) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (932) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (939) heap_init: At 40095090 len 0000AF70 (43 KiB): IRAM
Booting...
Guru Meditation Error of type IllegalInstruction occurred on core 0. Exception was unhandled.
Register dump:
PC : 0x400ff3c2 PS : 0x00060730 A0 : 0x800d15b3 A1 : 0x3ffb5260
A2 : 0x3ff48074 A3 : 0x82600000 A4 : 0x82200000 A5 : 0x00000000
A6 : 0x3ffc68d8 A7 : 0x3ffc698c A8 : 0x800fd597 A9 : 0x3ffb5240
A10 : 0x0000000a A11 : 0x3ffb30d4 A12 : 0x00060023 A13 : 0x00000000
A14 : 0x3ffc10c4 A15 : 0x3ffb41fc SAR : 0x00000000 EXCCAUSE: 0x00000000
EXCVADDR: 0x00000000 LBEG : 0x400014fd LEND : 0x4000150d LCOUNT : 0xfffffffd

Backtrace: 0x400ff3c2:0x3ffb5260 0x400d15b0:0x3ffb5340

Guru Meditation Error of type LoadProhibited occurred on core 0. Exception was unhandled.
Register dump:
PC : 0x400866f7 PS : 0x00060033 A0 : 0x80088c64 A1 : 0x3ffb4ec0
A2 : 0x3ffb4ef0 A3 : 0x00000020 A4 : 0x00000004 A5 : 0x00000000
A6 : 0x3ffc6918 A7 : 0x00000001 A8 : 0x3ffb4f20 A9 : 0x00000000
A10 : 0x3ffb4ef0 A11 : 0x3ffb4ec8 A12 : 0x00000020 A13 : 0x3ffc6948
A14 : 0x00000001 A15 : 0x00000000 SAR : 0x0000001b EXCCAUSE: 0x0000001c
EXCVADDR: 0x00000000 LBEG : 0x4000c46c LEND : 0x4000c477 LCOUNT : 0x00000000

Backtrace: 0x400866f7:0x3ffb4ec0 0x40088c61:0x3ffb4ef0 0x40088f4a:0x3ffb50c0 0x4008892c:0x3ffb5100 0x40088b04:0x3ffb5180 0x40081fbe:0x3ffb51a0 0x400ff3bf:0x3ffb5260 0x400ff3bf:0x3ffb5340

Guru Meditation Error of type LoadProhibited occurred on core 0. Exception was unhandled.
Register dump:
PC : 0x400866f7 PS : 0x00060033 A0 : 0x80088c64 A1 : 0x3ffb4b20
A2 : 0x3ffb4b50 A3 : 0x00000020 A4 : 0x00000004 A5 : 0x00000000
A6 : 0x3ffc6918 A7 : 0x3ff60000 A8 : 0x3ffb4b80 A9 : 0x00000000
A10 : 0x3ffb4b50 A11 : 0x3ffb4b28 A12 : 0x00000020 A13 : 0x3ffc6948
A14 : 0x3ffb51a0 A15 : 0x00000a39 SAR : 0x00000012 EXCCAUSE: 0x0000001c
EXCVADDR: 0x00000000 LBEG : 0x4000c46c LEND : 0x4000c477 LCOUNT : 0x00000000

Backtrace: 0x400866f7:0x3ffb4b20 0x40088c61:0x3ffb4b50 0x40088f4a:0x3ffb4d20 0x4008892c:0x3ffb4d60 0x40088b04:0x3ffb4de0 0x40081fbe:0x3ffb4e00 0x400866f4:0x3ffb4ec0 0x400866f4:0x3ffb4ef0 0x40088f4a:0x3ffb50c0 0x4008892c:0x3ffb5100 0x40088b04:0x3ffb5180 0x40081fbe:0x3ffb51a0 0x400ff3bf:0x3ffb5260 0x400ff3bf:0x3ffb5340


I'm back in the office and have access to my flash tools now. I tried burning the efuse, but I'm having the same issues as before:

espefuse.py --port /COM4 summary
espefuse.py v2.1-beta1
Connecting...
Security fuses:
FLASH_CRYPT_CNT Flash encryption mode counter = 0 R/W (0x0)
FLASH_CRYPT_CONFIG Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE Disable ROM BASIC interpreter fallback = 0 R/W (0x0)
ABS_DONE_0 secure boot enabled for bootloader = 0 R/- (0x0)
ABS_DONE_1 secure boot abstract 1 locked = 0 R/W (0x0)
JTAG_DISABLE Disable JTAG = 0 R/W (0x0)
DISABLE_DL_ENCRYPT Disable flash encryption in UART bootloader = 0 R/W (0x0)
DISABLE_DL_DECRYPT Disable flash decryption in UART bootloader = 0 R/W (0x0)
DISABLE_DL_CACHE Disable flash cache in UART bootloader = 0 R/W (0x0)
BLK1 Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLK2 Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLK3 Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Efuse fuses:
WR_DIS Efuse write disable mask = 4096 R/W (0x1000)
RD_DIS Efuse read disablemask = 0 R/W (0x0)
CODING_SCHEME Efuse variable block length scheme = 0 R/W (0x0)
KEY_STATUS Usage of efuse block 3 (reserved) = 0 R/W (0x0)

Config fuses:
XPD_SDIO_FORCE Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = 0 R/W (0x0)
XPD_SDIO_REG If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = 0 R/W (0x0)
XPD_SDIO_TIEH If XPD_SDIO_FORCE & XPD_SDIO_REG, 1=3.3V 0=1.8V = 0 R/W (0x0)
SPI_PAD_CONFIG_CLK Override SD_CLK pad (GPIO6/SPICLK) = 6 R/W (0x6)
SPI_PAD_CONFIG_Q Override SD_DATA_0 pad (GPIO7/SPIQ) = 17 R/W (0x11)
SPI_PAD_CONFIG_D Override SD_DATA_1 pad (GPIO8/SPID) = 8 R/W (0x8)
SPI_PAD_CONFIG_HD Override SD_DATA_2 pad (GPIO9/SPIHD) = 11 R/W (0xb)
SPI_PAD_CONFIG_CS0 Override SD_CMD pad (GPIO11/SPICS0) = 16 R/W (0x10)
DISABLE_SDIO_HOST Disable SDIO host = 0 R/W (0x0)

Identity fuses:
MAC MAC Address = 18:fe:34:6c:f5:97 R/W
CHIP_VERSION Chip version = 0 R/W (0x0)
CHIP_PACKAGE Chip package identifier = 2 R/W (0x2)

Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).


Now, I run these commands and it hangs at Connecting...:

espefuse.py --port /COM4 burn_efuse XPD_SDIO_FORCE 1
espefuse.py v2.1-beta1
Connecting...

espefuse.py --port /COM4 set_flash_voltage 1.8V
espefuse.py v2.1-beta1
Connecting...


Any thoughts? I tried both from the USB power supply I normally flash with and a high-power supply but it still hangs. Reading works fine.

WiFive
Posts: 1017
Joined: Tue Dec 01, 2015 7:35 am

Re: EFUSE read/write VDD_SDIO from user application

Postby WiFive » Thu Sep 14, 2017 5:31 am

Is your esptool up to date with this commit?

https://github.com/espressif/esptool/co ... 40e0b6666e

iosixllc
Posts: 43
Joined: Fri Mar 17, 2017 12:13 am

Re: EFUSE read/write VDD_SDIO from user application

Postby iosixllc » Thu Sep 14, 2017 5:58 am

It was not. I applied that patch and was able to get it to burn as expected - thanks.

espefuse.py --port /COM4 set_flash_voltage 1.8V
espefuse.py v2.1-beta1
Connecting...

Set internal flash voltage regulator (VDD_SDIO) to 1.8V.
The following efuses are burned: XPD_SDIO_FORCE, XPD_SDIO_REG.
It is possible to later increase the voltage to 3.3V (permanently) by burning additional efuse XPD_SDIO_TIEH
This is an irreversible operation.
Type 'BURN' (all capitals) to continue.
BURN
VDD_SDIO setting complete.

espefuse.py --port /COM4 summary
espefuse.py v2.1-beta1
Connecting...
Security fuses:
FLASH_CRYPT_CNT Flash encryption mode counter = 0 R/W (0x0)
FLASH_CRYPT_CONFIG Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE Disable ROM BASIC interpreter fallback = 0 R/W (0x0)
ABS_DONE_0 secure boot enabled for bootloader = 0 R/- (0x0)
ABS_DONE_1 secure boot abstract 1 locked = 0 R/W (0x0)
JTAG_DISABLE Disable JTAG = 0 R/W (0x0)
DISABLE_DL_ENCRYPT Disable flash encryption in UART bootloader = 0 R/W (0x0)
DISABLE_DL_DECRYPT Disable flash decryption in UART bootloader = 0 R/W (0x0)
DISABLE_DL_CACHE Disable flash cache in UART bootloader = 0 R/W (0x0)
BLK1 Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLK2 Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLK3 Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Efuse fuses:
WR_DIS Efuse write disable mask = 4096 R/W (0x1000)
RD_DIS Efuse read disablemask = 0 R/W (0x0)
CODING_SCHEME Efuse variable block length scheme = 0 R/W (0x0)
KEY_STATUS Usage of efuse block 3 (reserved) = 0 R/W (0x0)

Config fuses:
XPD_SDIO_FORCE Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = 1 R/W (0x1)
XPD_SDIO_REG If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = 1 R/W (0x1)
XPD_SDIO_TIEH If XPD_SDIO_FORCE & XPD_SDIO_REG, 1=3.3V 0=1.8V = 0 R/W (0x0)
SPI_PAD_CONFIG_CLK Override SD_CLK pad (GPIO6/SPICLK) = 6 R/W (0x6)
SPI_PAD_CONFIG_Q Override SD_DATA_0 pad (GPIO7/SPIQ) = 17 R/W (0x11)
SPI_PAD_CONFIG_D Override SD_DATA_1 pad (GPIO8/SPID) = 8 R/W (0x8)
SPI_PAD_CONFIG_HD Override SD_DATA_2 pad (GPIO9/SPIHD) = 11 R/W (0xb)
SPI_PAD_CONFIG_CS0 Override SD_CMD pad (GPIO11/SPICS0) = 16 R/W (0x10)
DISABLE_SDIO_HOST Disable SDIO host = 0 R/W (0x0)

Identity fuses:
MAC MAC Address = 18:fe:34:6c:f5:97 R/W
CHIP_VERSION Chip version = 0 R/W (0x0)
CHIP_PACKAGE Chip package identifier = 2 R/W (0x2)

Flash voltage (VDD_SDIO) set to 1.8V by efuse.

make flash
Flashing binaries to serial port /COM4 (app at offset 0x10000)...
esptool.py v2.1-beta1
Connecting......
Chip is ESP32D2WDQ5 (revision 0)
Uploading stub...
Running stub...
Stub running...
Changing baud rate to 2000000
Changed.
Configuring flash size...
Compressed 13808 bytes to 9019...
Wrote 13808 bytes (9019 compressed) at 0x00001000 in 0.1 seconds (effective 1752.4 kbit/s)...
Hash of data verified.
Compressed 654560 bytes to 430951...
Wrote 654560 bytes (430951 compressed) at 0x00010000 in 4.7 seconds (effective 1106.2 kbit/s)...
Hash of data verified.
Compressed 3072 bytes to 106...
Wrote 3072 bytes (106 compressed) at 0x00008000 in 0.0 seconds (effective 1584.4 kbit/s)...
Hash of data verified.

Leaving...
Hard resetting...


However, when I go to boot, I get this on serial console:

E (12) flash_parts: partition 0 invalid magic number 0x10aa
E (12) boot: Failed to verify partition table
E (12) boot: load partition table error!
user code done

iosixllc
Posts: 43
Joined: Fri Mar 17, 2017 12:13 am

Re: EFUSE read/write VDD_SDIO from user application

Postby iosixllc » Thu Sep 14, 2017 6:25 am

I tried the usual recovery steps:

esptool.py --port /COM4 read_flash_status
esptool.py v2.1-beta1
Connecting....
Detecting chip type... ESP32
Chip is ESP32D2WDQ5 (revision 0)
Uploading stub...
Running stub...
Stub running...
Status value: 0xff00
Hard resetting...

esptool.py --port /COM4 flash_id
esptool.py v2.1-beta1
Connecting........_____....._____.
Detecting chip type... ESP32
Chip is ESP32D2WDQ5 (revision 0)
Uploading stub...
Running stub...
Stub running...
Manufacturer: 9d
Device: 7015
Detected flash size: 2MB
Hard resetting...

esptool.py --port /COM4 write_flash_status --non-volatile 0
esptool.py v2.1-beta1
Connecting........_____....._
Detecting chip type... ESP32
Chip is ESP32D2WDQ5 (revision 0)
Uploading stub...
Running stub...
Stub running...
Initial flash status: 0xff00
Setting flash status: 0x0000
After flash status: 0xff00
Hard resetting...

esptool.py --chip esp32 --port /COM4 --baud 2000000 --before default_reset --after hard_reset erase_flash
esptool.py v2.1-beta1
Connecting........
Chip is ESP32D2WDQ5 (revision 0)
Uploading stub...
Running stub...
Stub running...
Changing baud rate to 2000000
Changed.
Erasing flash (this may take a while)...
Chip erase completed successfully in 4.0s
Hard resetting...

make flash
Flashing binaries to serial port /COM4 (app at offset 0x10000)...
esptool.py v2.1-beta1
Connecting.....
Chip is ESP32D2WDQ5 (revision 0)
Uploading stub...
Running stub...
Stub running...
Changing baud rate to 2000000
Changed.
Configuring flash size...
Compressed 13808 bytes to 9019...
Wrote 13808 bytes (9019 compressed) at 0x00001000 in 0.1 seconds (effective 1737.2 kbit/s)...
Hash of data verified.
Compressed 654560 bytes to 430951...
Wrote 654560 bytes (430951 compressed) at 0x00010000 in 4.8 seconds (effective 1102.4 kbit/s)...
Hash of data verified.
Compressed 3072 bytes to 106...
Wrote 3072 bytes (106 compressed) at 0x00008000 in 0.0 seconds (effective 1632.4 kbit/s)...
Hash of data verified.

Leaving...
Hard resetting...


But am still getting:
E (12) flash_parts: partition 0 invalid magic number 0x10aa
E (12) boot: Failed to verify partition table
E (12) boot: load partition table error!
user code done

WiFive
Posts: 1017
Joined: Tue Dec 01, 2015 7:35 am

Re: EFUSE read/write VDD_SDIO from user application

Postby WiFive » Thu Sep 14, 2017 7:23 am

Are your flash settings 40mhz DIO

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