Oh well, I just posted another closely related question on the forums and I can't find it due to it being submitted to approval, because I thought this one had not been posted and I didn't see any notification until after I did it.
I would like the discussion to continue on the other thread, as I go a little bit more specific about my doubts, but on the off chance it's not feasible, my follow up is this:
ESP_Dazz wrote: ↑
Thu Sep 12, 2019 1:45 pm
An 80MHz APB Clock is fed into the entire Timer Group. Each timer then takes 80MHz APB clock and divides it down via the prescaler to a frequency of their own liking. How much the 80MHz clock is divided down by is determined by the value set in the prescaler (i.e. the Divider).
For example, if a timer needs to tick (count up/down) at 800KHz, it would set its divider to 100. Because each timer has it's own prescaler, multiple timers can operate at different frequencies simulatneously.
This seems like some legacy code. Can see that macro being used anywhere else in IDF. But the macro is still correct as it indicates that for a timer to operate at 5MHz, the prescaler for the timer will be 16 (i.e. >> 4).
I guess that clarifies pretty much everything.
Does it mean I can have the timer ticking at 40MHz?
The divider can take be any 16-bit value.
Except 0 (obviously), but also 1. Why can it not be 1? Because of the division operation or some other cost involved in prescaling the clock?