This section only applies if you don't use DMA and choose to fill the FIFO from software. In other words, this is automatic if using DMA.Baldhead wrote: ↑Sun Nov 17, 2019 4:29 amIn "esp32_technical_reference_manual_en.pdf", page 307, says:
When TX_LEN is less than I2S_TX_DATA_NUM[5:0], the transmitted data, which is buffered in FIFO, has not reached the set threshold and
software can continue feeding data into FIFO.
- How does the dma controller know when tx fifo is full ?
- is it automatic or do i need to set something (maybe interrupt) ???
This is a two stage process. DMA will fill the TX FIFO of the I2S peripheral, then I2S peripheral reads the data from the FIFO to write to the LCD.Baldhead wrote: In "esp32_technical_reference_manual_en.pdf", page 119, says:
However, unlike the SPI DMA channels, the data size for a single transfer is one word, or four bytes.
* My data buffer are of type uint16_t.
* The i2s lcd mode are 8 bits parallel.
* The dma data size for a single transfer is one word, or four bytes( uint32_t ).
* The data read/write packet length for a FIFO operation is 32 bits.
If i want to write only one byte or a number of bytes that are not multiple of 4 bytes ?
The DMA stage (or even writing directly into the FIFO from CPU) has restrictions on transfer size. The I2S peripheral will read data from the FIFO based on its configuration, see section "12.4.4 Sending Data" plus the additional "LCD" modes.