Xtensa TIE Extension

StridingDragon
Posts: 13
Joined: Fri Aug 02, 2019 11:59 pm

Xtensa TIE Extension

Postby StridingDragon » Wed Jan 15, 2020 9:54 pm

I've been trying to see if there is a way to use Xtensa TIE Extensions with the ESP32 but it appears there is only the SDK available from Cadence for $1000/year per seat. Considering that virtually everyone tells me the SDK and tool suite is absolute crap, using an outdated compiler, broken tools that keep crashing, and zero support from Cadence, I have no intentions to shell out that kind of money for the tool.

Is there any other way how we can use TIE Extensions to extend the Xtensa instruction set? Custom instructions would really go a long way with the kind of data processing we are doing, which is mostly graphics-based.

Any ideas, pointers or suggestions would be truly welcome.

ESP_igrr
Posts: 1574
Joined: Tue Dec 01, 2015 8:37 am

Re: Xtensa TIE Extension

Postby ESP_igrr » Thu Jan 16, 2020 1:10 am

Hi StridingDragon,

TIEs can be added to an Xtensa processor when the processor is designed. TIEs are implemented with fixed-purpose blocks in silicon. Once the hardware description of the processor is finalized and the chip is produced, it is no longer possible to change anything about the TIEs.

To place this into context, the value proposition of Tensilica was in automating the processor configuration and TIE design flow, with toolchain generation and workload profiling used as a feedback loop. Oftentimes Xtensa cores would be used as auxillary DSPs for specific workloads, and the processor designers would have a pretty good idea what they need to optimize the core for. Tensilica SDK enabled them to profile their workload, identify the hotspots, and then add custom instructions to improve performance; rinse and repeat.

StridingDragon
Posts: 13
Joined: Fri Aug 02, 2019 11:59 pm

Re: Xtensa TIE Extension

Postby StridingDragon » Thu Jan 16, 2020 1:27 am

Ah, I get it. Thank you so much for the clarification.

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