Reduce power consumption in deep sleep on GPIO pads (non-RTC)

guillep2k
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Joined: Tue Feb 12, 2019 8:39 pm

Reduce power consumption in deep sleep on GPIO pads (non-RTC)

Postby guillep2k » Tue Apr 07, 2020 4:11 pm

Hi, guys. Following up on: What is the state of a digital IO in deep sleep. E.g. GPIO17

My question

I have pins on my ESP32-WROOM-32 that are connected to external signals (IO16, IO17) and do not have RTC capability. The signals on those pins are stable (i.e. have definite logic levels) from external sources (one chip's digital output and an external pull-up). When I enter deep sleep I'd wish to avoid leaking current through any of those pins. What is the best software setting for those pins before entering deep sleep?

Additional question

To expand my question, what's the electrical behavior of the general GPIO pins while the module is in deep sleep state? (i.e., which of the following is true):

- Not connected?: any signal between 0-3.3V, either valid or invalid logical level, will cause no harm or extra power draw.
- Connected, high-Z?: any signal between 0-3.3V, either valid or invalid logical level, will cause no harm, but may draw extra power if the logic level is indeterminate.
- Connected, internal pull-down?: any current source connected to the pin will leak current into the pull-down.
- Connected, internal pull-up?: any current sync connected to the pin will leak current from the pull-up.

Note: my question is aimed to acquire better knowledge of the internals of the chip; I'm not looking for suggestions about changing the design (in this case I have no control over it, it's an already produced board :roll:).

Thanks in advance!

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