where the xtensa CPU vector entry point address definition ?

caozilong
Posts: 4
Joined: Mon Feb 15, 2021 6:29 am

where the xtensa CPU vector entry point address definition ?

Postby caozilong » Mon Feb 22, 2021 8:33 am

i meet a crash in the point of "_WindowOverflow4", i try to find the XEA2 xtensa exception entry definition from the xtensa spec, but cant found the exception vector entry defition like other ISA like arm (0xffff0000) and mips(0xbfc000000) etc
so, any body can tell me how the xtensa cores exception vector definition?
thank you!

ESP_Sprite
Posts: 4426
Joined: Thu Nov 26, 2015 4:08 am

Re: where the xtensa CPU vector entry point address definition ?

Postby ESP_Sprite » Tue Feb 23, 2021 4:15 am

Xtensa has a CSR called VECBASE to indicate the position of these. However, if you have a crash in the WindowOverflow4 interrupt, there'sa high likelyhood you're doing something terribly wrong with stack memory. (Alternatively, you're doing something wrong with high-level interrupts.)

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