Increase 'F_digi_con' to increase ADC DMA sampling rate?
Posted: Tue May 17, 2022 10:08 am
The documentation for the ESP32-S3 mentions the ADC continuous (DMA) sampling rate is defined as ('F_digi_con' / 2) / delay_count. With a minimum delay of 30 and a clock of 5MHz this results in max 83kHz sampling rate.
Is this sampling rate independent of the amount of ADCs and/or channels in use?
Can F_digi_con be increased to further increase sampling rate (at reduced performance)?
Is this sampling rate independent of the amount of ADCs and/or channels in use?
Can F_digi_con be increased to further increase sampling rate (at reduced performance)?