ESP32-D2WD set GPIO17-U2TXD output 1

PaulShaw
Posts: 13
Joined: Tue Apr 24, 2018 8:54 am

ESP32-D2WD set GPIO17-U2TXD output 1

Postby PaulShaw » Thu May 10, 2018 7:02 am

hi.

I set GPIO17 output 1,ESP32-D2WD doesn't work,but it works on ESP32-D0WD and ESP32-S0WD.
It works when I comment out the code for config GPIO17.
code:
int sleep_time_ms = (now.tv_sec) * 1000 + (now.tv_usec) / 1000;

printf("11 time display %d %d\r\n",sleep_time_ms/1000,sleep_time_ms);
gpio_pad_select_gpio(U2TXD);
gpio_set_direction(U2TXD, GPIO_MODE_OUTPUT);
gpio_set_level(U2TXD, 1);
gpio_pad_select_gpio(U2RXD);
gpio_set_direction(U2RXD, GPIO_MODE_OUTPUT);
gpio_set_level(U2RXD, 1);
printf("time display %d %d\r\n",sleep_time_ms/1000,sleep_time_ms);

ESP32-D2WD log:
[0;32mI (21) boot: compile time 17:03:12[0m
[0;32mI (22) boot: Enabling RNG early entropy source...[0m
[0;32mI (38) boot: SPI Speed : 20MHz[0m
[0;32mI (51) boot: SPI Mode : DOUT[0m
[0;32mI (63) boot: SPI Flash Size : 2MB[0m
[0;32mI (76) boot: Partition Table:[0m
[0;32mI (87) boot: ## Label Usage Type ST Offset Length[0m
[0;32mI (109) boot: 0 nvs WiFi data 01 02 00009000 00006000[0m
[0;32mI (132) boot: 1 phy_init RF data 01 01 0000f000 00001000[0m
[0;32mI (156) boot: 2 factory factory app 00 00 00010000 00100000[0m
[0;32mI (179) boot: End of partition table[0m
[0;32mI (192) boot: bs.factory.offset = 0x10000..................., selected_subtype = 0x0, app_count = 0x0, bs.ota_info.offset = 0x0
[0m
[0;32mI (230) boot: Disabling RNG early entropy source...[0m
[0;32mI (247) boot: Loading app partition at offset 00010000[0m
[0;32mI (896) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512) [0m
[0;32mI (897) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x08efc ( 36604) map[0m
[0;32mI (913) boot: segment 2: paddr=0x00028f0c vaddr=0x3ffb0000 size=0x01c8c ( 7308) load[0m
[0;32mI (946) boot: segment 3: paddr=0x0002aba0 vaddr=0x40080000 size=0x00400 ( 1024) load[0m
[0;32mI (967) boot: segment 4: paddr=0x0002afa8 vaddr=0x40080400 size=0x08be8 ( 35816) load[0m
[0;32mI (1025) boot: segment 5: paddr=0x00033b98 vaddr=0x400c0000 size=0x00064 ( 100) load[0m
[0;32mI (1026) boot: segment 6: paddr=0x00033c04 vaddr=0x00000000 size=0x0c404 ( 50180) [0m
[0;32mI (1044) boot: segment 7: paddr=0x00040010 vaddr=0x400d0018 size=0x23950 (145744) map[0m
[0;32mI (1070) cpu_start: Pro cpu up.[0m
[0;32mI (1081) cpu_start: Starting app cpu, entry point is 0x40080de0[0m
[0;32mI (0) cpu_start: App cpu up.[0m
[0;32mI (1114) heap_alloc_caps: Initializing. RAM available for dynamic allocation:[0m
[0;32mI (1136) heap_alloc_caps: At 3FFAE2A0 len 00001D60 (7 KiB): DRAM[0m
[0;32mI (1157) heap_alloc_caps: At 3FFB2878 len 0002D788 (181 KiB): DRAM[0m
[0;32mI (1178) heap_alloc_caps: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM[0m
[0;32mI (1199) heap_alloc_caps: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM[0m
[0;32mI (1221) heap_alloc_caps: At 40088FE8 len 00017018 (92 KiB): IRAM[0m
[0;32mI (1242) cpu_start: Pro cpu start user code[0m
[0;32mI (1309) cpu_start: Starting scheduler on PRO CPU.[0m
[0;32mI (216) cpu_start: Starting scheduler on APP CPU.[0m
11 time display 0 7

Guru Meditation Error of type IllegalInstruction occurred on core 0. Exception was unhandled.
Register dump:
PC : 0x4042fdea PS : 0x00050b30 A0 : 0x400ef8cf A1 : 0x3ffc1d10
A2 : 0x00000011 A3 : 0x00000002 A4 : 0x403da893 A5 : 0x3ffc2cc0
A6 : 0x3ffb1308 A7 : 0x00060020 A8 : 0x00020000 A9 : 0x3ff44000
A10 : 0x3ffae3c0 A11 : 0x3ffae3c0 A12 : 0x00000001 A13 : 0x3ffc19f0
A14 : 0x3ffc19f0 A15 : 0x00000002 SAR : 0x0000000f EXCCAUSE: 0x00000000
EXCVADDR: 0x00000000 LBEG : 0x400014fd LEND : 0x4000150d LCOUNT : 0xffffffff

Backtrace: 0x4042fdea:0x3ffc1d10 0x400ef8cc:0x3ffc1d40 0x400d12e2:0x3ffc1d90

Rebooting...

ESP32-D0WD log:
[0;32mI (49) boot: compile time 17:03:12[0m
[0;32mI (84) boot: Enabling RNG early entropy source...[0m
[0;32mI (85) boot: SPI Speed : 20MHz[0m
[0;32mI (85) boot: SPI Mode : DOUT[0m
[0;32mI (94) boot: SPI Flash Size : 16MB[0m
[0;32mI (107) boot: Partition Table:[0m
[0;32mI (118) boot: ## Label Usage Type ST Offset Length[0m
[0;32mI (141) boot: 0 nvs WiFi data 01 02 00009000 00006000[0m
[0;32mI (164) boot: 1 phy_init RF data 01 01 0000f000 00001000[0m
[0;32mI (187) boot: 2 factory factory app 00 00 00010000 00100000[0m
[0;32mI (211) boot: End of partition table[0m
[0;32mI (224) boot: bs.factory.offset = 0x10000..................., selected_subtype = 0x0, app_count = 0x0, bs.ota_info.offset = 0x0
[0m
[0;32mI (262) boot: Disabling RNG early entropy source...[0m
[0;32mI (279) boot: Loading app partition at offset 00010000[0m
[0;32mI (928) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512) [0m
[0;32mI (929) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x08efc ( 36604) map[0m
[0;32mI (945) boot: segment 2: paddr=0x00028f0c vaddr=0x3ffb0000 size=0x01c8c ( 7308) load[0m
[0;32mI (977) boot: segment 3: paddr=0x0002aba0 vaddr=0x40080000 size=0x00400 ( 1024) load[0m
[0;32mI (998) boot: segment 4: paddr=0x0002afa8 vaddr=0x40080400 size=0x08be8 ( 35816) load[0m
[0;32mI (1057) boot: segment 5: paddr=0x00033b98 vaddr=0x400c0000 size=0x00064 ( 100) load[0m
[0;32mI (1058) boot: segment 6: paddr=0x00033c04 vaddr=0x00000000 size=0x0c404 ( 50180) [0m
[0;32mI (1075) boot: segment 7: paddr=0x00040010 vaddr=0x400d0018 size=0x23950 (145744) map[0m
[0;32mI (1101) cpu_start: Pro cpu up.[0m
[0;32mI (1113) cpu_start: Starting app cpu, entry point is 0x40080de0[0m
[0;32mI (0) cpu_start: App cpu up.[0m
[0;32mI (1146) heap_alloc_caps: Initializing. RAM available for dynamic allocation:[0m
[0;32mI (1168) heap_alloc_caps: At 3FFAE2A0 len 00001D60 (7 KiB): DRAM[0m
[0;32mI (1189) heap_alloc_caps: At 3FFB2878 len 0002D788 (181 KiB): DRAM[0m
[0;32mI (1210) heap_alloc_caps: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM[0m
[0;32mI (1231) heap_alloc_caps: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM[0m
[0;32mI (1253) heap_alloc_caps: At 40088FE8 len 00017018 (92 KiB): IRAM[0m
[0;32mI (1274) cpu_start: Pro cpu start user code[0m
[0;32mI (1340) cpu_start: Starting scheduler on PRO CPU.[0m
[0;32mI (216) cpu_start: Starting scheduler on APP CPU.[0m
11 time display 0 7

time display 0 7


Any other config different between ESP32-D2WD and ESP32-D0WD,ESP32S0WD?

Thanks in advance for your help!

ESP_Sprite
Posts: 9016
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32-D2WD set GPIO17-U2TXD output 1

Postby ESP_Sprite » Thu May 10, 2018 8:10 am

Datasheet of the ESP32, page 9: "ESP32-D2WD’s pins GPIO16, GPIO17, SD_CMD, SD_CLK, SD_DATA_0 and SD_DATA_1 are used for connecting the embedded flash, and are not recommended for other uses."

PaulShaw
Posts: 13
Joined: Tue Apr 24, 2018 8:54 am

Re: ESP32-D2WD set GPIO17-U2TXD output 1

Postby PaulShaw » Fri May 11, 2018 2:05 am

ESP_Sprite wrote:Datasheet of the ESP32, page 9: "ESP32-D2WD’s pins GPIO16, GPIO17, SD_CMD, SD_CLK, SD_DATA_0 and SD_DATA_1 are used for connecting the embedded flash, and are not recommended for other uses."
I think the flash use "SD_CMD, SD_CLK, SD_DATA_0 and SD_DATA_1",why it used GPIO16 and GPIO17?

ESP_Sprite
Posts: 9016
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32-D2WD set GPIO17-U2TXD output 1

Postby ESP_Sprite » Fri May 11, 2018 3:34 am

Because the internal flash in the D2WD is connected to different pads. It's a physical thing, if I recall correctly; the flash and ESP32 still are two separate dies and are connected using bond wires. However, you cannot make those too long or cross them, so we had to use some slightly different GPIOs for some flash pins.

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