RTC XTAL 32k not working/broken after SW_Reset OR Deepsleep

Post Reply
nevercast
Posts: 7
Joined: Tue Jan 08, 2019 2:58 am

RTC XTAL 32k not working/broken after SW_Reset OR Deepsleep

Postby nevercast » Tue Jan 08, 2019 3:19 am

Hello, I require an external crystal for the RTC because I need accurate deepsleep times over several hours. I have started a project on the esp-idf using Platform.IO, please excuse the poor project layout if it is not esp-idf standard.

What I've done:
1. I have modified the sdkconfig to use the external 32k oscillator for RTC instead of the internal 150k oscillator.
2. I have added some basic calibration code taken from the RTC test file on Github to verify it is oscillating.
3. Added software reset and deepsleep to ensure the crystal still works after a reset.

Expected Behavior:
1. The RTC XTAL is still running after deepsleep or software reset (I expect the RTC crystal to run always)

Observed behavior:
1. The RTC XTAL is not running. Logs give error.

Code used:
app_main.cpp
Code: [Select all] [Expand/Collapse]
  1. #include <stdio.h>
  2. #include "freertos/FreeRTOS.h"
  3. #include "freertos/task.h"
  4. #include "esp_system.h"
  5. #include "rom/rtc.h"
  6.  
  7. // Include private libraries.
  8. #include <Xtal_RTC.h>
  9.  
  10. #define CPU_PRO 0
  11. #define CPU_APP 1
  12.  
  13. RESET_REASON reset_reason;
  14.  
  15. void app_restart(void* context) {
  16.     printf("(app_restart) waiting 5 seconds...\n");
  17.     vTaskDelay(5000 / portTICK_RATE_MS);
  18.  
  19.     if (reset_reason == DEEPSLEEP_RESET) {
  20.         printf("(app_restart) immediate restart...\n");
  21.         esp_restart();
  22.     } else {
  23.         printf("(app_restart) deepsleep for 3 seconds...\n");
  24.         esp_sleep_enable_timer_wakeup(1000L * 3000L); // 3 seconds
  25.         esp_deep_sleep_start();
  26.     }
  27.  
  28. }
  29.  
  30. extern "C" void app_main(void) {
  31.     reset_reason = rtc_get_reset_reason(CPU_PRO);
  32.     printf("(app_main) Reset Reason: %u\n", (uint32_t)reset_reason);
  33.     calibrate_slow_clk();
  34.     printf("(app_main) Initialized.\n");
  35.     uint32_t random = esp_random();
  36.     printf("(app_main) Random Gen: %u\n", random);
  37.     xTaskCreate( app_restart, "app_restart", 2048, 0, 9, NULL );
  38. }
GeSHi © Codebox Plus Extension
Xtal_RTC.c
Code: [Select all] [Expand/Collapse]
  1. #include <stdio.h>
  2. #include "rom/ets_sys.h"
  3. #include "rom/uart.h"
  4. #include "soc/rtc.h"
  5. #include "soc/rtc_cntl_reg.h"
  6. #include "soc/rtc_io_reg.h"
  7. #include "soc/sens_reg.h"
  8. #include "soc/io_mux_reg.h"
  9. #include "driver/rtc_io.h"
  10. #include "freertos/FreeRTOS.h"
  11. #include "freertos/task.h"
  12. #include "freertos/semphr.h"
  13. #include "../esp_clk_internal.h"
  14. #include "esp_clk.h"
  15.  
  16. #include <Xtal_RTC.h>
  17.  
  18. #define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk)
  19. static uint32_t calibrate_one(rtc_cal_sel_t cal_clk, const char* name)
  20. {
  21.     const uint32_t cal_count = 1000;
  22.     const float factor = (1 << 19) * 1000.0f;
  23.     uint32_t cali_val;
  24.     printf("%s:\n", name);
  25.     for (int i = 0; i < 5; ++i) {
  26.         printf("calibrate (%d): ", i);
  27.         cali_val = rtc_clk_cal(cal_clk, cal_count);
  28.         printf("%.3f kHz\n", factor / (float) cali_val);
  29.     }
  30.     return cali_val;
  31. }
  32.  
  33. static void pull_out_clk(int sel)
  34. {
  35.     REG_SET_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M);
  36.     REG_CLR_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_RDE_M | RTC_IO_PDAC1_RUE_M);
  37.     REG_SET_FIELD(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_FUN_SEL, 1);
  38.     REG_SET_FIELD(SENS_SAR_DAC_CTRL1_REG, SENS_DEBUG_BIT_SEL, 0);
  39.     REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel);
  40. }
  41.  
  42. void calibrate_slow_clk(void) {
  43.     rtc_clk_32k_enable(true);
  44.  
  45.     uint32_t cal_32k = CALIBRATE_ONE(RTC_CAL_32K_XTAL);
  46.  
  47.     if (cal_32k == 0) {
  48.         printf("32K XTAL OSC has not started up\n");
  49.     } else {
  50.         printf("switching to RTC_SLOW_FREQ_32K_XTAL: ");
  51.         rtc_clk_slow_freq_set(RTC_SLOW_FREQ_32K_XTAL);
  52.         printf("done\n");
  53.         CALIBRATE_ONE(RTC_CAL_RTC_MUX);
  54.     }
  55.  
  56.     CALIBRATE_ONE(RTC_CAL_32K_XTAL);
  57.  
  58.     pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL);
  59. }
GeSHi © Codebox Plus Extension
Program expected behavior:
1. After reset the ESP32 should start, and calibrate the slow clock, showing 32k oscillations.
2. After 3 seconds, it will enter deepsleep for 3 seconds.
3. After wake from deepsleep, it will calibrate the slow clock, showing 32k oscillations.
4. After 3 seconds it will software reset, and repeat from 1.

Observed:
1. The program correctly alternates between deepsleep and software reset.
2. The oscillator doesn't work after a soft reset
3. The oscillator seems to work after a hard reset (Reset button on board)

ESP32 UART Output:
Code: [Select all] [Expand/Collapse]
  1. rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  2. flash read err, 1000
  3. ets_main.c 371
  4. ets Jun  8 2016 00:22:57
  5.  
  6. rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  7. configsip: 0, SPIWP:0xee
  8. clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  9. mode:DIO, clock div:2
  10. load:0x3fff0018,len:4
  11. load:0x3fff001c,len:4960
  12. ho 0 tail 12 room 4
  13. load:0x40078000,len:7768
  14. ho 0 tail 12 room 4
  15. load:0x40080000,len:6084
  16. entry 0x40080324
  17. I (32) boot: ESP-IDF 3.30101.0 2nd stage bootloader
  18. I (32) boot: compile time 12:59:10
  19. I (32) boot: Enabling RNG early entropy source...
  20. I (34) boot: SPI Speed      : 40MHz
  21. I (37) boot: SPI Mode       : DIO
  22. I (40) boot: SPI Flash Size : 4MB
  23. I (43) boot: Partition Table:
  24. I (46) boot: ## Label            Usage          Type ST Offset   Length
  25. I (52) boot:  0 nvs              WiFi data        01 02 00009000 00006000
  26. I (59) boot:  1 phy_init         RF data          01 01 0000f000 00001000
  27. I (65) boot:  2 factory          factory app      00 00 00010000 00100000
  28. I (72) boot: End of partition table
  29. I (75) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x05448 ( 21576) map
  30. I (91) esp_image: segment 1: paddr=0x00015470 vaddr=0x3ffc0000 size=0x01fe0 (  8160) load
  31. I (94) esp_image: segment 2: paddr=0x00017458 vaddr=0x3ffc1fe0 size=0x00000 (     0) load
  32. I (99) esp_image: segment 3: paddr=0x00017460 vaddr=0x40080000 size=0x00400 (  1024) load
  33. I (107) esp_image: segment 4: paddr=0x00017868 vaddr=0x40080400 size=0x08510 ( 34064) load
  34. I (128) esp_image: segment 5: paddr=0x0001fd80 vaddr=0x400c0000 size=0x00064 (   100) load
  35. I (129) esp_image: segment 6: paddr=0x0001fdec vaddr=0x50000000 size=0x00000 (     0) load
  36. I (133) esp_image: segment 7: paddr=0x0001fdf4 vaddr=0x00000000 size=0x0021c (   540)
  37. I (141) esp_image: segment 8: paddr=0x00020018 vaddr=0x400d0018 size=0x10c20 ( 68640) map
  38. I (178) boot: Loaded app from partition at offset 0x10000
  39. I (178) boot: Disabling RNG early entropy source...
  40. I (178) cpu_start: Pro cpu up.
  41. I (179) cpu_start: Starting app cpu, entry point is 0x40080f8c
  42. I (0) cpu_start: App cpu up.
  43. I (188) heap_init: Initializing. RAM available for dynamic allocation:
  44. I (194) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
  45. I (199) heap_init: At 3FFC3040 len 0001CFC0 (115 KiB): DRAM
  46. I (204) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
  47. I (210) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
  48. I (215) heap_init: At 40088910 len 000176F0 (93 KiB): IRAM
  49. I (220) cpu_start: Pro cpu start user code
  50. I (79) cpu_start: Starting scheduler on PRO CPU.
  51. I (0) cpu_start: Starting scheduler on APP CPU.
  52. (app_main) Reset Reason: 16
  53. RTC_CAL_32K_XTAL:
  54. calibrate (0): 31.998 kHz
  55. calibrate (1): 31.999 kHz
  56. calibrate (2): 31.998 kHz
  57. calibrate (3): 31.999 kHz
  58. calibrate (4): 31.998 kHz
  59. switching to RTC_SLOW_FREQ_32K_XTAL: done
  60. RTC_CAL_RTC_MUX:
  61. calibrate (0): 31.999 kHz
  62. calibrate (1): 31.998 kHz
  63. calibrate (2): 31.998 kHz
  64. calibrate (3): 31.999 kHz
  65. calibrate (4): 31.998 kHz
  66. RTC_CAL_32K_XTAL:
  67. calibrate (0): 31.999 kHz
  68. calibrate (1): 31.998 kHz
  69. calibrate (2): 31.999 kHz
  70. calibrate (3): 31.998 kHz
  71. calibrate (4): 31.998 kHz
  72. (app_main) Initialized.
  73. (app_main) Random Gen: 2955304622
  74. (app_restart) waiting 5 seconds...
  75. (app_restart) deepsleep for 3 seconds...
  76. ets Jun  8 2016 00:22:57
  77.  
  78. rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  79. configsip: 0, SPIWP:0xee
  80. clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  81. mode:DIO, clock div:2
  82. load:0x3fff0018,len:4
  83. load:0x3fff001c,len:4960
  84. ho 0 tail 12 room 4
  85. load:0x40078000,len:7768
  86. ho 0 tail 12 room 4
  87. load:0x40080000,len:6084
  88. entry 0x40080324
  89. I (33) boot: ESP-IDF 3.30101.0 2nd stage bootloader
  90. I (33) boot: compile time 12:59:10
  91. I (33) boot: Enabling RNG early entropy source...
  92. I (35) boot: SPI Speed      : 40MHz
  93. I (38) boot: SPI Mode       : DIO
  94. I (41) boot: SPI Flash Size : 4MB
  95. I (44) boot: Partition Table:
  96. I (47) boot: ## Label            Usage          Type ST Offset   Length
  97. I (53) boot:  0 nvs              WiFi data        01 02 00009000 00006000
  98. I (60) boot:  1 phy_init         RF data          01 01 0000f000 00001000
  99. I (66) boot:  2 factory          factory app      00 00 00010000 00100000
  100. I (73) boot: End of partition table
  101. I (76) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x05448 ( 21576) map
  102. I (91) esp_image: segment 1: paddr=0x00015470 vaddr=0x3ffc0000 size=0x01fe0 (  8160) load
  103. I (95) esp_image: segment 2: paddr=0x00017458 vaddr=0x3ffc1fe0 size=0x00000 (     0) load
  104. I (100) esp_image: segment 3: paddr=0x00017460 vaddr=0x40080000 size=0x00400 (  1024) load
  105. I (108) esp_image: segment 4: paddr=0x00017868 vaddr=0x40080400 size=0x08510 ( 34064) load
  106. I (129) esp_image: segment 5: paddr=0x0001fd80 vaddr=0x400c0000 size=0x00064 (   100)
  107. I (130) esp_image: segment 6: paddr=0x0001fdec vaddr=0x50000000 size=0x00000 (     0)
  108. I (133) esp_image: segment 7: paddr=0x0001fdf4 vaddr=0x00000000 size=0x0021c (   540)
  109. I (141) esp_image: segment 8: paddr=0x00020018 vaddr=0x400d0018 size=0x10c20 ( 68640) map
  110. I (178) boot: Loaded app from partition at offset 0x10000
  111. I (179) boot: Disabling RNG early entropy source...
  112. I (179) cpu_start: Pro cpu up.
  113. I (180) cpu_start: Starting app cpu, entry point is 0x40080f8c
  114. I (0) cpu_start: App cpu up.
  115. I (188) heap_init: Initializing. RAM available for dynamic allocation:
  116. I (194) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
  117. I (199) heap_init: At 3FFC3040 len 0001CFC0 (115 KiB): DRAM
  118. I (205) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
  119. I (210) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
  120. I (215) heap_init: At 40088910 len 000176F0 (93 KiB): IRAM
  121. I (221) cpu_start: Pro cpu start user code
  122. E (474) clk: RTC: Not found External 32 kHz XTAL. Switching to Internal 150 kHz RC chain
  123. I (161) cpu_start: Starting scheduler on PRO CPU.
  124. I (0) cpu_start: Starting scheduler on APP CPU.
  125. (app_main) Reset Reason: 5
  126. RTC_CAL_32K_XTAL:
  127. calibrate (0): inf kHz
  128. calibrate (1): inf kHz
  129. calibrate (2): inf kHz
  130. calibrate (3): inf kHz
  131. calibrate (4): inf kHz
  132. 32K XTAL OSC has not started up
  133. RTC_CAL_32K_XTAL:
  134. calibrate (0): inf kHz
  135. calibrate (1): inf kHz
  136. calibrate (2): inf kHz
  137. calibrate (3): inf kHz
  138. calibrate (4): inf kHz
  139. (app_main) Initialized.
  140. (app_main) Random Gen: 405345985
  141. (app_restart) waiting 5 seconds...
  142. (app_restart) immediate restart...
  143. ets Jun  8 2016 00:22:57
  144.  
  145. rst:0xc (SW_CPU_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  146. configsip: 0, SPIWP:0xee
  147. clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  148. mode:DIO, clock div:2
  149. load:0x3fff0018,len:4
  150. load:0x3fff001c,len:4960
  151. ho 0 tail 12 room 4
  152. load:0x40078000,len:7768
  153. ho 0 tail 12 room 4
  154. load:0x40080000,len:6084
  155. entry 0x40080324
  156. I (32) boot: ESP-IDF 3.30101.0 2nd stage bootloader
  157. I (32) boot: compile time 12:59:10
  158. I (32) boot: Enabling RNG early entropy source...
  159. I (35) boot: SPI Speed      : 40MHz
  160. I (38) boot: SPI Mode       : DIO
  161. I (41) boot: SPI Flash Size : 4MB
  162. I (44) boot: Partition Table:
  163. I (47) boot: ## Label            Usage          Type ST Offset   Length
  164. I (53) boot:  0 nvs              WiFi data        01 02 00009000 00006000
  165. I (59) boot:  1 phy_init         RF data          01 01 0000f000 00001000
  166. I (66) boot:  2 factory          factory app      00 00 00010000 00100000
  167. I (72) boot: End of partition table
  168. I (76) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x05448 ( 21576) map
  169. I (91) esp_image: segment 1: paddr=0x00015470 vaddr=0x3ffc0000 size=0x01fe0 (  8160) load
  170. I (95) esp_image: segment 2: paddr=0x00017458 vaddr=0x3ffc1fe0 size=0x00000 (     0) load
  171. I (99) esp_image: segment 3: paddr=0x00017460 vaddr=0x40080000 size=0x00400 (  1024) load
  172. I (108) esp_image: segment 4: paddr=0x00017868 vaddr=0x40080400 size=0x08510 ( 34064) load
  173. I (129) esp_image: segment 5: paddr=0x0001fd80 vaddr=0x400c0000 size=0x00064 (   100) load
  174. I (129) esp_image: segment 6: paddr=0x0001fdec vaddr=0x50000000 size=0x00000 (     0) load
  175. I (134) esp_image: segment 7: paddr=0x0001fdf4 vaddr=0x00000000 size=0x0021c (   540)
  176. I (142) esp_image: segment 8: paddr=0x00020018 vaddr=0x400d0018 size=0x10c20 ( 68640) map
  177. I (179) boot: Loaded app from partition at offset 0x10000
  178. I (179) boot: Disabling RNG early entropy source...
  179. I (179) cpu_start: Pro cpu up.
  180. I (180) cpu_start: Starting app cpu, entry point is 0x40080f8c
  181. I (170) cpu_start: App cpu up.
  182. I (189) heap_init: Initializing. RAM available for dynamic allocation:
  183. I (195) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
  184. I (200) heap_init: At 3FFC3040 len 0001CFC0 (115 KiB): DRAM
  185. I (205) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
  186. I (210) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
  187. I (216) heap_init: At 40088910 len 000176F0 (93 KiB): IRAM
  188. I (221) cpu_start: Pro cpu start user code
  189. E (475) clk: RTC: Not found External 32 kHz XTAL. Switching to Internal 150 kHz RC chain
  190. I (161) cpu_start: Starting scheduler on PRO CPU.
  191. I (0) cpu_start: Starting scheduler on APP CPU.
  192. (app_main) Reset Reason: 12
  193. RTC_CAL_32K_XTAL:
  194. calibrate (0): inf kHz
  195. calibrate (1): inf kHz
  196. calibrate (2): inf kHz
  197. calibrate (3): inf kHz
  198. calibrate (4): inf kHz
  199. 32K XTAL OSC has not started up
  200. RTC_CAL_32K_XTAL:
  201. calibrate (0): inf kHz
  202. calibrate (1): inf kHz
  203. calibrate (2): inf kHz
  204. calibrate (3): inf kHz
  205. calibrate (4): inf kHz
  206. (app_main) Initialized.
  207. (app_main) Random Gen: 4108722250
  208. (app_restart) waiting 5 seconds...
GeSHi © Codebox Plus Extension

sdkconfig.h diff
Code: [Select all] [Expand/Collapse]
  1. - #define CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC 1
  2. + #define CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL 1
  3.  
  4. - #define CONFIG_ESP32_RTC_CLK_CAL_CYCLES 1024
  5. + #define CONFIG_ESP32_RTC_CLK_CAL_CYCLES 300
  6. + #define CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES 5
  7.  
  8. - #define CONFIG_LOG_COLORS 1
  9. + #define CONFIG_LOG_COLORS 0
GeSHi © Codebox Plus Extension
Please let me know if I can provide more information.
Kind regards, Josh.

Edit 1
I should add that yes I do have loading capacitors on my crystal, the crystal is also 32000Hz instead of 32768Hz, I will have the correct part shortly but for now I don't see any issue using a badly clocked crystal since I only want to ensure its always running, the frequency is irrelevant at this point.
Top
Post Reply

Return to “ESP-IDF”

Who is online

Users browsing this forum: Majestic-12 [Bot] and 246 guests