I²C clock problem

persan666
Posts: 20
Joined: Fri Feb 16, 2018 9:17 am

I²C clock problem

Postby persan666 » Fri Jan 18, 2019 10:09 am

I have some problems with I²2 when I communicating with a battery gauge-IC BQ35100. I am using a ESP-Wroom-32D with ESP-IDF 3.2
If I set the I²2 clock frequency to 100KHz or 400KHz I will get I²C timeouts all the time when reading.
What I have seen is that the clock is not consistent and varies during a single byte transfer and it does not look like a slave clock stretch. The application is only doing this and i have also tried running the I²C communication in a separate task on different cores.
Here is a recording with a logic analyzer with 100KHz clock. The marking circle to the right shows a strange behavior. The clock is 893KHz! See the the zoomed in picture below.
If I use 10KHz as I²C clock it work most of the time.
External pull-ups is used. Tried with both 10K and 2.2KOhm. Henceforth I will use 2.2KOhm because the BQ35100 requires maximum rise time of 300ns.
clock inconsistant2.PNG
clock inconsistant2.PNG (82.83 KiB) Viewed 2923 times
i2c 893KHz.png
i2c 893KHz.png (52.37 KiB) Viewed 2923 times
My reading routine is as follow:

Code: Select all

esp_err_t i2c_master_read_slave(i2c_port_t i2c_num, uint8_t slave_address, uint8_t register_address, uint8_t* data_rd, size_t size)
{
    i2c_cmd_handle_t cmd = i2c_cmd_link_create();
    i2c_master_start(cmd);
    if (register_address!= -1) {
        i2c_master_write_byte(cmd, slave_address << 1 | I2C_MASTER_WRITE, I2C_ACK_CHECK_EN);
        i2c_master_write_byte(cmd, register_address, I2C_ACK_CHECK_EN);
        i2c_master_start(cmd);
    }
    i2c_master_write_byte(cmd, slave_address << 1 | I2C_READ_BIT, I2C_ACK_CHECK_EN);
    if (size > 1) {
        i2c_master_read(cmd, data_rd, size - 1, I2C_ACK_VAL);
    }
    i2c_master_read_byte(cmd, data_rd + size - 1, I2C_NACK_VAL);
    i2c_master_stop(cmd);
    esp_err_t ret = i2c_master_cmd_begin(i2c_num, cmd, 100000 / portTICK_RATE_MS);
    i2c_cmd_link_delete(cmd);

    if(ret != ESP_OK)
    	ESP_LOGE(TAG, "i2c error: %s", esp_err_to_name(ret));

    return ret;
}

ESP_houwenxiang
Posts: 118
Joined: Tue Jun 26, 2018 3:09 am

Re: I²C clock problem

Postby ESP_houwenxiang » Sun Jan 20, 2019 4:12 am

Hi, persan666
It seems that your I2C bus is broken. When the driver detects a timeout event, it clears the I2C bus. Also, your IDF version is a bit old, we updated the I2C driver 1 month ago, please try the latest version. By the way, I want to know the following informations:

1. If the hardware filter of I2C is enabled? if not, the latest version have enabled this feature by default, you can have a try.
2. How many slaves are in you I2C bus?
3. Whether there is a 3.3v - 5V level matching circuit?
4. Whether there is a large capacitance on the I2C bus?

thanks !!
wookooho

persan666
Posts: 20
Joined: Fri Feb 16, 2018 9:17 am

Re: I²C clock problem

Postby persan666 » Mon Jan 21, 2019 8:29 am

ESP_houwenxiang wrote:
Sun Jan 20, 2019 4:12 am
Hi, persan666
It seems that your I2C bus is broken. When the driver detects a timeout event, it clears the I2C bus. Also, your IDF version is a bit old, we updated the I2C driver 1 month ago, please try the latest version. By the way, I want to know the following informations:

1. If the hardware filter of I2C is enabled? if not, the latest version have enabled this feature by default, you can have a try.
2. How many slaves are in you I2C bus?
3. Whether there is a 3.3v - 5V level matching circuit?
4. Whether there is a large capacitance on the I2C bus?

thanks !!
Thanks for your reply!

1. What version of IDF do you prefer? Isn't the 3.2 version the latest released? Commit: bed50a93f
2. Only one!
3. All circuits use 3.3V
4. No capacitors, The IC is connected directly to the ESP (3cm apart) with pull-ups .

ESP_houwenxiang
Posts: 118
Joined: Tue Jun 26, 2018 3:09 am

Re: I²C clock problem

Postby ESP_houwenxiang » Mon Jan 21, 2019 10:04 am

Hi,
Just found that the I2C driver in release / v3.2 is not up to date. Can you help try the master branch?
wookooho

persan666
Posts: 20
Joined: Fri Feb 16, 2018 9:17 am

Re: I²C clock problem

Postby persan666 » Mon Jan 21, 2019 10:35 am

ESP_houwenxiang wrote:
Mon Jan 21, 2019 10:04 am
Hi,
Just found that the I2C driver in release / v3.2 is not up to date. Can you help try the master branch?
OK!
Which tag should I use? or latest and greatest?

persan666
Posts: 20
Joined: Fri Feb 16, 2018 9:17 am

Re: I²C clock problem

Postby persan666 » Mon Jan 21, 2019 2:39 pm

ESP_houwenxiang wrote:
Mon Jan 21, 2019 10:04 am
Hi,
Just found that the I2C driver in release / v3.2 is not up to date. Can you help try the master branch?
I have now tested with the master branch but with similar results. See recording below.
i2c 100kHz master branch.png
i2c 100kHz master branch.png (89.54 KiB) Viewed 2808 times
And when changing the I²C clock frequency to 10KHz its working. see recording below.
i2c 10kHz master branch.png
i2c 10kHz master branch.png (82.99 KiB) Viewed 2808 times
Thanks in advance!

ESP_houwenxiang
Posts: 118
Joined: Tue Jun 26, 2018 3:09 am

Re: I²C clock problem

Postby ESP_houwenxiang » Tue Jan 22, 2019 6:55 am

Hi, @persan666
Thanks for you feedback, from the picture we know that the timing is abnormal. Can you help with another test?
in i2c.c, please find the function ` i2c_master_clear_bus` and change it to:
```
static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
{
return ESP_OK;
}
```

I want to know if the clock is stable, thanks !!
wookooho

persan666
Posts: 20
Joined: Fri Feb 16, 2018 9:17 am

Re: I²C clock problem

Postby persan666 » Wed Jan 23, 2019 4:38 pm

ESP_houwenxiang wrote:
Tue Jan 22, 2019 6:55 am
Hi, @persan666
Thanks for you feedback, from the picture we know that the timing is abnormal. Can you help with another test?
in i2c.c, please find the function ` i2c_master_clear_bus` and change it to:
```
static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
{
return ESP_OK;
}
```

I want to know if the clock is stable, thanks !!
Thank you for your reply!
I have done some recordings with the suggested change. See below

10KHz (still working)
i2c_master_clear_bus changed 10KHz.png
i2c_master_clear_bus changed 10KHz.png (81.71 KiB) Viewed 2715 times
100KHz (not working)
i2c_master_clear_bus changed 100KHz.png
i2c_master_clear_bus changed 100KHz.png (73.74 KiB) Viewed 2715 times

ESP_houwenxiang
Posts: 118
Joined: Tue Jun 26, 2018 3:09 am

Re: I²C clock problem

Postby ESP_houwenxiang » Thu Jan 24, 2019 11:39 am

Hi,
Why the SCL frequency changes during data transmission? :?:
wookooho

persan666
Posts: 20
Joined: Fri Feb 16, 2018 9:17 am

Re: I²C clock problem

Postby persan666 » Thu Jan 24, 2019 3:26 pm

ESP_houwenxiang wrote:
Thu Jan 24, 2019 11:39 am
Hi,
Why the SCL frequency changes during data transmission? :?:
I also wonders why this is so. It could not be the slave that doing clock stretching because then the positive clock level should be shorter than the low level?

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