5 posts • Page 1 of 1
The LED PWM module cannot be used to generate the MCLK required for I2S. MCLK requires at a rate of 64x to 256x of the sampling rate. The max. frequency that can be generated by this module is 78.125KHz (= 80MHz / 1024), so, don't try to make use of it. I want to take a look at PWM0~3 modules for generating the MCLK, but there is no information about them.
That's not entirely true. The hardware happily supports a divider of e.g. 2, leading to a 40MHz signal. The driver actually also supports this, but not in an obvious way: the led_timer_bit_t structure you use to select the depth only has 10 to 15-bit options. However, if instead you feed a literal '1' into the setup function instead of one of the enum values, it should work just fine to give you an 1-bit counter. The same goes for any other literal number in the 1-20 range. I'm not sure why we did not include the other bit options as well, to be honest.
Who is online
Users browsing this forum: pathob and 16 guests