However, now we are implementing an RDM responder and must transmit as well as receive data.
We observe the following unexpected sequence of events:
1. configure uart to generate brk_det and rxfifo_full interrupts
2. the interrupts are generated and we receive messages prefaced by break.
3. load some data in tx_fifo. it is transmitted normally.
4. we continue to receive messages prefaced by break.
5. reconfigure baud rate of uart in order to send a break.
6. transmit some data
7. configure it back to original value.
8. brk_det interrupts are no longer generated. rxfifo_full interrupts continue normally.
workaround: if we reset the uart entirely with uart_param_config and uart_set_pin, then the brk_det interrupt is again generated.
Furthermore, we also notice that the processor instantly crashes when the following instruction is executed:
Code: Select all
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); UART[uart_num]->int_clr.txfifo_empty = 1; UART[uart_num]->conf1.txfifo_empty_thrhd = 1U; UART[uart_num]->int_ena.txfifo_empty = 1; UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);