ESP32 as a logic analyzer.

Olof Astrand
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Joined: Tue Jan 31, 2017 10:59 am

ESP32 as a logic analyzer.

Postby Olof Astrand » Wed Dec 20, 2017 10:49 am

By using sigrok and implementing the SUMP protocol over serial I was able to use the ESP32 as a logical analyzer.
Quite a nice way to get a better understanding of the streams of bits running over the wires of the ESP32.

https://en.wikipedia.org/wiki/Sigrok


Image

Here is the source.
https://github.com/Ebiroll/esp32_sigrok

Does not yet work with Open Bench Logic sniffer but that will be the next step if this project sparks interest.
https://lxtreme.nl/projects/ols/

Another improvement would be using parallel i2s input with DMA to get a higher and smother sampling rate.

Happy holidays

ESP_Angus
Posts: 1267
Joined: Sun May 08, 2016 4:11 am

Re: ESP32 as a logic analyzer.

Postby ESP_Angus » Wed Dec 20, 2017 11:40 pm

Nice! Sprite & I were actually chatting about this the other day. Will watch this project with interest.

Once you have I2S and DMA is doing the heavy lifting, you may be able to do SUMP over a TCP socket. :)

Olof Astrand
Posts: 16
Joined: Tue Jan 31, 2017 10:59 am

Re: ESP32 as a logic analyzer.

Postby Olof Astrand » Thu Dec 21, 2017 10:19 am

Hello again.

I did some more tests yesterday and it turns out that the reason why it was working so well was because I was using pin 12-15 on the WROVER-KIT. Sigrok was then able to use the JTAG, chip on the WROVER-KIT board for data acquisition.

It was just a coincidence that I used these pins on the WROVER board, and I should have become more suspicious when the code was working on the first try. :D

This is however good news as sigrok was running quite well with this setup, and this is better than having a second ESP32 for data acquisition.

During the holidays I will give it another try and will try to get parallel i2s with DMA transfers running for those who do not have a WROVER-KIT. I think implementing the SUMP protocol is still a good Idea, and getting it to run over Wifi is even better. However the current implementation with alarms to trigger the sampling, does not work.

Best regards,
Olof

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Vader_Mester
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Re: ESP32 as a logic analyzer.

Postby Vader_Mester » Thu Jan 18, 2018 9:27 am

Hi Olof,

Is there a way to something else than the Wrover kit, so with something like the Devkit for example?

I also saw on the Guthub, that the current sample rate is hard coded to 10kHz. For me it seems quite small, or maybe I'm missing something.

Regards,
Ben
There are 2 types of programmer people: The Expert programmer and The Smart programmer

The Expert programmer easily writes any code from scratch.
The Smart programmer uses his google/github powers first ;)

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rudi ;-)
Posts: 1247
Joined: Fri Nov 13, 2015 3:25 pm

Re: ESP32 as a logic analyzer.

Postby rudi ;-) » Mon Jan 22, 2018 9:04 am

Olof Astrand wrote:By using sigrok and implementing the SUMP protocol over serial I was able to use the ESP32 as a logical analyzer.
Quite a nice way to get a better understanding of the streams of bits running over the wires of the ESP32.

https://en.wikipedia.org/wiki/Sigrok


Image

Here is the source.
https://github.com/Ebiroll/esp32_sigrok

Does not yet work with Open Bench Logic sniffer but that will be the next step if this project sparks interest.
https://lxtreme.nl/projects/ols/

Another improvement would be using parallel i2s input with DMA to get a higher and smother sampling rate.

Happy holidays

very nice example! you are welcome!
i did a mini oszilloscope for android and on a wifi port ( like angus spoken )
MVI_9699.gif
MVI_9699.gif (4.95 MiB) Viewed 2641 times

i will try to use your project in my simple doings - very very welcome!
thanks!

best wishes
rudi ;-)
-------------------------------------
love it, change it or leave it.
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問候飛出去的朋友遍全球魯迪

Olof Astrand
Posts: 16
Joined: Tue Jan 31, 2017 10:59 am

Re: ESP32 as a logic analyzer.

Postby Olof Astrand » Wed Jan 31, 2018 9:36 am

Vader_Mester wrote:Hi Olof,

Is there a way to something else than the Wrover kit, so with something like the Devkit for example?

I also saw on the Guthub, that the current sample rate is hard coded to 10kHz. For me it seems quite small, or maybe I'm missing something.

Regards,
Ben
Hello,

Sorry for the late reply. Yes it was hard coded to 10kHz as I used a high performance timer to collect data. I could not get it to run faster with this technique. A much better way to do this is by using DMA and i2s.
It does not require the Wrover kit, but is then limited to 10kHz. The Rigol DS emulation over wifi also is a bit unstable. Most of the times it works but I have a feeling that the huge amounts of interrupts maybe makes the network code drop some packets.

https://twitter.com/ESP32net/status/958438631949111298

Here is another guy, looking to do something similar.
https://github.com/easyvolts/espScope

Regards,
Olof

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