TG0WDT_SYS_RESET and TG1WDT_SYS_RESET

0xffff
Posts: 34
Joined: Tue Jun 19, 2018 1:53 am

TG0WDT_SYS_RESET and TG1WDT_SYS_RESET

Postby 0xffff » Thu Nov 08, 2018 7:49 pm

Hi,

I am running freertos on 2 cpus - at one customer site I see occasional errors such as the following, sometimes with TG0 and sometimes with TG1, and every so often the board even locks up (but that's w/o any errors whatsoever). The stack pointer printed often points to a "Double Exception".

I was unable to find a clear explanation of the timer group 1 and group 0 watchdog resets. As best I could figure out it when TG1 fires it means that FreeRTOS task switching was blocked for a long time (how long?), which would prevent important interrupts from firing. This only happens at one site where the customer has many device on modbus. But not reading from some of the modbus devices didn't help matters.

Code: Select all

[2018-11-07T23:55:58.879] [ALL] USB - ���������������������;�IՁMeditatiol Error����� 0 panic'ed (D/uble epception)
[2018-11-07T23:55:58.882] [ALL] USB - Register dump:
[2018-11-07T23:55:59.876] [ALL] USB - PC      : 0x400d216a  PS      : 0x00060836  A0      : ets Jun  8 2016 00:22:57
[2018-11-07T23:55:59.877] [ALL] USB -
[2018-11-07T23:55:59.882] [ALL] USB - rst:0x7 (TG0WDT_SYS_RESET),boot:0x17 (SPI_FAST_FLASH_BOOT)
[2018-11-07T23:55:59.885] [ALL] USB - configsip: 0, SPIWP:0xee
[2018-11-07T23:55:59.890] [ALL] USB - clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
[2018-11-07T23:55:59.892] [ALL] USB - mode:DIO, clock div:2
[2018-11-07T23:55:59.932] [ALL] USB - load:0x3fff0p���f���怘�����x��xx�xx������f���f��x怘�����x������f������������x~f��������怘�����x������f��������f怘�f��`��f����fx`����`��~�x�~�������~�f�������~f~ff�xfxf~f��f�~�������f���W (74) boot: PRO CPU has been reset by WDT.
[2018-11-07T23:55:59.939] [ALL] USB - W (74) boot: WDT reset info: PRO CPU PC=0x400803c3 (waiti mode)
[2018-11-07T23:55:59.944] [ALL] USB - W (76) boot: WDT reset info: APP CPU PC=0x40084b63
Any information that can help isolate possible issues and allow for more intelligent experiments much appreciated.

ESP_Sprite
Posts: 1997
Joined: Thu Nov 26, 2015 4:08 am

Re: TG0WDT_SYS_RESET and TG1WDT_SYS_RESET

Postby ESP_Sprite » Fri Nov 09, 2018 8:04 am

That looks like a mess - are you sure the power supply to the ESP32 is sufficient?

0xffff
Posts: 34
Joined: Tue Jun 19, 2018 1:53 am

Re: TG0WDT_SYS_RESET and TG1WDT_SYS_RESET

Postby 0xffff » Fri Nov 09, 2018 4:41 pm

Thanks - I enabled brownout detection yesterday and noticed a few instances where it triggered. I've asked customer to instrument supply quality to check. Will post results if that was the issue.

0xffff
Posts: 34
Joined: Tue Jun 19, 2018 1:53 am

Re: TG0WDT_SYS_RESET and TG1WDT_SYS_RESET

Postby 0xffff » Wed Nov 14, 2018 4:36 pm

Unfortunately don't have anything definitive from the customer yet but I have now also seen this w/o the mess in a test fixture. What causes these resets?

ESP_Sprite
Posts: 1997
Joined: Thu Nov 26, 2015 4:08 am

Re: TG0WDT_SYS_RESET and TG1WDT_SYS_RESET

Postby ESP_Sprite » Thu Nov 15, 2018 7:29 am

Hard to say - as I said before, the UART output looks like a mess. I'd very much suspect the hardware here.

Who is online

Users browsing this forum: No registered users and 13 guests