Turning off interrupts on core 1

apuder
Posts: 22
Joined: Mon Mar 26, 2018 7:27 pm

Turning off interrupts on core 1

Postby apuder » Thu Jun 06, 2019 9:48 pm

Hi. I want to use core 1 to poll GPIO pins in a tight loop. In order for fastest response, I am turning off interrupts on core 1 (read this post for a rationale for doing this: viewtopic.php?f=2&t=10006). Turning off interrupts on core 1 via portDISABLE_INTERRUPTS() and disabling the Watchdog Timer is easy enough. However, this has some nasty side-effects. Some API that runs on core 0 apparently also wants to execute code on core 1 (I believe this is needed for proper synchronization of some API such as writing to NVS). Since interrupts are disabled on core 1, core 0 gets hung when using such API. I can guarantee that core 1 is not using any ESP32 API; only memory-mapped I/O to access GPIO pins. What are my options here to use APIs such as NVS on core 0 with interrupts on core 1 being disabled?
TIA,
AP

WiFive
Posts: 2390
Joined: Tue Dec 01, 2015 7:35 am

Re: Turning off interrupts on core 1

Postby WiFive » Fri Jun 07, 2019 3:56 am

I guess you would have to modify the ipc, dport access, and crosscore interrupt features and ensure you aren't violating the dport workarounds.

apuder
Posts: 22
Joined: Mon Mar 26, 2018 7:27 pm

Re: Turning off interrupts on core 1

Postby apuder » Mon Jun 10, 2019 2:53 am

If I wanted to continue to use NVS API on core 0, would it be OK to call

Code: Select all

spi_flash_guard_set(&g_flash_guard_no_os_ops);
after turning off interrupts on core 1?

ESP_igrr
Posts: 1460
Joined: Tue Dec 01, 2015 8:37 am

Re: Turning off interrupts on core 1

Postby ESP_igrr » Mon Jun 10, 2019 10:16 am

Probably not. SPI flash guards are there to guarantee that the other CPU doesn't execute instructions from Flash while the cache is disabled.

apuder
Posts: 22
Joined: Mon Mar 26, 2018 7:27 pm

Re: Turning off interrupts on core 1

Postby apuder » Mon Jun 10, 2019 2:27 pm

Forgot to mention that on core 1 I do not call any ESP-related API; only memory-mapped I/O on some GPIO pins. So I know that core 1 is not doing anything with SPI.

Who is online

Users browsing this forum: Google [Bot] and 28 guests